336 results about "Master clock" patented technology

The invention relates to the technical field of synchronization in data communication, and provides a PTP protocol-based chip-level hardware timestamp generation method and system, and the method comprises the steps: 1, receiving a synchronization message and a delay request message from a main clock, carrying out the evaluation of a physical layer signal, and recording a first hardware timestamp; 2, responding to the received delay request message, generating and sending a delay response message, acquiring bidirectional transmission delay data by exchanging the delay request and the delay response message, and calculating clock skew in combination with the first hardware timestamp and the bidirectional transmission delay data; 3, adjusting the local clock frequency according to the clock skew; 4, after the synchronization is completed, associating the second hardware timestamp with the corresponding data message, and storing the associated data in a buffer area in the chip; and 5, generating standardized timestamp information, and outputting the standardized timestamp information through a chip interface. And high-precision time synchronization and timestamp generation are realized.

The invention discloses a vehicle-mounted cross-protocol data time sequence cooperative processing method, which comprises the following steps: establishing a unified time reference, and providing an accurate space-time coordinate system for heterogeneous network nodes by electing a global master clock and constructing a clock relation model and a periodic correction mechanism; systematic cognition and management of communication resources are realized, and a verified protocol capability table is generated by automatically identifying protocol types and variants; constructing an automatic mapping system from demand to execution, performing formalized packaging on a target scene by introducing a unified intermediate model, generating a cross-protocol mapping rule based on the model and a protocol capability table, and then forming a global scheduling table in combination with a unified time reference; the cooperative communication of all nodes is finally realized by using the global scheduling table, and the end-to-end delay is constrained within the preset range, so that the problem that the end-to-end time sequence in the vehicle-mounted heterogeneous network is uncontrollable is solved, and the controllability and reliability of the time sequence of the vehicle-mounted network are improved.

The present application belongs to the technical field of communications, and discloses a clock synchronization method, a device, and a computer readable storage medium. The method comprises: selecting a master clock source inside of a base station to be a clock synchronization source of a fusion control system; on the basis of the clock synchronization source, constructing a wired synchronous master clock message and an air interface synchronous master clock message; and sending the wired synchronization master clock message to a wired connection device, and sending the air interface synchronization master clock message to a wireless connection device.

The invention provides a multi-sensor fusion robot grabbing path planning method and device, and relates to the field of automation. The method comprises the following steps: constructing a first time correction relation based on observation parameters of a multi-source sensor; correcting the relation based on the first time; inputting the hardware timestamp synchronized to the master clock source into the extended state estimation model; iteratively updating the observation parameters of the multi-source sensor based on the extended state estimation model, and constructing a second time correction relation according to the updated observation parameters of the multi-source sensor; constructing a pose continuous time trajectory function corresponding to the target robot based on the second time correction relation; the continuous time trajectory function and the multi-source sensor observation parameters serve as input, and a grabbing path corresponding to the target robot is output through a time sequence consistency constrained joint optimization model; and controlling the target robot to execute grabbing operation based on the grabbing path. The problem that in the prior art, the precision of a robot grabbing path is low is solved.

The invention relates to the technical field of network communication, in particular to a logistics equipment unified access method based on multi-protocol conversion. The specific implementation process comprises: establishing a model comprising a source logistics device, a target logistics device, a protocol conversion gateway and a time-sensitive network, wherein the time-sensitive network comprises a network master clock; the protocol conversion gateway and the network master clock are periodically synchronized, an original data packet of the source logistics equipment is analyzed, and data content and a source identifier containing a time sequence relation are extracted; through an adaptive mapping rule, mapping the data content and the source identifier into a time-sensitive network traffic category containing predetermined traffic, and obtaining a gating scheduling strategy of the time-sensitive network traffic category; and the data content is converted and packaged into a time-sensitive network data frame, and the time-sensitive network data frame is sent to the target logistics equipment according to a gating scheduling strategy. According to the invention, the access accuracy and stability of the logistics equipment are realized by fusing protocol conversion and the time-sensitive network.

The invention relates to the technical field of radar information, in particular to a satellite clock performance evaluation method for constructing a reference time benchmark based on an inter-satellite link, which comprises the following steps of: 1, collecting GNSS inter-satellite bidirectional pseudo-range observation data, establishing a bidirectional pseudo-range observation equation, reducing to the same target moment to obtain an inter-satellite relative clock error, and calculating the inter-satellite relative clock error; reducing to a main clock on a selected main satellite to obtain a clock difference of each clock relative to the initial time reference; step 2, fitting a polynomial clock error parameter by using the accumulated satellite clock error data with a certain arc length, deducting the clock error parameter from the satellite clock error epochwise, and calculating to obtain a clock error residual error; step 3, the alron variance of each satellite clock is calculated by using the clock error residual error, the stability of each clock is evaluated, and then the weight of each satellite clock is determined; 4, constructing a space-based time reference based on the clock error residual error obtained in the step 2 and the satellite clock weight determined in the step 3; and step 5, evaluating the performance of the satellite clocks based on the clock difference of each satellite clock under the space-based time reference.

The invention provides a digital clock remote metering method based on network delay suppression, which comprises the following steps of: constructing a layered synchronous architecture, deploying a main clock source, a plurality of regional clock servers and a plurality of terminal devices, connecting the plurality of regional clock servers with the main clock source through optical fiber special lines to obtain reference time, each regional clock server is connected with a plurality of terminal devices through a 5G / industrial Ethernet to form a three-level synchronous network; rTT data of the terminal device and a regional server are obtained through bidirectional timestamp interaction, and message screening is carried out according to a preset rule; calculating a final time delay compensation value by adopting a mixed time delay compensation algorithm, and calibrating a terminal clock by adopting the final time delay compensation value; and adopting a time selection algorithm to obtain an optimal reference source for data synchronous analysis. According to the invention, the time deviation problem between the current time indicating value of the digital clock and the standard time and the data synchronization analysis problem can be solved.

The invention discloses an SLAM-oriented multi-sensor space-time synchronization and online calibration method, and relates to the technical field of computer vision and robot perception. Comprising the steps that S100, initialization is carried out, and an initial pose and an external parameter transformation matrix initial value are obtained through coarse alignment; s200, data acquisition and preprocessing: acquiring IMU data, LiDAR data and Odom data in real time, and performing data filtering, distortion removal, time sequence correction and point cloud downsampling processing on the acquired data; and S300, performing time synchronization processing, estimating the time offset of the LiDAR and Odom data in real time, and performing unified correction to generate a unified timestamp. According to the method, an online time offset estimation and compensation mechanism with an IMU as a main clock is established, accurate synchronization of sensor data of different frequencies is achieved, and the problem of data alignment caused by sampling frequency difference and clock drift is effectively solved; and meanwhile, tight coupling fusion is realized by using an IMU pre-integration factor, a LiDAR residual factor and an Odom constraint factor, so that the space-time consistency of multi-sensor data is remarkably improved.

The invention provides a large-scale computing power cluster-oriented resource collaboration and time synchronization method and system, and relates to the technical field of computing power network architecture. Firstly, resource registration and state maintenance are carried out on a computing power node through an authoritative DNS; after a task is received, the system intelligently selects an optimal target computing power node and plans a data transmission path; in order to realize accurate collaboration, the system dynamically creates a clock synchronization domain according to a task, elects a master clock and plans an optimal clock synchronization path; and finally, the system encapsulates and packs the optimal task data transmission path, the main clock timestamp and the optimal clock synchronization path identifier, and distributes the data to related nodes, so that efficient coordination and high-precision time synchronization of resources are realized. According to the method, optimal matching of tasks and resources is achieved, the high efficiency of data transmission is guaranteed, the precision and reliability of time synchronization are guaranteed from a physical link, and finally efficient coordination and high-precision time synchronization of the resources in the computing power cluster are achieved.

The invention relates to the technical field of vehicle-mounted integrated navigation, in particular to a double-clock synchronization IMU error correction method and system fused with 5G communication. The method comprises the following steps: acquiring a GNSS main clock signal, an auxiliary clock signal and a 5G communication clock signal, and establishing a unified time reference system; constructing a transverse speed prediction model to predict a transverse movement track in the high-speed lane changing process of the vehicle, and combining the transverse movement track with IMU inertial measurement data to calculate a transverse offset residual error of the vehicle; inputting the lateral offset residual error, the lane center line offset, the steering wheel angle data and the yaw velocity data of the vehicle into the improved error risk prediction neural network model for joint processing; and correcting the vehicle navigation state data in real time by using an extended Kalman filter. According to the invention, the 5G communication and GNSS double clock sources are fused in the vehicle high-speed lane changing scene, and high-precision IMU error correction of vehicle lane changing navigation state correction is carried out.

The invention provides a multi-sensor domain controller dynamic management method and a domain controller system, and the method comprises the following steps: S1, taking an external Ethernet gateway as a main clock source, and carrying out the time service of an MCU module in a domain controller based on a GPTP protocol; s2, the MCU module serves as a secondary clock source, distributes synchronous clock signals to the SOC module and an external sensor and collects clock skew data in real time; s3, when the main clock source fails, automatically switching to an internal GNSS module and an IMU module as standby clock sources, and dynamically compensating a time sequence error based on historical clock skew data; s4, controlling a global time synchronization error to be less than 150 microseconds through hardware-level timestamp marking and a software-level error correction algorithm; and S5, based on the synchronized time sequence data, performing timestamp alignment and fusion on the heterogeneous data input by the multiple sensors. According to the invention, the problems of clock redundancy and insufficient error compensation in the prior art are solved.

The invention discloses an audio and video acquisition synchronous management method, and relates to the technical field of data synchronization. The method is executed by main control equipment and comprises the following steps: S1, acquiring a satellite time reference through a dual-mode time service module; s2, based on the pulse signal of the temperature compensated crystal oscillator, a master clock signal is generated according to a formula Tmaster = TGPS + alpha delta T + beta (delta f / f0), TGPS is a satellite time reference, alpha is a temperature compensation coefficient and ranges from 0.2 to 0.8, and beta is a frequency drift correction factor; s3, establishing an inter-device time synchronization communication link through an IEEE 1588PTP protocol, and broadcasting a synchronization pulse by the main control device; s4, the data buffer area is adjusted in real time according to the dynamic buffer control formula D (t) = D0 + k1 * (delta t) 2 + k2 * d delta t / dt, k1 = 0.15 ms-2, and k2 = 2.5 ms2 / s; s5, when the network time delay gt is detected; and at 150ms, switching to a local clock compensation mode, and triggering the extended Kalman filter to re-correct the clock parameters. According to the invention, a hybrid synchronization architecture with local clock correction capability is constructed, and self-adaptive time difference compensation without network dependence is realized.

Disclosed are a system on chip, method and device supporting time synchronization, and a storage medium, which relate to the technical field of time synchronization, the system on chip synchronizes the time of an STBM in the system on chip with the time of an off-chip master clock through a first processor core according to a first preset period; based on the first time of the STBM after time synchronization, calibrating a hardware clock of the first network card to obtain a first time reference; calibrating the time of the STBM based on the first time to obtain a second time reference; synchronizing, by the second processor core, the time of the second network card with the time of the first time reference based on a first time difference between the first network card and the second network card; and synchronizing the system time with the time of the second time reference based on a second time difference between the second time reference and the system time of the operating system. According to the system, double time references can be obtained, sub-microsecond-level synchronization precision is realized, and the strict requirement of a high-precision time synchronization scene on time synchronization precision is met.

A method for synchronizing an analog-to-digital converter, ADC, the method comprising: stopping, by a processor, a master clock signal to the ADC to pause sampling of the ADC, the master clock signal being supplied by an external master clock to the ADC; detecting, by the ADC, that a synchronization event has occurred whilst the master clock is stopped; restarting, by the processor, the master clock signal to the ADC; resetting, by the ADC, an internal filter at a time that is synchronous with the master clock; and resuming, by the ADC, sampling in response to resetting the internal filter of the ADC.

The invention provides a vehicle-mounted time synchronization method and device, and the method is applied to a vehicle-mounted network, and comprises the steps: obtaining the topology of the vehicle-mounted network, and determining a master clock and slave equipment according to the topology of the vehicle-mounted network; wherein the master clock and the slave device are connected through a network interface supporting a precise time protocol; broadcasting a synchronization message to the slave device through a preset frequency by using the master clock, wherein the synchronization message at least comprises a first timestamp of a moment when the synchronization message leaves the master clock through the network interface; receiving the synchronization message by using the slave device, and determining a second timestamp of the moment when the synchronization message reaches the slave device through the network interface; and pre-determining propagation delay, determining clock skew of the slave device according to the first timestamp, the second timestamp and the propagation delay, and synchronizing a local clock of the slave device according to the clock skew. The synchronization delay is avoided, and the time synchronization efficiency is improved.

Described is a method of synchronizing a TSN NW-TT module inside a UPF with a Grandmaster (GM) in a Time Domain of the communication network. The method comprises receiving one or more PTP or gPTP messages on an N3 interface of the UPF. The method includes determining a first time offset value between the GM and the UPF N3 interface based on information received in the PTP or gPTP messages. A timing of the UPF N3 interface is adjusted using the determined first time offset value to synchronize the time between the UPF N3 interface and the GM. The method includes determining a second time offset value between the UPF N3 interface and the NW-TT module. A timing of the NW-TT module is adjusted using the determined second time offset value to synchronize the time between the NW-TT module and the GM.

The invention discloses a clock processing method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of communication, and the method comprises the steps: building a cross-domain clock based on a main clock in a digital circuit; setting a first delay constraint for the cross-domain clock based on a preset delay threshold; the Gray code path is determined in the time sequence path corresponding to the cross-domain clock, and the first delay constraint is adjusted based on the clock frequency of the cross-domain clock to obtain the second delay constraint, so that the problems that the requirements of different types of time sequence paths on path constraints are often different, and if the constraints are not distinguished when the time sequence paths are designed, the time sequence paths cannot be designed are solved. The technical problem that the power consumption of the digital circuit is increased due to the fact that a design tool may add more buffers on a path or enhance the driving capability of the buffers is solved, and the technical effect of reducing the power consumption of the digital circuit to a certain extent on the premise of ensuring the time sequence requirement of the cross-clock domain is achieved.

The invention discloses a Beidou PTP master clock device based on chip atomic clock timekeeping, which integrates a chip atomic clock and a Beidou satellite time service signal, and comprises the following steps: firstly, receiving a Beidou satellite signal through a satellite receiving module, and generating an accurate 1PPS signal, a TOD signal and a 10MHz frequency signal based on the satellite signal; high-precision time-frequency reference is provided for equipment, and the problem that clock precision is insufficient in a traditional clock synchronization system is solved through the design. Secondly, the first clock board and the second clock board carry chip atomic clocks, and the high stability and low power consumption characteristics of the chip atomic clocks enable the equipment to maintain high precision of clock signals during long-time operation, so that clock errors caused by crystal oscillator frequency drift and aging in a traditional system are avoided. Moreover, the communication core board is connected with the upper computer, so that instructions can be received in real time, and the clock board and the logic control board can be controlled to work, and therefore, the system can quickly respond to the instructions of the upper computer, and accurate time control can be realized.

A clock synchronization method is disclosed. The method comprises receiving master timing synchronization data from a master clock device, wherein the master timing synchronization data is based at least in part on quantum data obtained from a first quantum device of the master clock device. The method comprises determining local timing synchronization data that is based at least in part on local quantum data obtained from a second local quantum device, wherein the second local quantum device is entangled with the first quantum device such that the local quantum data and the quantum data obtained from the first quantum device are identical at a same time. The method comprises using the determined local timing synchronization data and the received master timing synchronization data to determine a timing correction factor. The method comprises correcting a local system time using the timing correction factor.

Aspects of the subject disclosure may include, for example, a device, including: a processing system including a processor; a clock; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: advertising via Border Gateway Protocol (BGP) a capability as a precision timing protocol (PTP) master clock through an Internet Protocol (IP) / Multi-Protocol Label Switching (MPLS) network, wherein the advertising includes an IP address of the device; receiving a unicast signaling mechanism from a PTP client node in the network; and sending clock messages to the PTP client node responsive to accepting the PTP client node. Other embodiments are disclosed.

The present invention provides a distributed precise time acquisition method based on the TTP bus, which is applied to an unmanned aerial vehicle embedded system and includes: using the satellite receiver node with a fault tolerance mechanism in the embedded system as the master clock node, and using the remaining nodes in the embedded system as backup master clock nodes; communicatively connecting the master clock node and the backup master clock nodes through the TTP bus; correcting the local clocks of each node by using a distributed clock synchronization method; and acquiring the local UTC time of each node at the current moment by using a distributed precise time acquisition method. The method of the present invention can obtain a high-precision local clock for each node without adding a high-precision crystal oscillator to other nodes except the satellite receiver node, and each node can acquire the local UTC time at the current moment through the distributed precise time acquisition method based on the satellite receiver.

A test device tests conditions associated with a fronthaul in an Open Radio Access Network (O-RAN). The test device can field test an O-RAN radio unit (O-RU) installed at a cell site by emulating an O-RAN distributed unit (O-DU) in the O-RAN connected to the O-RU via the fronthaul of the O-RAN. The testing includes executing managing plane (M-plane) and synchronization plane (S-plane) messaging to test management session establishment, device setting testing, and master clock synchronization testing.

The invention relates to the field of time synchronization, and discloses a time synchronization method and device based on a base station, communication equipment and a medium, and the time synchronization method based on the base station comprises the steps: obtaining initial clock reference information, transmitting the information to an adjacent base station through an IEEE1588 protocol, and forming a candidate synchronization signal. And based on the candidate synchronization signals, selecting an optimal master clock from the adjacent base stations by adopting an optimal master clock algorithm, and taking the time of the selected master clock as standard time. And based on the selected standard time, the standard time is issued to the whole base station network through cascade transmission among the multiple stages of base stations, so that each base station can perform periodic correction based on the standard time, thereby ensuring unification and accurate synchronization of clocks of the whole network. According to the time synchronization method based on the base stations, the clock synchronization precision between the base stations is effectively improved, clock drift and errors are reduced, and stable operation of the base stations in a complex environment is ensured.

A method of synchronizing a network side time sensitive network (TSN) converter (NW-TT) module within a user plane function (UPF) in a communication network with a master clock (GM) in the 5G time domain of the communication network is described. The method comprises the step of adjusting the clock frequency of an N3 interface to enable the N3 interface to be synchronized with the clock of a GM. The method includes generating one or more pulses on a pin of the N3 interface. The method includes detecting the one or more pulses on a pin of the NW-TT module. The method includes determining a time offset value (Offset NW-TT) between the N3 interface and the NW-TT module. The method includes adjusting a time or clock frequency of the NW-TT module using a determined time offset value (Offset NW-TT), thereby enabling time synchronization of the NW-TT module and the GM.

The invention provides a data processing method and device, a storage medium and a program product, and the method comprises the steps: a control device carries out the clock synchronization calibration of a plurality of camera devices according to a main clock, and synchronously sends a preset control signal to the plurality of camera devices; after receiving a preset control signal sent by the control device, each camera device synchronously generates a key frame in response to the preset control signal, encodes and generates video stream data carrying a key frame generation timestamp, and then sends the video stream data taking the key frame as an initial frame to the control device; and the control equipment stores the multi-channel video stream data with the same timestamp from the plurality of camera devices into the same time slot to obtain a multi-channel data block, and generates and stores a time slot index anchor point for querying the multi-channel data block, so that the corresponding multi-channel data block is queried based on the time slot index anchor point subsequently for video playback. The synchronization of the multi-channel video can be effectively guaranteed, the video playback error is reduced, and the multi-channel video playback synchronization precision is improved.

In one embodiment, a system includes a peripheral device, which includes an interface to receive from a virtual machine (VM) running on a host device, over a communication data bus, a request for timing data derived from a time measurement dialogue, the host device maintaining a master clock time, a hardware clock to maintain a peripheral device clock time, and processing circuitry to transform the master clock time to a frame of reference of the VM, and provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM.

The invention discloses a sensor network time synchronization method, which comprises the following steps: firstly, clustering and networking sensor nodes according to equipment to which the sensor nodes belong, and for clusters, fusing clock frequency offset between a quantized master control clock signal and a cluster head node into an improved TPSN protocol to dynamically calibrate a logic clock of the cluster head node; and for the interior of the cluster, calibrating the logic clock of the child node in the cluster based on the clock drift amount and the clock offset amount of the cluster head node and the child node in the cluster. According to the method, the characteristics of a power equipment monitoring scene are combined, and a dynamic hierarchical adjustment mechanism and a bidirectional calibration strategy are introduced, so that the time-varying influence of frequency deviation on the synchronization error can be remarkably suppressed, and the adaptability to network topology change is improved.

The invention discloses a time synchronization method, device and equipment and a storage medium, relates to the technical field of time synchronization, is applied to a first target system configured with an application processing unit and a first clock source, and comprises the following steps: acquiring a clock selection message sent by a second target system by using a preset clock information sending program; a real-time processing unit and a second clock source are configured in the second target system, and the clock selection message is generated by the second target system based on clock information of the second clock source; determining master clocks of the first target system and the second target system based on the clock information of the first clock source and the clock information of the second clock source in the clock selection message; and performing time synchronization between the main clock and the second target system by using the main clock and based on a locally preset time synchronization compensation value. By removing the dynamic field in the clock selection message of the real-time processing unit, the clock selection message is simplified, so that cross-domain time synchronization can be realized between the real-time processing unit and the application processing unit.

Communication systems and methods are disclosed herein. In an embodiment, a communication system includes a grandmaster clock and a modem unit. The grandmaster clock is configured to output a primary clock reference based on a received signal. The modem unit is configured for communication with a remote terminal. The modem unit includes a network clock configured to be tuned based on the primary clock reference. The network clock is further configured to output a first signal to be used for a time reference for communications with the remote terminal. The modern unit also includes a master clock configured to be tuned based on the primary clock reference. The master clock is further configured to output a second signal to be used for a frequency reference for communications with the remote terminal.

A method for synchronizing an analog-to-digital converter, ADC, the method comprising: stopping, by a processor, a master clock signal to the ADC to pause sampling of the ADC, the master clock signal being supplied by an external master clock to the ADC; detecting, by the ADC, that a synchronization event has occurred whilst the master clock is stopped; restarting, by the processor, the master clock signal to the ADC; resetting, by the ADC, an internal filter at a time that is synchronous with the master clock; and resuming, by the ADC, sampling in response to resetting the internal filter of the ADC.