156 results about "Master clock" patented technology

The invention discloses a vehicle-mounted cross-protocol data time sequence cooperative processing method, which comprises the following steps: establishing a unified time reference, and providing an accurate space-time coordinate system for heterogeneous network nodes by electing a global master clock and constructing a clock relation model and a periodic correction mechanism; systematic cognition and management of communication resources are realized, and a verified protocol capability table is generated by automatically identifying protocol types and variants; constructing an automatic mapping system from demand to execution, performing formalized packaging on a target scene by introducing a unified intermediate model, generating a cross-protocol mapping rule based on the model and a protocol capability table, and then forming a global scheduling table in combination with a unified time reference; the cooperative communication of all nodes is finally realized by using the global scheduling table, and the end-to-end delay is constrained within the preset range, so that the problem that the end-to-end time sequence in the vehicle-mounted heterogeneous network is uncontrollable is solved, and the controllability and reliability of the time sequence of the vehicle-mounted network are improved.

The invention discloses an SLAM-oriented multi-sensor space-time synchronization and online calibration method, and relates to the technical field of computer vision and robot perception. Comprising the steps that S100, initialization is carried out, and an initial pose and an external parameter transformation matrix initial value are obtained through coarse alignment; s200, data acquisition and preprocessing: acquiring IMU data, LiDAR data and Odom data in real time, and performing data filtering, distortion removal, time sequence correction and point cloud downsampling processing on the acquired data; and S300, performing time synchronization processing, estimating the time offset of the LiDAR and Odom data in real time, and performing unified correction to generate a unified timestamp. According to the method, an online time offset estimation and compensation mechanism with an IMU as a main clock is established, accurate synchronization of sensor data of different frequencies is achieved, and the problem of data alignment caused by sampling frequency difference and clock drift is effectively solved; and meanwhile, tight coupling fusion is realized by using an IMU pre-integration factor, a LiDAR residual factor and an Odom constraint factor, so that the space-time consistency of multi-sensor data is remarkably improved.

A method of synchronizing a network side time sensitive network (TSN) converter (NW-TT) module within a user plane function (UPF) in a communication network with a master clock (GM) in the 5G time domain of the communication network is described. The method comprises the step of adjusting the clock frequency of an N3 interface to enable the N3 interface to be synchronized with the clock of a GM. The method includes generating one or more pulses on a pin of the N3 interface. The method includes detecting the one or more pulses on a pin of the NW-TT module. The method includes determining a time offset value (Offset NW-TT) between the N3 interface and the NW-TT module. The method includes adjusting a time or clock frequency of the NW-TT module using a determined time offset value (Offset NW-TT), thereby enabling time synchronization of the NW-TT module and the GM.

A method for synchronizing an analog-to-digital converter, ADC, the method comprising: stopping, by a processor, a master clock signal to the ADC to pause sampling of the ADC, the master clock signal being supplied by an external master clock to the ADC; detecting, by the ADC, that a synchronization event has occurred whilst the master clock is stopped; restarting, by the processor, the master clock signal to the ADC; resetting, by the ADC, an internal filter at a time that is synchronous with the master clock; and resuming, by the ADC, sampling in response to resetting the internal filter of the ADC.

The invention discloses a multi-sensor monitoring system and method based on time alignment, and belongs to the technical field of multi-sensor monitoring, and the system comprises a sensor collection module which is used for obtaining an electrocardiosignal, a photoelectric volume pulse wave signal, a heart sound signal and a respiratory impedance signal containing a main clock receiving timestamp; the time alignment module is used for performing acquisition time alignment on the electrocardiosignal, the pulse oximeter signal, the heart sound signal and the respiratory impedance signal containing the main clock receiving timestamp to form the electrocardiosignal, the pulse oximeter signal, the heart sound signal and the respiratory impedance signal which are in time alignment; the multi-modal fusion analysis module is used for extracting local morphological features in the electrocardiosignal, the pulse oximeter signal, the heart sound signal and the respiratory impedance signal after time alignment to form a feature map, and extracting dynamic weights between different signals and between different time points / features in the same signal; according to the invention, the interpretability and accuracy of judgment are improved.

The present application relates to wafer transfer equipment technical field, in order to solve how to realize the reasonable collaborative control of RGV and box opening mechanism technical problem, provide a kind of system and method for controlling RGV and box opening mechanism collaborative operation, the system includes RGV, box opening mechanism and control center, control center receives the sensor data of RGV by first communication link, and receives the sensor data of box opening mechanism by second communication link, and sends control instruction to RGV by first communication link, and sends control instruction to box opening mechanism by second communication link, to realize the collaborative control of RGV and box opening mechanism, wherein, control center continuously obtains the first clock signal of itself, and continuously obtains the second clock signal of RGV and the third clock signal of box opening mechanism, control center selects one from first, second and third clock signals as the master clock signal of system in each control period and carries out time alignment.

The application provides a substation-oriented anchor point timestamp calibration method and related device, which is applied to a collection terminal in a substation monitoring system, the substation monitoring system further comprises a master clock and a sensor in communication connection with the collection terminal, and the method comprises the following steps: determining a drift parameter of a local crystal oscillator of the collection terminal according to a clock offset sequence between the collection terminal and the master clock in a plurality of continuous synchronization periods; correcting a sampling counter in the collection terminal by using the drift parameter; if a transient partial discharge signal is detected according to a data frame sequence collected by the sensor on a target metal pipeline in the substation, a dynamic anchor point is established at a triggering moment of the transient partial discharge signal; and based on the dynamic anchor point, the generated sampling count sequence after correction and a time reference of the collection terminal, a data frame related to the transient partial discharge signal in the data frame sequence is timestamped. The accuracy of timestamping is improved.

The invention provides a time synchronization method and equipment for a hybrid PTP protocol network. The method comprises the following steps: setting a first PTP port to be a full-path time transmission PTP protocol and belong to a first PTP domain; the second PTP port is set to be a partial path time transmission PTP protocol and belongs to a second PTP domain; a first PTP notification message is received through the first PTP port; a second PTP notification message is received through a second PTP port; based on an optimal master clock algorithm, comparing the priorities of the first PTP notification message and the second PTP notification message, and electing a master port and a slave port from the first PTP port and the second PTP port; and packaging and sending the optimal clock information of the PTP notification message received by the master port and the PTP domain to which the PTP notification message belongs according to the PTP protocol standard of the slave port.

The application discloses a kind of high-precision Beidou time service master clock devices based on double-chip atomic clock fusion, it relates to timing synchronization technical field, the device includes satellite receiving module, master control processing module, double-chip atomic clock module, clock taming module, time-frequency output module, display control module and power module;Each module is cooperated by work mode automatic switching mechanism Work;Double-chip atomic clock module adopts two pieces chip level atomic clock and constitutes master-slave redundant architecture, and the phase and frequency deviation information of main atomic clock and slave atomic clock are fused and mutually checked by extended Kalman filtering;The taming algorithm in clock taming module is formed by extended Kalman filtering link, PID controller link, digital phase-locked loop link cascade;Work mode automatic switching mechanism is according to the automatic switching of work mode according to the operating state of the device;Overcome the insufficient of time service precision, low reliability, taming algorithm performance is limited and so on in prior art.

The invention relates to a method for synchronizing a clock signal (CLK) with a reference clock (RCLK), wherein the clock signal is obtained on the basis of a local master clock and an adjustable frequency multiplication factor. The method utilizes a master clock signal to synchronize a frequency multiplication factor to compensate for frequency deviation. In a data packet gap of communication standards such as Bluetooth, corresponding signals are transmitted and received.

The application relates to the technical field of surveying and mapping geographic information, and discloses a surveying and mapping intelligent analysis system based on multi-source data fusion, which comprises a multi-source acquisition and space-time reference alignment module, a factor graph consistency fusion and gate module and the like. The multi-source acquisition and space-time reference alignment module is configured to lock a main clock source through a hardware timing protocol, set a hard time alignment threshold, receive multi-source sensor data, judge a time synchronization deviation fed back by the sensor, and output original observation data flow when the time synchronization deviation is lower than the hard time alignment threshold. The factor graph consistency fusion and gate module is configured to receive the original observation data flow and build a global factor graph containing a full-source data constraint chain. The hardware timing protocol locking and hard time alignment threshold mechanism are adopted to establish a unified space-time reference at a physical level from the source, eliminate spatial misplacement caused by sensor sampling differences, realize high-precision consistency fusion of multi-source data, and solve the problems of difficulty in determining deviation sources and low fusion efficiency in traditional technologies.

The invention relates to a time synchronization system and method of a TSN train communication network. The system comprises a backbone network clock domain, a marshalling network clock domain and an intermediate clock domain formed by connecting backbone network nodes and marshalling network nodes, the two backbone network clock domains receive the same external clock source through each autonomous clock node to realize time synchronization, and provide a unified time reference for each marshalling network clock domain; under the condition that the time synchronization of the clock domain of the backbone network is abnormal or invalid, the backbone network node sends a synchronization abnormal signal to the marshalling network node of the intermediate clock domain where the backbone network node is located; the marshalling network clock domain is used for realizing time synchronization of equipment supporting the TSN in the marshalling network; under the condition that the synchronization abnormal signal is received, the marshalling network node of the middle clock domain does not enable the time synchronization function, so that the backbone network clock domain is isolated from the marshalling network clock domain where the marshalling network node is located. The problem that large-area synchronization abnormity of the whole vehicle may be caused once the time synchronization of the backbone network fails is solved.

This invention relates to a method for optimizing synchronization accuracy in end-to-end transmission mode clock synchronization systems. First, the master and slave nodes within the clock synchronization system exchange PTP messages in end-to-end transmission mode according to the IEEE 1588 Precision Clock Protocol. The slave node obtains the timestamps and transmission delays recorded in each PTP message. Then, the slave node uses a filtering algorithm to process the forward and reverse transmission delays. Combining this with the clock offset calculation formula in the IEEE 1588 Precision Clock Protocol, the clock offset between the slave node and the master clock is calculated using the timestamps in the PTP messages and the processed transmission delays. Finally, the calculated clock offset is used to adjust the local clock. This invention solves the problem of asymmetric delays during message transmission affecting the clock synchronization accuracy between the master and slave nodes in end-to-end transmission mode clock synchronization systems, improving the time synchronization accuracy between devices in network communication systems and having broad application prospects.

The invention provides a clock interruption method and device. The clock interruption device comprises a PTP timestamp module, a TSN flow scheduling module, a local clock crystal oscillator, an interruption controller and an external equipment interface. The method comprises the following steps: a PTP timestamp module receives a PTP protocol message periodically sent by a main clock, and generates a calibration signal according to the PTP protocol message to calibrate a local clock crystal oscillator; the local clock crystal oscillator outputs a calibrated local clock signal to the PTP timestamp module and the TSN flow scheduling module; the TSN flow scheduling module sends the interrupt trigger signal to an interrupt controller according to a corresponding time window in a predefined gating list according to a local clock signal; and the interrupt controller generates an interrupt signal according to the interrupt trigger signal and sends the interrupt signal to the external equipment through the external equipment interface. In this way, fusion of high-precision time synchronization and high-determinacy transmission is achieved through deep cooperation of the PTP and the TSN on three levels of hardware architecture, scheduling logic and an interrupt mechanism.

The invention relates to the technical field of internal clock correction of an intelligent fusion terminal, in particular to a self-adaptive clock synchronization method for the intelligent fusion terminal, which comprises the following steps: S1, acquiring a plurality of clock synchronization sources and corresponding quality characteristic parameters thereof; s2, calculating a corresponding comprehensive quality score, and selecting a clock synchronization source with the highest comprehensive quality score as a main clock source; s3, calculating the time deviation between the internal clock of the intelligent fusion terminal and the main clock source, and if the time deviation exceeds a deviation threshold value, correcting the internal clock of the intelligent fusion terminal through the main clock source; s4, calculating a clock drift rate between a current corrected value and a previous corrected value of the internal clock of the intelligent fusion terminal, if the clock drift rate exceeds a drift rate threshold value, triggering main clock source switching, and returning to the step S2; and S5, periodically executing the step S2, and dynamically updating the main clock source. According to the invention, the flexibility, reliability and stability of clock synchronization of the intelligent fusion terminal can be improved.

The application provides a five-port chip, comprising: a clock module, configured to form a synchronous clock according to an external clock input by a main clock port; a data input module, connected to an output end of the clock module, configured to receive configuration differential data input by a main data positive port and a main data negative port under control of the synchronous clock and convert the configuration differential data into configuration information and store the configuration information; a main module, connected to an output end of the data input module, configured to read the configuration information, perform chip configuration, and generate data to be transmitted under control of a system clock; and a data output module, connected to the output end of the clock module and the output end of the main module, configured to convert the data to be transmitted into differential data to be transmitted, and output the differential data to be transmitted through the main data positive port and the main data negative port in a set frame format based on the synchronous clock. The five-port chip provided by the application solves the problem of poor anti-interference capability of an existing image sensor chip in a data transmission process.

A communication system includes a primary clock device having a precision clock and configured to transmit pulse signals at a constant rate. The communication system further includes a plurality of agent devices, each agent device comprising an internal timestamp control loop, a timestamp generator configured to update timestamps at an adjustable increment rate, and control logic configured to synchronize the agent device with the primary clock device using the internal timestamp control loop. The control logic enables each agent device to maintain synchronization with the primary clock device by adjusting the adjustable increment rate based on timing differences between estimated and actual signal reception times.

A wireless communication system comprises repeater nodes that serve as a wireless repeater network, where the wireless repeater network comprises a chain of repeater nodes that wirelessly repeat a data signal within the repeater network as millimeter wave wireless signals based on equalizations of time-shifted representations of the data signal. A first repeater node in the chain uses a satellite clock signal as a master clock for maintaining phase coherency among the repeater nodes of the chain.

The application provides a resource coordination and time synchronization method and system for a large-scale computing power cluster, and relates to the technical field of computing power network architecture. First, the computing power nodes are registered and maintained by an authoritative DNS. After receiving a task, the system intelligently selects the optimal target computing power node and plans the data transmission path. To achieve precise coordination, the system dynamically creates a clock synchronization domain according to the task, elects a master clock and plans the optimal clock synchronization path. Finally, the system encapsulates and packages the optimal task data transmission path, the master clock timestamp and the optimal clock synchronization path identifier, and distributes them to the related nodes, thereby realizing efficient resource coordination and high-precision time synchronization. The method not only realizes the optimal matching of tasks and resources, guarantees the efficiency of data transmission, but also guarantees the accuracy and reliability of time synchronization from the physical link, and finally realizes efficient resource coordination and high-precision time synchronization in the computing power cluster.

The invention discloses an integrated voice-video collaborative perception all-in-one machine interaction system, which comprises a camera module, a microphone array module, a loudspeaker module, a processor module and a memory module, and is characterized in that the processor module is configured to execute the following steps: S1, processing an audio signal acquired by the microphone array module, obtaining sound source direction information and carrying out voice activity detection; s2, processing a video frame collected by the camera module, detecting and tracking a face or human body area of at least one target, and extracting mouth motion features; s3, based on a unified master clock, stamping unified timestamps on the audio data in the S1 and the video data in the S2 to realize cross-modal time synchronization; the method has the advantages that audio and video bimodal information is deeply integrated, fusion decision making is carried out under the unified time reference, and therefore stable, accurate and self-adaptive spokesman tracking and video composition are achieved.

This utility model discloses a signal hub board and a grid screen control system for a mesh screen. The signal hub board includes an input interface, multiple output interfaces, and a signal distribution circuit. The input interface receives a drive signal from a receiving card, which includes a master clock signal and multiple parallel data signals. The signal distribution circuit includes a clock buffer module and a data buffer module. The clock buffer module receives the master clock signal and, through buffering and copying, generates multiple output clock signals that are the same number as the number of output interfaces and synchronized with the phase. The data buffer module buffers the multiple parallel data signals one-to-one to generate multiple output data signals. Each output clock signal is paired with its corresponding output data signal and sent to a single mesh screen module through the corresponding output interface. The signal hub board and control system of this application improve signal quality by centrally synchronizing and shaping the drive signals, thereby ensuring that the mesh screen can achieve smooth, clear, and high-quality video playback.

The present disclosure relates to a semiconductor device and a method of operating a semiconductor device. The semiconductor device includes a charge pump circuit configured to generate an output voltage by pumping an input voltage according to a first master clock and a second master clock; a voltage detection circuit configured to generate a comparison signal by comparing the output voltage with a reference voltage; and a drive control circuit configured to: selectively invert the first external clock and the second external clock at a start time of an active period of the comparison signal to receive the inverted clocks as first internal clocks and second internal clocks; generate the first master clock and the second master clock according to the first internal clocks and the second internal clocks while controlling a transition order such that the second master clock transitions after the first master clock transitions during the active period of the comparison signal; and store logic levels of the first master clock and the second master clock as a first preliminary clock and a second preliminary clock, respectively, at an end time of the active period of the comparison signal.

Adaptive slope compensation circuit in a current-mode controlled DC-DC switching converter, comprising: a compensation ramp (840, 810) having two or more zones (Period1, Period2), each zone having a specific slope value (805, 815, 825, 820, 830), configured to respond to a duty cycle, and configured to maintain a maximum ramp current contribution for all values ​​of an output voltage at one end of a switching period, or for one-times > 50% of a total switching cycle time Tpd, to maintain a constant offset value at an application point for all values ​​of the output voltage, with a clock in antiphase to the main clock being provided to control the switching of the compensation ramp (840, 810).

The invention relates to the technical field of satellite time service, in particular to an electric power communication clock verification method, system and device based on Beidou B2b and a medium. A main clock obtains local time according to time zone setting, receives Beidou signals and obtains observation data, broadcast ephemeris and Beidou signal correction information based on the received Beidou signals; extracting a satellite orbit and a clock error correction number based on the Beidou signal correction information, correcting a broadcast ephemeris based on the extracted clock error correction number, obtaining a precise satellite orbit and a clock error, and performing data preprocessing on observation data; constructing an observation equation based on the preprocessed observation data, the precise satellite orbit and the clock error, and obtaining the deviation between the local time of the master clock and the standard time through a parameter estimation method; and based on the obtained deviation between the local time of the master clock and the standard time, the master clock sends the time code to the power system equipment, and the power equipment performs time verification according to the time code, so that the time consistency and the operation stability of the power communication system are improved.

The invention provides a low-delay feedback communication system and a low-delay feedback communication method based on an FPGA (Field Programmable Gate Array), which allow data transmission to be started under any master clock without dead time. Meanwhile, received data are allowed to be automatically used for correcting the delay shift value in real time, manual setting is not needed, appropriate calibration parameters can be obtained only through two-layer circulation in the calibration process used for achieving delay self-calibration, the logic occupation amount is small, applicability is high, use is easy, convenient and reliable, and the method is suitable for large-scale popularization and application. The low-delay feedback is allowed to be realized in a simple and reliable manner. Particularly, by means of a specific calibration parameter valuing mode, the stability of correctly receiving data is further improved, and implementation of the low-delay feedback process is facilitated. Besides, in the invention, the transmission requirement of communication data can be met only by using a pair of differential signal lines, and a source synchronous clock (namely a channel associated clock) does not need to be sent.

This invention relates to a data acquisition system based on an ADC chip for use in power detection equipment. The system includes a data acquisition circuit that acquires voltage and current traveling wave signals, performs signal conditioning, impedance matching, and differential drive processing; an ADC chip that performs analog-to-digital conversion on the signals output from the data acquisition circuit; an FPGA chip that receives digital signals, performs buffering, processing, and digital filtering operations, extracts the characteristics of power frequency signals and traveling wave signals in the power system, and performs data synchronization processing; and a CNV processing circuit that performs synchronization processing and edge shaping on the system master clock signal, outputting a synchronization signal to the FPGA to keep the sampling timing of the ADC chip synchronized with the system master clock. This invention converts the system master clock and drives the ADC sampling trigger path, achieving system-wide clock unification. After buffering and trigger shaping, the CNV signal has sharp edges and low jitter, suitable for high-speed ADC sampling. During long-term operation, the sampling points will not drift relative to the system clock, facilitating multi-module data alignment and synchronization processing.

The invention provides an image data display system and method, electronic equipment and a storage medium. Wherein the display system transmits data through a serial peripheral interface (SPI) bus, the display system comprises a master device and a slave device, the master device comprises a data input circuit, a data output circuit and a serial clock circuit, the serial clock circuit comprises a phase-locked loop circuit, the slave device comprises a display device, and the master device acquires image data to be transmitted; the phase-locked loop circuit is used for increasing the original main clock frequency of the serial clock circuit; the main device carries out coding and signal enhancement processing on the image data and transmits the processed image data; the master device dynamically performs signal shaping on a master clock signal output by the serial clock circuit; and the display device performs decoding and time sequence matching on the received image data and then displays the image data. According to the method, the display effect of the image data can be improved on the basis that an existing SPI display screen is not changed or changed at low cost.

The invention relates to the technical field of communication, discloses an electromagnetic spectrum abnormal signal monitoring method and system based on double acquisition and comparison, and aims to solve the problems of asynchronous double-channel sampling and high abnormal signal omission ratio and false alarm rate caused by clock drift and physical path delay in the prior art. According to the method, a hardware-level self-adaptive clock synchronization compensation circuit is constructed, clock path delay is quantized and offset in real time before analog-to-digital conversion, and a first sampling clock and a second sampling clock which are accurately synchronized are generated; a dual-channel ADC is used for synchronously collecting the same radio frequency signal, and abnormal signals are judged and identified through spectrum coherence analysis and differential spectrum threshold. The system comprises a main clock unit, a self-adaptive synchronous compensation circuit, a dual-channel ADC module and a data processing comparison module. The picosecond-level synchronization precision is achieved, external time service is not needed, the missing detection and false alarm rate is remarkably reduced, and the method is suitable for high-reliability frequency spectrum monitoring in the complex electromagnetic environment.

A backlight control chip (001), a driving method and a backlight control system, and a near-eye display device. The backlight control chip (001) is used for driving a backlight module, comprising: a boost circuit (101), the boost circuit (101) is configured to receive and boost a variable frequency clock signal (EXT_CLK) into a synchronization signal (HVSYNC_IN), wherein the variable frequency clock signal (EXT_CLK) and the synchronization signal (HVSYNC_IN) both have the same refresh rate as variable frequency display; a gating circuit (102), the gating circuit (102) is configured to receive the synchronization signal (HVSYNC_IN), a fixed frequency signal (VSYNC), a variable frequency signal (512xVSYNC), a first frame frequency control signal (HVSYNC_EN) and a second frame frequency control signal (DPLL_ENB), and after controlling the switching output of the synchronization signal (HVSYNC_IN) and the variable frequency signal (512xVSYNC) in response to the first frame frequency control signal (HVSYNC_EN), then controlling the switching output of the synchronization signal (HVSYNC_IN) or the variable frequency signal (512xVSYNC) and the fixed frequency signal (VSYNC) in response to the second frame frequency control signal (DPLL_ENB), wherein the fixed frequency signal (VSYNC) is used to complete the generation of the internal main clock signal of the backlight control chip (001), the variable frequency signal (512xVSYNC) is irrelevant to the refresh rate of variable frequency display, and the frame frequency control signal includes the first frame frequency control signal (HVSYNC_EN) and the second frame frequency control signal (DPLL_ENB).