140 results about "Clock skew" patented technology

The invention discloses a power distribution station overload risk alarm method and device based on multi-source sensing data fusion, and relates to the technical field of intelligent early warning, and the method comprises the following steps: in the operation process of a power distribution station, injecting a micro-amplitude synchronization pulse in a multi-source sensing data collection stage, collecting a pulse feedback result, calculating and collecting clock offset, and constructing a second-level alignment vector; time sequence synchronization among different sensing channels is realized, and a turn-back sensitive baseline is established. According to the method, through multi-source sensing data alignment and turn-back identification, in combination with edge fidelity filtering, heat accumulation calculation and fast and slow variable decoupling, accurate early warning of abnormal load fluctuation is realized, a closed-loop control mechanism of residual feedback is established, and the accuracy and foresight of power distribution station overload risk identification are remarkably improved.

Die or chip interconnect clock skew compensation can be performed for a multi -IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi - IC module that is receiving data and clock signals from a second die or chip of the multi -IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.

The invention relates to the technical field of copper pipe flaw detection, in particular to a flaw detection ink jet line time sequence synchronous control method, system and equipment, and the method comprises the following steps: flaw detection equipment and an ink jet head establish a master-slave node relationship according to a communication network protocol, the flaw detection equipment is used as a master node, and the ink jet head is used as a slave node; the master node acquires flaw detection signals of the copper pipe in real time, encapsulates the flaw detection signals into a data packet carrying a timestamp, and transmits the data packet to the slave node according to a communication network protocol; after the slave nodes receive the data packets, the timestamps are analyzed, and ink jet trigger compensation time is calculated based on a network transmission delay prediction model; a synchronous ink jet instruction is generated according to the ink jet trigger compensation time, and an ink jet head is controlled to mark the defect position of the copper pipe; and periodically checking clock skew data of the master and slave nodes based on a communication network protocol, and dynamically updating the network transmission delay prediction model. According to the invention, the core problem of mark position offset caused by insufficient clock synchronization precision is effectively solved.

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

The invention provides an electric power internet of things minute-level data acquisition method based on hierarchical time synchronization, which comprises the following steps of: 1, dividing an HPLC (High Performance Liquid Chromatography) channel into a time synchronization time slot and a data uploading time slot, and dynamically adjusting the bandwidth proportion of the time synchronization time slot and the data uploading time slot; 2, clock skew compensation is completed through bidirectional message interaction of the master node and the slave node, and a uniform minute-level time framework of the whole network is established; step 3, based on the local clock calibrated by the terminal equipment, calculating an accurate acquisition triggering moment by combining the distributed offset parameters, and when a preset time slot is reached, automatically executing instantaneous sampling of data; and 4, constructing a priority evaluation model based on the voltage abrupt change rate and the emergency level, calculating data acquisition priorities in real time, and executing corresponding operations according to different priorities. According to the method, active preemptive transmission of fault feature data in a single acquisition period is realized through a dynamic priority model in which the voltage break rate is linked with the event level.

The invention relates to an ephemeris broadcast and time synchronization method for Beidou pseudolite deformation monitoring, and belongs to the technical field of satellite positioning. The method comprises the following steps: constructing a linearization error equation based on a pseudo-range observation value, and solving a clock error correction amount in combination with a robust iterative algorithm to improve the time synchronization precision; analyzing ephemeris parameters of the Beidou GEO satellite, calculating earth-fixed coordinates of the Beidou GEO satellite, and rotating and adapting the earth-fixed coordinates; establishing an affine transformation relationship between the pseudo-satellite coordinates and GEO ephemeris, and generating optimized pseudo-satellite ephemeris data; and a time synchronization protocol is designed, and clock skew is compensated through bidirectional timestamp interaction of the main base station and the pseudo satellite. According to the method, nanosecond synchronization of the pseudo-satellite and the real satellite is realized, the ephemeris parameter redundancy problem of the static pseudo-satellite is optimized, multi-system cooperative work is supported, and the deformation monitoring reliability and precision under the complex terrain are remarkably improved.

The invention provides a multi-magnetic accurate positioning method based on APSO-LM fusion, and solves the technical contradictions that global search and local convergence are unbalanced and the resolving efficiency is low in the existing multi-magnetic accurate positioning technology. The method comprises the following steps: constructing a magnetic moment calibration module, selecting a sensor array calibration point, collecting magnetic field data, and calculating a precise magnetic moment amplitude based on a magnetic dipole model; an NSS-VMGT initial positioning result is input through a parameter initialization module, APSO and LM algorithm parameters are configured, and particle vectors are normalized; generating a particle swarm by using an APSO global search module, and iteratively screening a global optimal parameter as an LM initial value; calculating a residual error and a Jacobian matrix by means of an LM local refining module, and iteratively optimizing and outputting a magnetic source position and a magnetic moment; and the dynamic compensation module is used for calibrating clock skew and inhibiting environment interference. The device is realized based on STM32H743, and comprises a 7 * 7 lis2mdltr sensor array, a dual-chip data acquisition link, an APSO-LM algorithm hardware acceleration module and an upper computer interaction unit.

The embodiment of the invention discloses a time synchronization method and device based on Kalman filtering, a medium and a product. According to the method, the precision and the speed of time synchronization are improved by establishing a double-state model containing clock skew and clock drift; a dynamic suppression factor is introduced to adaptively adjust an observation noise covariance to deal with abnormal noise; distinguishing and independently adjusting the process noise covariance of the clock skew and the clock drift by adopting a block self-adaptive strategy so as to match different noise characteristics of the clock skew and the clock drift; and finally, high-precision and high-robustness time synchronization is realized through Kalman filtering.

The invention provides an inter-satellite link bidirectional measurement method based on a same-time same-frequency full-duplex system, which overcomes the problem that receiving and transmitting of a traditional time-division half-duplex system cannot work at the same time and at the same frequency, and can effectively improve the information transmission rate and the ranging precision. The inter-satellite transmission rate, the measurement frequency and the data updating rate can be doubled; simultaneous and same-frequency measurement between satellites can greatly eliminate distance measurement errors caused by relative motion between satellites, clock skew and Doppler effect; a complex orbit model does not need to be established to improve the distance measurement precision, the time scale reduction error is greatly reduced, and the overall measurement performance is improved.

The invention relates to the technical field of radio orientation, in particular to an enhanced Beidou precise time service method based on a receiver clock model, which comprises the following steps: acquiring multi-source data, and preprocessing the multi-source data; establishing a Beidou receiver clock model, optimizing model parameters through a least square method, outputting a first clock drift value and a first coefficient, and predicting a second clock drift value and a second coefficient by using a machine learning model; then, a Bayesian fusion model is utilized to be combined with the Beidou receiver clock model and the machine learning model, a clock drift predicted value is output, and a time migration predicted value is calculated; calculating a carrier-to-noise ratio loss value, an autocorrelation function distortion value and a phase change value, generating a signal quality index, and calculating an error compensation value by using a weight distribution mechanism; and finally, correcting the clock skew according to the error compensation value. Through combination of multiple models, the precision of clock drift prediction is improved, and the clock skew is effectively corrected, so that the precision of mountainous area time service is improved.

The invention relates to the technical field of telecommunication, and discloses an earphone and sound box multichannel audio synchronous transmission method and system, and the method comprises the steps: firstly obtaining an initial audio stream of a target device (earphone and sound box), recognizing format features, analyzing a frequency spectrum component, generating a left / right sound channel signal, then detecting the transmission priority of the sound channel signal, analyzing a channel distribution demand, and carrying out the transmission of the sound channel signal; the query equipment responds to the time delay and calculates a synchronization reference value, then determines a signal competition hotspot based on the value, analyzes the interference intensity and the frequency band occupancy rate, calculates a clock offset index, then determines a collaborative playing path according to the index, queries a phase tolerance threshold, formulates a time sequence calibration process, and finally corrects a sound channel signal by using the process. Obtaining, recording and optimizing clock reference parameters, and generating a synchronous transmission scheme. The overall sound effect stability of cooperative playing of the earphone and the sound box can be improved.

A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

Clock synchronization in a multichip module is provided. Relative clock skews among a plurality of digital devices are detected based on a pairwise exchange of clock signals between digital devices. In some aspects, the plurality of digital devices comprising at least one noncommunicating pair of digital devices. Based on the relative clock skews of the various devices, the respective clock signals of the plurality of digital devices are deskewed.

The invention relates to the technical field of photoetching machine data transmission, and discloses an ultra-high-speed distributed data transmission synchronization system of a direct-writing photoetching machine. The system comprises a dynamic exposure pulse analysis module which constructs a distributed transmission delay calculation model based on historical operation data, collects data such as a laser trigger pulse sequence in real time and outputs a theoretical transmission synchronization value; the multi-channel time sequence offset detection module generates a node-level multi-channel time sequence offset matrix through multi-dimensional comparison of the theoretical value and the actual transmission time sequence; the spatial topology mapping module is combined with the physical position and the link impedance parameter to generate a time sequence abnormal propagation path probability distribution cloud picture so as to locate a high-delay area; and the dynamic bandwidth allocation module configures a transmission strategy according to the data, starts redundant channel parallel transmission for a high-delay area, and implements dynamic clock offset compensation for adjacent nodes, so that the synchronization stability and transmission efficiency of data transmission are effectively improved.

Provided is a method for performing clock synchronization in a wireless network performed by an electronic device acting as a third device. The method includes: receiving a data packet transmitted from a first device via a second device, the data packet including a first timestamp when the first device transmits the data packet; acquiring a local timestamp indicating when the third device receives the data packet, and time information transmitted by the second device indicating when the data packet is received; computing delay information of a specified link part of a transmission link between the third device and the first device accordingly; computing, according to the delay information of the specified link part and a link type of the specified link part, a clock skew corresponding to the specified link part; and performing, according to the clock skew, clock synchronization on a transmission node corresponding to the specified link part.

The invention discloses a data synchronous backup method and system for a distributed mobile storage cluster, and relates to the technical field of mobile distributed storage, comprising the following steps of: cooperatively calculating clock skew and drift of each node based on an ultra-wideband bidirectional ranging result of a mobile node in the distributed mobile storage cluster; forming a distributed relative clock under the conditions of no external time source and fixed master control node; when any mobile node is subjected to data change, calling a distributed relative clock to obtain a logic timestamp; generating difference information through a local conflict-free copy data engine; binding the logic timestamps with the difference information to form increment synchronization entries and storing the increment synchronization entries in a to-be-synchronized list; when the two mobile nodes enter a communication range, comparing the maximum logic timestamps in the to-be-synchronized lists of the two mobile nodes, and initiating a synchronization request from a backward party to a leading party; according to the invention, the distributed relative clock is formed based on the bidirectional ranging result, and the autonomous synchronization capability and the consistency keeping efficiency of the mobile distributed storage cluster are improved.

The invention relates to a positioning method, a positioning device and a readable storage medium, and relates to the technical field of satellite navigation. The positioning method is applied to a receiver, and the receiver receives a pseudo satellite signal sent by each target satellite in a plurality of target satellites simulated by a pseudo satellite base station; wherein the number of the target satellites is at least four, and the target satellites are satellites which are invisible at the position where the receiver is located; for each pseudo-satellite base station, determining auxiliary positioning information of the pseudo-satellite base station according to the pseudo-satellite signal corresponding to the pseudo-satellite base station; wherein the auxiliary positioning information comprises the base station position of the pseudo satellite base station and the clock skew, and the clock skew is the skew between the clock of the pseudo satellite base station and the local clock of the receiver; and determining the position of the receiver according to the auxiliary positioning information of the pseudo satellite base station.

The invention discloses a cascade clock synchronization circuit. The cascade clock synchronization circuit comprises M stages of clock synchronization circuits in cascade connection, and each clock synchronization circuit comprises a phase detection module and a clock generation module. When the i-th count value is X + 2N-1 and X + N-1, the phase detection module outputs an i-th phase detection signal and sets the i-th phase detection signal as an effective level; and the clock generation module carries out frequency division on the ith high-frequency clock N according to the effective level of the ith phase detection signal to generate an ith Nth frequency division clock synchronous with the ith high-frequency clock N, counts the level change of the ith-level phase detection signal to obtain an ith cascade count value, and outputs the ith-level cascade signal and sets the ith-level cascade signal as the effective level when the ith cascade count value is X + 2N-1 and X. According to the invention, the problem of synchronization failure caused by clock skew accumulation of the high-speed clock and the low-speed clock in the multi-channel clock synchronization process is solved. Especially in a multi-channel data synchronous transmission scene such as a multi-BANK multi-SerDes architecture, the problem of clock synchronization failure caused by clock skew accumulation is effectively solved.

The invention provides a time-space structured sparse optical coding deepwater heterogeneous network data synchronization method and system, and the method comprises the steps: carrying out the sparse decomposition of the time sequence clock deviation data of each current underwater node at a transmitting end device of a deepwater heterogeneous network based on a trained over-complete dictionary, and obtaining an original sparse vector; converting the dynamic compression observation data corresponding to the original sparse vector into an optical signal, and transmitting the optical signal to a receiving end device of the deepwater heterogeneous network by a transmitting end device through an umbilical cable; demodulating the optical signal into an observation vector through receiving end equipment, inputting the observation vector into the trained deep expansion network model, and outputting a reconstructed sparse vector by the deep expansion network model; and recovering the reconstructed sparse vector into a clock skew signal through the over-complete dictionary, and generating a clock synchronization calibration instruction to realize data synchronization of the corresponding underwater node. According to the invention, the problems of high bandwidth occupation, low signal ratio and poor reconstruction time efficiency existing in the underwater network time synchronization technology can be solved.

The invention relates to a TMR sensor network self-synchronization time service method, device and equipment and a medium, and the method comprises the following steps: obtaining a power line power frequency magnetic field signal collected by a TMR sensor in real time, extracting a fundamental component, and marking a magnetic field zero crossing point; based on a PTP protocol, a master node periodically broadcasts a synchronous message at a magnetic field zero crossing point and adds a magnetic field zero crossing point timestamp, and a slave node compares a time difference between the receiving timestamp and the magnetic field zero crossing point and calculates a first delay; the slave node sends a delay request message, the master node compares the receiving timestamp with the magnetic field zero crossing point time difference, and second delay is calculated; and calculating a clock skew based on the first time delay and the second time delay, calculating a result obtained by subtracting the clock skew from the current time by the slave node, and taking the result as accurate time of the slave node to finish time synchronization. Compared with the prior art, the method has the advantages that passive high-precision self-synchronizing time service can be realized, and the like.

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

Various aspects of the subject technology relate to systems, methods, and machine-readable media for selective encryption in a shared artificial reality environment. Various aspects may include determining contextual information of the shared artificial reality environment. Aspects may also include encrypting communication in the environment into encrypted channels and non-encrypted channels based on the contextual information. Aspects may also include determining a correlation between the encrypted channels and the non-encrypted channels. Aspects may also include applying, based on the correlation, a partial encryption to the non-encrypted channels for obscuring a cryptographic code of the communication. Aspects may include determining a recombination of the encrypted channels and the non-encrypted channels based on clock skew.

Die or chip interconnect clock skew compensation can be performed for a multi-IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi-IC module that is receiving data and clock signals from a second die or chip of the multi-IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.

The invention discloses a control instruction rate matching method of a distributed controller-driver, and relates to the technical field of distributed control, and the method comprises the steps: carrying out instruction frequency detection through employing a clock source of the driver, and obtaining a frequency error value of a controller instruction; performing interpolation caching processing on the controller instruction based on the frequency error value of the controller instruction to obtain frequency error information of instruction caching; and performing dynamic period adjustment according to the frequency error value of the controller instruction and the frequency error information of the instruction cache, and obtaining a control instruction rate matching result. Frequency detection and dynamic period adjustment are independently completed through the driver, a controller does not need to participate in clock calibration, the communication bandwidth is prevented from being occupied by a calibration instruction, and the system communication efficiency is remarkably improved; and in combination with interpolation cache processing, clock skew can be compensated in real time, the instruction frequency error is controlled within an extremely low range, the system fluctuation risk is effectively reduced, a communication protocol does not need to be modified, and the method is completely compatible with an existing hardware architecture.

The invention belongs to the field of power system management, and particularly relates to a power system time synchronization management device. The device comprises a master station management module, a station control management module and an interval management module which respectively comprise a monitoring end and a monitored end, the monitored end of the master station management module is used for acquiring clock data of a monitored object at a master station, and the monitoring end is used for respectively determining clock skew of the station control management module and the monitored object at the master station relative to the monitoring end of the master station management module; a monitored end of the station control management module is used for acquiring clock data of a monitored object at a substation control layer, and a monitoring end is used for respectively determining clock skew of the interval management module and the monitored object at the substation control layer relative to the monitoring end of the station control management module; the monitored end of the interval management module is used for acquiring clock data of the monitored object at the substation interval layer, and the monitoring end is used for determining clock skew of the monitored object at the substation interval layer relative to the monitoring end of the interval management module.

Trajectory planning to improve clock skew is disclosed. In one aspect, an array of nodes includes a plurality of nodes having clock distribution circuitry configured to distribute a clock signal to each of the nodes. The clock signal propagates in a first direction at least between adjacent nodes. The nodes (202) also include a trajectory plan that includes a plurality of conductive lines to carry communication signals that propagate between the adjacent nodes. The plurality of conductive lines includes a first conductive line (404) configured to carry a first communication signal in a direction opposite the first direction and a second conductive line (402) configured to carry a second communication signal in the first direction, wherein a width of the first conductive line is greater than a width of the second conductive line.

A semiconductor device includes a receiver and a controller. The receiver is configured to sample a data signal and a track signal received through data lanes in response to rising edges of first and second internal clock signal pairs. The controller is configured to detect a skew status between the track signal and the first and second internal clock signal pairs, based on the number of times a specific logic level of the track signal is sampled in synchronization with each of the first and second internal clock signal pairs, and provide the receiver with a clock shift signal for calibrating a clock skew, based on the skew status.

The invention discloses a signal data receiving terminal for data recovery without a reference clock and a receiving method of the signal data receiving terminal, and relates to the technical field of clock data recovery. And the inner side of the fixing frame is fixedly connected with a terminal body which is used for receiving external data and is embedded into the clock body to recover the precision of the clock body. According to the signal data receiving terminal for data recovery without the reference clock and the receiving method of the signal data receiving terminal, external data are received through the terminal body, the terminal body exchanges timestamps, counteracts transmission delay and calculates clock skew through two-way communication, and the local clock frequency is adjusted through feedback control of the received signals, so that the data recovery efficiency is improved. When the terminal body starts to receive external data, the deformation metal sheet can pull the receiving antenna to move towards the outer side, the receiving antenna extends out of the interior of the terminal body to better receive the external data, and subsequent data recovery of a non-reference clock is facilitated.

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

The invention relates to the technical field of integrated circuits, and discloses a multi-FPGA global clock synchronization device and method, and the device comprises an inter-board clock synchronization circuit and an in-board clock synchronization circuit. The inter-board clock synchronization circuit comprises an inter-board clock expansion circuit and an inter-board feedback clock circuit, the input end of the inter-board clock expansion circuit is connected with an external clock and a crystal oscillator signal, and the inter-board feedback clock circuit is connected between the output end and the input end of the inter-board clock expansion circuit; the in-board clock synchronization circuit comprises an in-board clock expansion circuit and an in-board feedback clock circuit, the input end of the in-board clock expansion circuit is connected with a clock signal output by the inter-board clock synchronization circuit, and the in-board feedback clock circuit is connected between the output end and the input end of the in-board clock expansion circuit; the output end of the in-board clock expansion circuit is connected with the internal logic module. Through an inter-board / internal clock expansion circuit and a dynamic feedback compensation mechanism, clock skew between board levels and boards is eliminated, and clock synchronization of a large-scale prototype verification system is supported.