107 results about "Clock skew" patented technology

The invention discloses a power distribution station overload risk alarm method and device based on multi-source sensing data fusion, and relates to the technical field of intelligent early warning, and the method comprises the following steps: in the operation process of a power distribution station, injecting a micro-amplitude synchronization pulse in a multi-source sensing data collection stage, collecting a pulse feedback result, calculating and collecting clock offset, and constructing a second-level alignment vector; time sequence synchronization among different sensing channels is realized, and a turn-back sensitive baseline is established. According to the method, through multi-source sensing data alignment and turn-back identification, in combination with edge fidelity filtering, heat accumulation calculation and fast and slow variable decoupling, accurate early warning of abnormal load fluctuation is realized, a closed-loop control mechanism of residual feedback is established, and the accuracy and foresight of power distribution station overload risk identification are remarkably improved.

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

The invention relates to an ephemeris broadcast and time synchronization method for Beidou pseudolite deformation monitoring, and belongs to the technical field of satellite positioning. The method comprises the following steps: constructing a linearization error equation based on a pseudo-range observation value, and solving a clock error correction amount in combination with a robust iterative algorithm to improve the time synchronization precision; analyzing ephemeris parameters of the Beidou GEO satellite, calculating earth-fixed coordinates of the Beidou GEO satellite, and rotating and adapting the earth-fixed coordinates; establishing an affine transformation relationship between the pseudo-satellite coordinates and GEO ephemeris, and generating optimized pseudo-satellite ephemeris data; and a time synchronization protocol is designed, and clock skew is compensated through bidirectional timestamp interaction of the main base station and the pseudo satellite. According to the method, nanosecond synchronization of the pseudo-satellite and the real satellite is realized, the ephemeris parameter redundancy problem of the static pseudo-satellite is optimized, multi-system cooperative work is supported, and the deformation monitoring reliability and precision under the complex terrain are remarkably improved.

The invention provides a multi-magnetic accurate positioning method based on APSO-LM fusion, and solves the technical contradictions that global search and local convergence are unbalanced and the resolving efficiency is low in the existing multi-magnetic accurate positioning technology. The method comprises the following steps: constructing a magnetic moment calibration module, selecting a sensor array calibration point, collecting magnetic field data, and calculating a precise magnetic moment amplitude based on a magnetic dipole model; an NSS-VMGT initial positioning result is input through a parameter initialization module, APSO and LM algorithm parameters are configured, and particle vectors are normalized; generating a particle swarm by using an APSO global search module, and iteratively screening a global optimal parameter as an LM initial value; calculating a residual error and a Jacobian matrix by means of an LM local refining module, and iteratively optimizing and outputting a magnetic source position and a magnetic moment; and the dynamic compensation module is used for calibrating clock skew and inhibiting environment interference. The device is realized based on STM32H743, and comprises a 7 * 7 lis2mdltr sensor array, a dual-chip data acquisition link, an APSO-LM algorithm hardware acceleration module and an upper computer interaction unit.

The embodiment of the invention discloses a time synchronization method and device based on Kalman filtering, a medium and a product. According to the method, the precision and the speed of time synchronization are improved by establishing a double-state model containing clock skew and clock drift; a dynamic suppression factor is introduced to adaptively adjust an observation noise covariance to deal with abnormal noise; distinguishing and independently adjusting the process noise covariance of the clock skew and the clock drift by adopting a block self-adaptive strategy so as to match different noise characteristics of the clock skew and the clock drift; and finally, high-precision and high-robustness time synchronization is realized through Kalman filtering.

The invention provides an inter-satellite link bidirectional measurement method based on a same-time same-frequency full-duplex system, which overcomes the problem that receiving and transmitting of a traditional time-division half-duplex system cannot work at the same time and at the same frequency, and can effectively improve the information transmission rate and the ranging precision. The inter-satellite transmission rate, the measurement frequency and the data updating rate can be doubled; simultaneous and same-frequency measurement between satellites can greatly eliminate distance measurement errors caused by relative motion between satellites, clock skew and Doppler effect; a complex orbit model does not need to be established to improve the distance measurement precision, the time scale reduction error is greatly reduced, and the overall measurement performance is improved.

The invention relates to the technical field of telecommunication, and discloses an earphone and sound box multichannel audio synchronous transmission method and system, and the method comprises the steps: firstly obtaining an initial audio stream of a target device (earphone and sound box), recognizing format features, analyzing a frequency spectrum component, generating a left / right sound channel signal, then detecting the transmission priority of the sound channel signal, analyzing a channel distribution demand, and carrying out the transmission of the sound channel signal; the query equipment responds to the time delay and calculates a synchronization reference value, then determines a signal competition hotspot based on the value, analyzes the interference intensity and the frequency band occupancy rate, calculates a clock offset index, then determines a collaborative playing path according to the index, queries a phase tolerance threshold, formulates a time sequence calibration process, and finally corrects a sound channel signal by using the process. Obtaining, recording and optimizing clock reference parameters, and generating a synchronous transmission scheme. The overall sound effect stability of cooperative playing of the earphone and the sound box can be improved.

A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

Clock synchronization in a multichip module is provided. Relative clock skews among a plurality of digital devices are detected based on a pairwise exchange of clock signals between digital devices. In some aspects, the plurality of digital devices comprising at least one noncommunicating pair of digital devices. Based on the relative clock skews of the various devices, the respective clock signals of the plurality of digital devices are deskewed.

The invention relates to the technical field of photoetching machine data transmission, and discloses an ultra-high-speed distributed data transmission synchronization system of a direct-writing photoetching machine. The system comprises a dynamic exposure pulse analysis module which constructs a distributed transmission delay calculation model based on historical operation data, collects data such as a laser trigger pulse sequence in real time and outputs a theoretical transmission synchronization value; the multi-channel time sequence offset detection module generates a node-level multi-channel time sequence offset matrix through multi-dimensional comparison of the theoretical value and the actual transmission time sequence; the spatial topology mapping module is combined with the physical position and the link impedance parameter to generate a time sequence abnormal propagation path probability distribution cloud picture so as to locate a high-delay area; and the dynamic bandwidth allocation module configures a transmission strategy according to the data, starts redundant channel parallel transmission for a high-delay area, and implements dynamic clock offset compensation for adjacent nodes, so that the synchronization stability and transmission efficiency of data transmission are effectively improved.

Provided is a method for performing clock synchronization in a wireless network performed by an electronic device acting as a third device. The method includes: receiving a data packet transmitted from a first device via a second device, the data packet including a first timestamp when the first device transmits the data packet; acquiring a local timestamp indicating when the third device receives the data packet, and time information transmitted by the second device indicating when the data packet is received; computing delay information of a specified link part of a transmission link between the third device and the first device accordingly; computing, according to the delay information of the specified link part and a link type of the specified link part, a clock skew corresponding to the specified link part; and performing, according to the clock skew, clock synchronization on a transmission node corresponding to the specified link part.

The invention discloses a data synchronous backup method and system for a distributed mobile storage cluster, and relates to the technical field of mobile distributed storage, comprising the following steps of: cooperatively calculating clock skew and drift of each node based on an ultra-wideband bidirectional ranging result of a mobile node in the distributed mobile storage cluster; forming a distributed relative clock under the conditions of no external time source and fixed master control node; when any mobile node is subjected to data change, calling a distributed relative clock to obtain a logic timestamp; generating difference information through a local conflict-free copy data engine; binding the logic timestamps with the difference information to form increment synchronization entries and storing the increment synchronization entries in a to-be-synchronized list; when the two mobile nodes enter a communication range, comparing the maximum logic timestamps in the to-be-synchronized lists of the two mobile nodes, and initiating a synchronization request from a backward party to a leading party; according to the invention, the distributed relative clock is formed based on the bidirectional ranging result, and the autonomous synchronization capability and the consistency keeping efficiency of the mobile distributed storage cluster are improved.

The invention discloses a cascade clock synchronization circuit. The cascade clock synchronization circuit comprises M stages of clock synchronization circuits in cascade connection, and each clock synchronization circuit comprises a phase detection module and a clock generation module. When the i-th count value is X + 2N-1 and X + N-1, the phase detection module outputs an i-th phase detection signal and sets the i-th phase detection signal as an effective level; and the clock generation module carries out frequency division on the ith high-frequency clock N according to the effective level of the ith phase detection signal to generate an ith Nth frequency division clock synchronous with the ith high-frequency clock N, counts the level change of the ith-level phase detection signal to obtain an ith cascade count value, and outputs the ith-level cascade signal and sets the ith-level cascade signal as the effective level when the ith cascade count value is X + 2N-1 and X. According to the invention, the problem of synchronization failure caused by clock skew accumulation of the high-speed clock and the low-speed clock in the multi-channel clock synchronization process is solved. Especially in a multi-channel data synchronous transmission scene such as a multi-BANK multi-SerDes architecture, the problem of clock synchronization failure caused by clock skew accumulation is effectively solved.

The invention provides a time-space structured sparse optical coding deepwater heterogeneous network data synchronization method and system, and the method comprises the steps: carrying out the sparse decomposition of the time sequence clock deviation data of each current underwater node at a transmitting end device of a deepwater heterogeneous network based on a trained over-complete dictionary, and obtaining an original sparse vector; converting the dynamic compression observation data corresponding to the original sparse vector into an optical signal, and transmitting the optical signal to a receiving end device of the deepwater heterogeneous network by a transmitting end device through an umbilical cable; demodulating the optical signal into an observation vector through receiving end equipment, inputting the observation vector into the trained deep expansion network model, and outputting a reconstructed sparse vector by the deep expansion network model; and recovering the reconstructed sparse vector into a clock skew signal through the over-complete dictionary, and generating a clock synchronization calibration instruction to realize data synchronization of the corresponding underwater node. According to the invention, the problems of high bandwidth occupation, low signal ratio and poor reconstruction time efficiency existing in the underwater network time synchronization technology can be solved.

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

Various aspects of the subject technology relate to systems, methods, and machine-readable media for selective encryption in a shared artificial reality environment. Various aspects may include determining contextual information of the shared artificial reality environment. Aspects may also include encrypting communication in the environment into encrypted channels and non-encrypted channels based on the contextual information. Aspects may also include determining a correlation between the encrypted channels and the non-encrypted channels. Aspects may also include applying, based on the correlation, a partial encryption to the non-encrypted channels for obscuring a cryptographic code of the communication. Aspects may include determining a recombination of the encrypted channels and the non-encrypted channels based on clock skew.

The invention discloses a control instruction rate matching method of a distributed controller-driver, and relates to the technical field of distributed control, and the method comprises the steps: carrying out instruction frequency detection through employing a clock source of the driver, and obtaining a frequency error value of a controller instruction; performing interpolation caching processing on the controller instruction based on the frequency error value of the controller instruction to obtain frequency error information of instruction caching; and performing dynamic period adjustment according to the frequency error value of the controller instruction and the frequency error information of the instruction cache, and obtaining a control instruction rate matching result. Frequency detection and dynamic period adjustment are independently completed through the driver, a controller does not need to participate in clock calibration, the communication bandwidth is prevented from being occupied by a calibration instruction, and the system communication efficiency is remarkably improved; and in combination with interpolation cache processing, clock skew can be compensated in real time, the instruction frequency error is controlled within an extremely low range, the system fluctuation risk is effectively reduced, a communication protocol does not need to be modified, and the method is completely compatible with an existing hardware architecture.

Trajectory planning to improve clock skew is disclosed. In one aspect, an array of nodes includes a plurality of nodes having clock distribution circuitry configured to distribute a clock signal to each of the nodes. The clock signal propagates in a first direction at least between adjacent nodes. The nodes (202) also include a trajectory plan that includes a plurality of conductive lines to carry communication signals that propagate between the adjacent nodes. The plurality of conductive lines includes a first conductive line (404) configured to carry a first communication signal in a direction opposite the first direction and a second conductive line (402) configured to carry a second communication signal in the first direction, wherein a width of the first conductive line is greater than a width of the second conductive line.

A semiconductor device includes a receiver and a controller. The receiver is configured to sample a data signal and a track signal received through data lanes in response to rising edges of first and second internal clock signal pairs. The controller is configured to detect a skew status between the track signal and the first and second internal clock signal pairs, based on the number of times a specific logic level of the track signal is sampled in synchronization with each of the first and second internal clock signal pairs, and provide the receiver with a clock shift signal for calibrating a clock skew, based on the skew status.

The invention discloses a signal data receiving terminal for data recovery without a reference clock and a receiving method of the signal data receiving terminal, and relates to the technical field of clock data recovery. And the inner side of the fixing frame is fixedly connected with a terminal body which is used for receiving external data and is embedded into the clock body to recover the precision of the clock body. According to the signal data receiving terminal for data recovery without the reference clock and the receiving method of the signal data receiving terminal, external data are received through the terminal body, the terminal body exchanges timestamps, counteracts transmission delay and calculates clock skew through two-way communication, and the local clock frequency is adjusted through feedback control of the received signals, so that the data recovery efficiency is improved. When the terminal body starts to receive external data, the deformation metal sheet can pull the receiving antenna to move towards the outer side, the receiving antenna extends out of the interior of the terminal body to better receive the external data, and subsequent data recovery of a non-reference clock is facilitated.

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

The present invention relates to a time-domain ping-pong quantized ultra-high-speed analog-to-digital converter, comprising: a sampling switch, a voltage-to-time conversion module, a first ping-pong channel, a second ping-pong channel, a time residual generator, an asynchronous pipelined successive approximation time-to-digital converter, an encoder, and a code value combination unit. The sampling switch is used to sample an input signal; the voltage-to-time conversion module is used to convert the sampled signal into a voltage-to-time signal; the first ping-pong channel and the second ping-pong channel are used to quantize a differential time signal within different sampling periods; the time residual generator is used to generate a time residual signal; the asynchronous pipelined successive approximation time-to-digital converter is used to quantize the residual time difference; the encoder is used to perform code value conversion; and the code value combination unit is used to combine the first quantization code value and the second quantization code value. The converter significantly reduces circuit area while achieving the sampling speed of two channels, and clock skew and jitter of the clock signal do not affect circuit performance.

The invention provides a charging pile clock skew detection and automatic calibration method and system, and the method comprises the steps: a charging pile billing control unit detects a charging pile clock through a timer, and judges whether the current clock has skew or not through a triple detection algorithm; when the current clock has deviation, the charging pile billing control unit reports the clock deviation fault of the equipment side to the charging service platform; when the charging pile billing control unit receives a time synchronization instruction sent by the charging service platform, a calibration operation is executed, and a calibration result is reported to the charging service platform; the problem of inaccurate charging metering and billing caused by clock skew is solved, and the risk of inaccurate metering and billing caused by clock skew can be greatly reduced.

A derivative measurement circuit is configured to sample the input voltage of an input line to determine the time-derivative of the input voltage. A plurality of time-interleaved analog-to-digital converters (ADCs) are configured to convert respective input-voltage samples that are sampled at different times. The ADCs do not convert the input-voltage samples having respective time-derivatives that are above a predetermined threshold magnitude or that are relatively high to limit sampling clock jitter and sampling clock skew.

A processing system includes a peripheral device configured to store security information and having a clock input to receive a gated clock; a watch clock generator configured to generate a watch clock having a reduced duty cycle relative to the system clock; and clock control circuitry configured to select the system clock as a gated clock during normal operation of the peripheral device and select the watch clock as a gated clock during a low power mode of the peripheral device. The watch clock generator may include a counter that counts system clock cycles and a clock pulse selector, such as a mode circuit, configured to select the cycles of the system clock to generate a watch clock. For multiple peripherals, the delay circuitry may skew a watch clock between two or more peripherals. A plurality of watch clocks having different delayed duty cycles may be generated, each for a corresponding group of a plurality of groups of peripherals.

The invention provides an audio output sampling rate calculation method and device, electronic equipment and a storage medium. The method is applied to an audio playing system, and comprises the following steps: in an audio data playing process of an audio buffer area, detecting a filling level of the audio buffer area according to a preset detection frequency; wherein the filling level is used for indicating the current data volume of the audio buffer area; based on the filling level, first clock skew corresponding to the recent multiple detection periods is obtained, and a clock skew set is obtained; calculating a first clock calibration amount according to a first clock skew corresponding to the current detection period in the clock skew set; performing clock drift trend prediction on the clock skew set, and determining a second clock calibration amount according to a prediction result; and according to the first clock calibration amount and the second clock calibration amount, determining the sampling rate of at least one frame of audio data output audio buffer in the future. The method and the device are used for carrying out real-time, accurate and self-adaptive clock calibration on audio playing.

The invention discloses a server detection method and a program product. Acquiring a hardware fingerprint vector and an operation parameter vector of the server, and determining an equipment state detection model corresponding to the server; wherein the hardware fingerprint vector comprises an equipment manufacturer code, a mainboard model code and a firmware version code; the operation parameter vector comprises a voltage ripple, a clock skew rate, a bus load rate and an environment temperature and humidity parameter; inputting the hardware fingerprint vector and the operation parameter vector into an equipment state detection model to obtain an equipment operation state of the server; wherein the equipment operation state comprises a normal state and at least one fault state; and determining a target response operation corresponding to the equipment running state of the server, and executing the target response operation. Therefore, the intelligent detection of the server can be realized, the potential hardware degradation risk in the server is avoided in time, and the accuracy of server detection is improved.

The invention relates to the technical field of medium-wave broadcast, and discloses a medium-wave broadcast audio signal intelligent switching output method, which comprises the following steps: S1, initializing configuration; s2, performing real-time detection; s3, intelligent switching is carried out; s4, alarming and logging in a grading manner; and S5, state backward reading and updating. According to the method and the system for intelligently switching and outputting the medium-wave broadcast audio signals, an AD9850 clock detection unit, an AD8232 and ADS1115 amplitude detection unit, an LM311 peak detection unit, an STM32F103 phase detection unit and an AD637 THD detection unit of a multi-parameter detection module are used for cooperatively detecting AES clock skew, signal amplitude, peak, left and right sound channel phase difference and total harmonic distortion; a power supply detection circuit composed of an LM339 comparator and a TL431 reference source is matched to monitor power supply voltage deviation, each unit is judged to be abnormal according to preset logic, key parameters which are not involved in the prior art are covered, judgment rules are clear, potential faults are comprehensively and accurately recognized, and missed judgment and misjudgment are avoided.

The invention discloses a real-time audio and video end-to-end delay statistical method based on two-way time synchronization, and particularly relates to the technical field of real-time audio and video communication and network performance measurement, which comprises the following steps: S1, time synchronization: a plug flow client and a pull flow client respectively calculate clock skew with an SFU server through two-way message exchange; the method comprises the following steps: S1, a flow pushing end converts an acquisition timestamp and deviation into SFU reference time, and the SFU reference time and stage time consumption metadata are embedded into SEI information to be sent along with a video stream, S3, an SFU server forwards the video stream containing the SEI information, and S4, delay calculation and decomposition: a flow pulling end analyzes the SEI information, calculates total end-to-end delay in combination with the deviation of the flow pulling end, and decomposes the time consumption of each stage. Through high-precision time synchronization and time data losslessly carried by SEI information, non-intrusive, automatic, full-link-covered and decomposable end-to-end delay accurate statistics is realized, and the bottleneck problems that a traditional method is high in invasiveness, low in precision and incapable of positioning are effectively solved.