59 results about "Clock skew" patented technology

The invention provides a multi-magnetic accurate positioning method based on APSO-LM fusion, and solves the technical contradictions that global search and local convergence are unbalanced and the resolving efficiency is low in the existing multi-magnetic accurate positioning technology. The method comprises the following steps: constructing a magnetic moment calibration module, selecting a sensor array calibration point, collecting magnetic field data, and calculating a precise magnetic moment amplitude based on a magnetic dipole model; an NSS-VMGT initial positioning result is input through a parameter initialization module, APSO and LM algorithm parameters are configured, and particle vectors are normalized; generating a particle swarm by using an APSO global search module, and iteratively screening a global optimal parameter as an LM initial value; calculating a residual error and a Jacobian matrix by means of an LM local refining module, and iteratively optimizing and outputting a magnetic source position and a magnetic moment; and the dynamic compensation module is used for calibrating clock skew and inhibiting environment interference. The device is realized based on STM32H743, and comprises a 7 * 7 lis2mdltr sensor array, a dual-chip data acquisition link, an APSO-LM algorithm hardware acceleration module and an upper computer interaction unit.

The invention relates to the technical field of telecommunication, and discloses an earphone and sound box multichannel audio synchronous transmission method and system, and the method comprises the steps: firstly obtaining an initial audio stream of a target device (earphone and sound box), recognizing format features, analyzing a frequency spectrum component, generating a left / right sound channel signal, then detecting the transmission priority of the sound channel signal, analyzing a channel distribution demand, and carrying out the transmission of the sound channel signal; the query equipment responds to the time delay and calculates a synchronization reference value, then determines a signal competition hotspot based on the value, analyzes the interference intensity and the frequency band occupancy rate, calculates a clock offset index, then determines a collaborative playing path according to the index, queries a phase tolerance threshold, formulates a time sequence calibration process, and finally corrects a sound channel signal by using the process. Obtaining, recording and optimizing clock reference parameters, and generating a synchronous transmission scheme. The overall sound effect stability of cooperative playing of the earphone and the sound box can be improved.

The invention relates to the technical field of photoetching machine data transmission, and discloses an ultra-high-speed distributed data transmission synchronization system of a direct-writing photoetching machine. The system comprises a dynamic exposure pulse analysis module which constructs a distributed transmission delay calculation model based on historical operation data, collects data such as a laser trigger pulse sequence in real time and outputs a theoretical transmission synchronization value; the multi-channel time sequence offset detection module generates a node-level multi-channel time sequence offset matrix through multi-dimensional comparison of the theoretical value and the actual transmission time sequence; the spatial topology mapping module is combined with the physical position and the link impedance parameter to generate a time sequence abnormal propagation path probability distribution cloud picture so as to locate a high-delay area; and the dynamic bandwidth allocation module configures a transmission strategy according to the data, starts redundant channel parallel transmission for a high-delay area, and implements dynamic clock offset compensation for adjacent nodes, so that the synchronization stability and transmission efficiency of data transmission are effectively improved.

The invention discloses a data synchronous backup method and system for a distributed mobile storage cluster, and relates to the technical field of mobile distributed storage, comprising the following steps of: cooperatively calculating clock skew and drift of each node based on an ultra-wideband bidirectional ranging result of a mobile node in the distributed mobile storage cluster; forming a distributed relative clock under the conditions of no external time source and fixed master control node; when any mobile node is subjected to data change, calling a distributed relative clock to obtain a logic timestamp; generating difference information through a local conflict-free copy data engine; binding the logic timestamps with the difference information to form increment synchronization entries and storing the increment synchronization entries in a to-be-synchronized list; when the two mobile nodes enter a communication range, comparing the maximum logic timestamps in the to-be-synchronized lists of the two mobile nodes, and initiating a synchronization request from a backward party to a leading party; according to the invention, the distributed relative clock is formed based on the bidirectional ranging result, and the autonomous synchronization capability and the consistency keeping efficiency of the mobile distributed storage cluster are improved.

The invention provides a time-space structured sparse optical coding deepwater heterogeneous network data synchronization method and system, and the method comprises the steps: carrying out the sparse decomposition of the time sequence clock deviation data of each current underwater node at a transmitting end device of a deepwater heterogeneous network based on a trained over-complete dictionary, and obtaining an original sparse vector; converting the dynamic compression observation data corresponding to the original sparse vector into an optical signal, and transmitting the optical signal to a receiving end device of the deepwater heterogeneous network by a transmitting end device through an umbilical cable; demodulating the optical signal into an observation vector through receiving end equipment, inputting the observation vector into the trained deep expansion network model, and outputting a reconstructed sparse vector by the deep expansion network model; and recovering the reconstructed sparse vector into a clock skew signal through the over-complete dictionary, and generating a clock synchronization calibration instruction to realize data synchronization of the corresponding underwater node. According to the invention, the problems of high bandwidth occupation, low signal ratio and poor reconstruction time efficiency existing in the underwater network time synchronization technology can be solved.

Various aspects of the subject technology relate to systems, methods, and machine-readable media for selective encryption in a shared artificial reality environment. Various aspects may include determining contextual information of the shared artificial reality environment. Aspects may also include encrypting communication in the environment into encrypted channels and non-encrypted channels based on the contextual information. Aspects may also include determining a correlation between the encrypted channels and the non-encrypted channels. Aspects may also include applying, based on the correlation, a partial encryption to the non-encrypted channels for obscuring a cryptographic code of the communication. Aspects may include determining a recombination of the encrypted channels and the non-encrypted channels based on clock skew.

Trajectory planning to improve clock skew is disclosed. In one aspect, an array of nodes includes a plurality of nodes having clock distribution circuitry configured to distribute a clock signal to each of the nodes. The clock signal propagates in a first direction at least between adjacent nodes. The nodes (202) also include a trajectory plan that includes a plurality of conductive lines to carry communication signals that propagate between the adjacent nodes. The plurality of conductive lines includes a first conductive line (404) configured to carry a first communication signal in a direction opposite the first direction and a second conductive line (402) configured to carry a second communication signal in the first direction, wherein a width of the first conductive line is greater than a width of the second conductive line.

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

The invention provides a charging pile clock skew detection and automatic calibration method and system, and the method comprises the steps: a charging pile billing control unit detects a charging pile clock through a timer, and judges whether the current clock has skew or not through a triple detection algorithm; when the current clock has deviation, the charging pile billing control unit reports the clock deviation fault of the equipment side to the charging service platform; when the charging pile billing control unit receives a time synchronization instruction sent by the charging service platform, a calibration operation is executed, and a calibration result is reported to the charging service platform; the problem of inaccurate charging metering and billing caused by clock skew is solved, and the risk of inaccurate metering and billing caused by clock skew can be greatly reduced.

A processing system includes a peripheral device configured to store security information and having a clock input to receive a gated clock; a watch clock generator configured to generate a watch clock having a reduced duty cycle relative to the system clock; and clock control circuitry configured to select the system clock as a gated clock during normal operation of the peripheral device and select the watch clock as a gated clock during a low power mode of the peripheral device. The watch clock generator may include a counter that counts system clock cycles and a clock pulse selector, such as a mode circuit, configured to select the cycles of the system clock to generate a watch clock. For multiple peripherals, the delay circuitry may skew a watch clock between two or more peripherals. A plurality of watch clocks having different delayed duty cycles may be generated, each for a corresponding group of a plurality of groups of peripherals.

The invention provides an audio output sampling rate calculation method and device, electronic equipment and a storage medium. The method is applied to an audio playing system, and comprises the following steps: in an audio data playing process of an audio buffer area, detecting a filling level of the audio buffer area according to a preset detection frequency; wherein the filling level is used for indicating the current data volume of the audio buffer area; based on the filling level, first clock skew corresponding to the recent multiple detection periods is obtained, and a clock skew set is obtained; calculating a first clock calibration amount according to a first clock skew corresponding to the current detection period in the clock skew set; performing clock drift trend prediction on the clock skew set, and determining a second clock calibration amount according to a prediction result; and according to the first clock calibration amount and the second clock calibration amount, determining the sampling rate of at least one frame of audio data output audio buffer in the future. The method and the device are used for carrying out real-time, accurate and self-adaptive clock calibration on audio playing.

The invention discloses a real-time audio and video end-to-end delay statistical method based on two-way time synchronization, and particularly relates to the technical field of real-time audio and video communication and network performance measurement, which comprises the following steps: S1, time synchronization: a plug flow client and a pull flow client respectively calculate clock skew with an SFU server through two-way message exchange; the method comprises the following steps: S1, a flow pushing end converts an acquisition timestamp and deviation into SFU reference time, and the SFU reference time and stage time consumption metadata are embedded into SEI information to be sent along with a video stream, S3, an SFU server forwards the video stream containing the SEI information, and S4, delay calculation and decomposition: a flow pulling end analyzes the SEI information, calculates total end-to-end delay in combination with the deviation of the flow pulling end, and decomposes the time consumption of each stage. Through high-precision time synchronization and time data losslessly carried by SEI information, non-intrusive, automatic, full-link-covered and decomposable end-to-end delay accurate statistics is realized, and the bottleneck problems that a traditional method is high in invasiveness, low in precision and incapable of positioning are effectively solved.

The disclosed systems and methods provide signal crossing across die boundaries of stacked dies. By having a queue structure coupled to a multiplexer hierarchy, clock skew and other differences between stacked dies can be addressed without require a prohibitive number of TSVs, BPVs, or other vertical interconnects. Various other methods, systems, and computer-readable media are also disclosed.

Disclosed are a positioning method and apparatus, which are used for eliminating a clock skew between base stations and improving the UE positioning accuracy of an UL-TDOA / DL-TDOA positioning technical scheme. The method comprises: determining positioning reference signal configuration information; for a downlink time difference of arrival (DL-TDOA) positioning technical scheme, receiving and measuring downlink positioning reference signals from different base stations on the basis of the positioning reference signal configuration information, determining downlink positioning measurement quantity information, and reporting the downlink positioning measurement quantity information and location information of a reference terminal; and for an uplink time difference of arrival (UL-TDOA) positioning technical scheme, sending an uplink positioning reference signal on the basis of the positioning reference signal configuration information, and sending the location information of the reference terminal.

This invention discloses a drive control system and method for an LED display device. The drive control system includes: at least two GPIO ports; at least two DMA controllers; a PWM module; and a master timer. The trigger output of the master timer is connected to the trigger inputs of all DMA controllers and the synchronization input of the PWM module to generate a synchronization trigger signal. The synchronization trigger signal is used to simultaneously trigger all DMA controllers to perform a data transfer from their corresponding buffers to their bound output data registers, while simultaneously keeping the clock signal in phase with the data transfer. This invention solves the technical problems in the prior art where, when multiple DMA controllers control multiple GPIO ports respectively, the data signals output from different groups of GPIO ports exhibit clock skew, leading to image tearing and misalignment at screen seams, and the data signal and clock signal being out of sync, causing display noise and flicker.

The invention relates to the technical field of integrated circuits, and discloses a calibration system of a high-speed digital-to-analog converter, which comprises a transmitting end circuit, a digital-to-analog converter, an analog-to-digital converter, a digital calibration circuit and a clock calibration circuit, and is characterized in that the clock calibration circuit comprises a deflection calibration unit, a rising edge calibration unit and a falling edge calibration unit; the skew calibration unit synchronously adjusts the clock signal of each channel according to the control word to realize multi-channel clock skew calibration; and the rising edge or falling edge calibration unit accurately adjusts the rising edge or falling edge of the single pulse according to the pulse control word to realize 1 ui pulse width calibration. By decoupling skew calibration and 1ui pulse width calibration, deterministic jitter can be effectively reduced, the eye pattern opening degree is improved, and the signal integrity of a high-speed link is improved.

The utility model discloses a multichannel programmable PWM drive circuit based on FPGA, comprising a first decoupling capacitor, a second decoupling capacitor, an FPGA chip, a bidirectional buffer chip, and an extended PWM output chip, the input end of the FPGA chip is connected with a + 1.2 V power supply signal, a + 3.3 V power supply signal, and a clock signal, the output end of the FPGA chip and the input end of the bidirectional buffer chip are connected with the + 3.3 V power supply signal, and the output end of the bidirectional buffer chip is connected with the output end of the extended PWM output chip. The first decoupling capacitor and the second decoupling capacitor are electrically connected with the output end of the bidirectional buffer chip, and the output end of the bidirectional buffer chip and the input end of the extended PWM output chip are connected with VCC voltage signals. The parallel multi-channel PWM drive circuit based on the FPGA can solve the technical problems that when a traditional parallel multi-channel PWM drive circuit based on the FPGA is used for guaranteeing phase synchronization and frequency consistency among multiple channels, complex clock management is depended, the parallel multi-channel PWM drive circuit is easily influenced by wiring delay and clock skew, and therefore waveform distortion is easily caused.

A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

The invention discloses a robot simulation consistency control method, and particularly relates to the technical field of robot simulation, and the method comprises the steps: 1, creating a central node Server and a plurality of Clients, and generating a SyncPoint message time sequence containing a timestamp, a channel category and a dependency relationship based on real vehicle data; 2, deeply coupling timestamps of a main link message and a bypass message by adopting Bundle binding, and forming a key value pair dependency relationship in a preprocessing stage; 3, synchronous control is established, the Client needs to request authorization and block waiting before sending, the Server broadcasts an analog clock and authorizes after verifying time sequence consistency, and clock skew is monitored in real time and dynamically compensated; and 4, the downstream Client feeds back a receiving state, intelligently releases non-key dependency waiting when the computing power is sufficient, restores a real vehicle multi-source data dependency relationship through Bundle binding, and eliminates behavior randomness caused by bypass message inconsistency.

The apparatus includes a clock skew calibration circuit configured to be coupled to the multi-phase clock generator via a plurality of delay lines, wherein the first clock skew calibration unit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signals and to generate a reduced frequency signal based on the clock signals; and a delay line control circuit configured to compare a duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal to adjust the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

The application discloses the technical field of video monitoring and image recognition, and particularly relates to a video monitoring transmission time delay detection method and system based on image recognition. First, stable texture features of an image are extracted by SIFT to generate a 128-dimensional descriptor, then a Lucas-Kanade algorithm is used to capture inter-frame motion trends to generate time features, and finally, attention mechanism dynamic weighting fusion is used to generate a space-time joint feature vector. Then, a dynamic template containing space-time features and a local clock is generated at a sending end, and a FLANN algorithm is used for cross-end matching at a receiving end. Through a double-calibration mechanism of basic time delay calculation, clock offset calibration and jitter compensation, the influence of network jitter and clock deviation is eliminated, and finally, the calibrated time delay is output. Based on this, the application has the advantages of avoiding the interference of network jitter on time delay detection accuracy and reducing the false alarm situation caused by instantaneous deviation through double-calibration time delay calculation and cross-end feature accurate matching design.

The present disclosure relates in one aspect to methods of adjusting a second system clock frequency of a slave or second device to a first system clock frequency of a first device connectable thereto via a unidirectional or bidirectional wireless data communication link so to reduce clock skew between the first and second system clock frequencies.

The invention discloses an encrypted traffic identification method based on endogenous behavior and physical feature modeling. The method comprises the following steps: extracting compliance traffic data blocks; calculating a protocol stack behavior entropy as a quantitative fingerprint based on the transmission layer dynamic behavior sequence; calculating an instantaneous clock offset value based on the physical clock signal sequence; calculating a behavior entropy anomaly score and a physical feature anomaly score; and constructing a multi-source evidence vector and a context feature vector, performing attention mechanism dynamic fusion based on the multi-source evidence vector and the context feature vector, and outputting a comprehensive risk score. According to the method, traffic decryption is not needed, and the inherent, stable and difficult-to-forge characteristics of a kernel and hardware of equipment are quantified through protocol stack behavior entropy and a physical clock offset map; performing cross-layer logic and physical rationality dual verification to generate quantifiable credibility evidence; and by utilizing an attention mechanism, a multi-source evidence vector and a context feature vector are intelligently constructed, and accurate and explainable risk judgment is output.

A hierarchical activation-broadcast network for column-oriented neural-network compute arrays is disclosed. Activation values corresponding to each processing row are distributed concurrently to all columns of processing elements through a hierarchical latch tree that fans out the signals synchronized within one clock period. The broadcast network maintains precise timing alignment among columns while minimizing capacitive loading and clock skew. The distribution fabric may be fabricated on a separate die or interposer and connected to the compute die by high-density hybrid bonds. The approach enables wide, low-skew activation delivery across large arrays, reducing energy consumption and improving frequency scalability for CASCADE architectures.

Far-end audio samples may be received corresponding to far-end audio that is output from one or more audio output components. Near-end audio samples may be received corresponding to near-end audio that is captured by one or more audio input components. A plurality of acoustic path estimates and a plurality of clock skew estimates may be calculated in an alternating order, using a state-space model, based at least in part on the far-end audio samples and the near-end audio samples. A first acoustic path estimate and a first clock skew estimate may be used to calculate a second acoustic path estimate. A first portion of the far-end audio may be filtered with the second acoustic path estimate to generate a replica of echo in the first portion of the far-end audio. The replica of the echo may be removed from a corresponding second portion of the near-end audio.

This invention discloses a system for eliminating clock skew in the coordinated control of redundant controllers, belonging to the field of clock synchronization technology. It includes a master controller, a synchronization source module, and multiple slave controllers. The master controller communicates with the multiple slave controllers via a bidirectional transmission channel for signal exchange, enabling the master controller to control the multiple slave controllers through the bidirectional transmission channel. The synchronization source module communicates with the master controller and the multiple slave controllers, sending interrupt trigger signals or time acquisition signals. The synchronization source module periodically sends interrupt trigger signals or time acquisition signals to the master controller and slave controllers, allowing them to periodically calibrate their clocks at equal intervals. This resets the clock skew value, preventing its accumulation and keeping it within a reasonable range.

The invention relates to the technical field of unmanned aerial vehicle cluster control, particularly provides a mobile node bidirectional time synchronization model and a link delay estimation method, and solves the problems of link asymmetry and clock drift on low-cost equipment. The method comprises the following steps: establishing a bidirectional time synchronization model and defining a local clock of each node, and exchanging and recording timestamps according to messages among the nodes; the timestamp is used for calculating link delay and performing preliminary time synchronization; a Kalman filtering method is used for estimating the relative speed and the accelerated speed between the nodes, and one-way link propagation delay is calculated through a kinematics equation; estimating the dynamic propagation delay; the recursive least square method is adopted to jointly estimate the clock skew and the clock drift, so that the calculation amount and the storage amount are reduced; meanwhile, a theoretical lower limit of the joint estimator is deduced to evaluate the estimation performance. The system comprises a model building module, a delay calculation module and a performance estimation module. According to the method, the precision error caused by link asymmetry is eliminated, and the dynamic node time synchronization precision is improved.

The invention relates to the technical field of wireless communication security and clock synchronization, and discloses a clock self-synchronization communication method based on double dynamic factors, which comprises the following steps that: an initiating end firstly generates a main factor Q and a cofactor P bound with a timestamp and a device ID (Identity), generates dynamic encryption strings S1 and S2 by using symmetric encryption and asymmetric encryption respectively, and combines the dynamic encryption strings S1 and S2 into a synchronous code C1; after analysis, the receiving end verifies the homology of the S1 and the S2 through bidirectional decryption, and equipment authentication and anti-replay are realized; if verification fails, starting data correction, dynamically fitting the ID by using a Hamming distance algorithm and comparing a timestamp; according to the method, the clock skew is calculated based on the valid timestamp passing verification, closed-loop calibration is triggered when the clock skew exceeds the standard, clock synchronization is embedded in security authentication, the replay attack resistance, authentication robustness and clock synchronization precision are remarkably enhanced, and deep integration of security and synchronization is achieved.

Techniques for clock distribution with fixed clock offsets are disclosed. In one aspect, a clock distribution network for a node array includes clock distribution circuitry of a plurality of nodes. At least one of the nodes is configured to receive a clock signal, provide the clock signal to computing circuitry, and provide the clock signal to a neighboring node. There can be a unit of delay between the clock signal at the node and the neighboring node. In certain embodiments, the node can provide the clock signal to a first neighboring node in a same column and a second neighboring node in a same row, where the first and second neighboring nodes receive the clock signal with substantially the same delay.

The application provides an error calibration device, method, phase-locked loop and chip. The device comprises a phase offset controller configured to input a feedback clock output by a DCO at a second time and a preset reference clock into a TDC; and an output calibrator configured to compare an actual code output by the TDC with a preset check code, and output a comparison result to the digital loop filter; wherein the actual code = a phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the check code is obtained by offsetting the feedback clock output by the DCO at a first time and / or the preset reference clock by the phase offset controller to form a preset phase difference, and inputting the reference clock and the feedback clock with the preset phase difference into the TDC; and the check code = the preset phase difference / the unit delay. By comparing the actual code with the check code, the unit delay contained in both the actual code and the check code can be eliminated, so as to alleviate the jitter of the clock output by the DCO.