3384results about "Generating/distributing signals" patented technology

The invention discloses an LCD display screen display fault judgment method, and relates to the related technical field of LCD display screen detection. Comprising the steps of synchronous acquisition and preprocessing of multi-source signals, feature extraction, establishment of a fault judgment model, generation of a dynamic test mode, dynamic generation of a targeted test image according to a preliminary detection result to excite a potential fault, iterative optimization of a test sequence by a Q-learning algorithm, and fault diagnosis. The invention also discloses a system for judging the display fault of the LCD screen. The system comprises a multi-source data acquisition module, a central processing unit, a memory and a user interface. Various data including display data, driving voltage / current monitoring data, temperature distribution, environment parameters and the like are synchronously collected through the optical sensor, the electric signal probe, the thermal imaging module and the environment sensor, all-directional information of the LCD display screen in the operation process can be obtained, and limitation and misjudgment possibly caused by a single data source are avoided.

Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.

The invention discloses an RFSOC-based FAST core array distributed collaborative observation and data fusion method and system, and the method comprises the steps: S1, system initialization: a master node RFSOC generates a global clock, achieves the phase synchronization of multiple board cards through an SYSREF differential signal, and completes the calibration of a three-stage clock tree; s2, signal acquisition and preprocessing: directly sampling a 3-8GHz radio frequency signal through an ADC (Analog to Digital Converter), and performing digital down-conversion to obtain a baseband signal; s3, intelligent resource scheduling: identifying a signal type based on an ESN (Echo State Neural Network), and dynamically allocating FPGA logic resources through an improved ant colony algorithm; s4, heterogeneous calculation acceleration: executing a 128-channel digital beam forming pipeline on the FPGA; s5, cross-domain data fusion; s6, collaborative observation planning; and S7, outputting data. The method is suitable for multi-beam synthesis, cross-region joint observation and mass data real-time processing scenes, and provides key technical support for solving the frontier scientific problems such as rapid radio storm origin and black hole activity monitoring.

The invention discloses a multi-sensory interaction synchronization system and method based on a dynamic timestamp, and relates to the technical field of human-computer interaction. The system comprises a time reference module which is used for providing a unified time reference for all devices through a high-precision time source; and the signal coding module is used for coding the visual, auditory, tactile and olfactory signals into data frames in a unified format, and embedding dynamic timestamps in the data frames, and the dynamic timestamps are used for indicating the decoding time of the signals in the terminal equipment. Through the high-precision time reference, the dynamic timestamp and the dynamic compensation technology, millisecond-level synchronization of multi-modal signals is achieved, immersion is improved, by means of the cross-platform protocol adaptation and semantic web technology, the equipment integration cost is reduced, federated learning and edge computing are fused, data privacy and system robustness are enhanced, and the system performance is improved. And in combination with dynamic priority scheduling and semantic network technologies, complex scene interaction experience is adaptively optimized, and core technical support is provided for multiple fields.

Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

Die or chip interconnect clock skew compensation can be performed for a multi -IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi - IC module that is receiving data and clock signals from a second die or chip of the multi -IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.

The invention discloses an electronic lead seal data management method based on a block chain, relates to the technical field of internet data services, and aims to solve the problems of node data asynchronization, state updating failure and potential safety hazards of an intelligent contract in the prior art. The data consistency is ensured through a distributed clock synchronization algorithm and a version number verification mechanism; the reliability and fault tolerance of state updating are improved by adopting an improved Byzantine fault-tolerant algorithm and an asynchronous two-stage transaction submission mechanism; data integrity and traceability are guaranteed through a state machine detection mechanism and transaction log records; the security and maintainability of the smart contract are improved based on an automatic code auditing algorithm and a proxy contract mode of a graph neural network; real-time data monitoring and exception repair are realized by using an under-chain auditing mechanism and a cross-chain data consistency verification protocol; according to the invention, the data consistency, the system safety and the reliability of electronic lead seal data management are obviously improved.

In one embodiments, a first device includes a first n-pulse-per-second (nPPS) output interface to be connected to a second nPPS input interface of a second device via a first clock connection, and to send a first pulse at time A to the second nPPS input interface for receipt at time B, and a first nPPS input interface to be connected to a second nPPS output interface of the second device via a second clock connection, to receive a second pulse at time D from the second nPPS output interface sent at time C, and to log time D in a first memory, and delay computation circuitry to compute a clock connection delay in the first clock connection and / or the second clock connection based on time A, time D, and a time difference between receiving the first pulse in, and sending the second pulse from, the second device.

The invention discloses an intelligent motion capture system and method of a multi-mode sensor, and the method comprises the steps: creating and installing links among an optical module, an inertia module, a touch module, a synchronization core module and a to-be-detected object; sending a synchronous starting pulse signal based on the synchronous core module, setting the synchronous starting pulse signal as a clock reference starting point, and starting the optical module, the inertia module and the touch module based on the clock reference starting point; performing data acquisition on a to-be-measured object based on the optical module, the inertia module and the touch module to obtain an object acquisition information data set; and creating an acquisition original timestamp based on the synchronous start pulse signal, creating a sensor network delay model to dynamically adjust the acquisition original timestamp to obtain a calibration timestamp, and analyzing and correcting the time offset of the object data acquisition information. The method and the device have the effect of improving the accuracy of intelligent motion capture of the multi-mode sensor.

The invention provides a method for automatically calibrating collected data of high-precision measurement and control deformation monitoring equipment, and belongs to the technical field of wind tunnel inner profile measurement. Multi-equipment clock synchronization is realized by establishing a unified time reference system, and measurement data of different frequencies are processed by adopting a CPU-GPU heterogeneous parallel processing architecture, so that the measurement accuracy is improved. The method comprises the following steps: performing three-level alignment on time, space and precision dimensions by using a multi-level clustering algorithm, eliminating clock differences among equipment by using a clock drift correction equation set, establishing a space coordinate system conversion matrix to unify a global coordinate system, and performing adaptive data fusion according to a precision weight by using a Kalman filtering fusion algorithm. And a data quality evaluation system is established to ensure the accuracy of a calibration result, a high-precision calibration data set is finally output, and the technical problem that the measurement precision is reduced due to space-time inconsistency of heterogeneous data of multiple devices is solved.

The invention provides a signal decoding method based on a PSI5 interface, and relates to the technical field of signal decoding, and the decoding method comprises the following steps: processing and adjusting a received PSI5 signal to obtain an accurate identification signal; and extracting a clock signal from the PSI5 signal, designing a clock compensation algorithm according to the quantum neural network, and dynamically adjusting the clock signal to obtain clock synchronization data. And determining a data frame boundary, and decoding the accurate identification signal to obtain original data. And performing comparative analysis on the original data and the PSI5 signal to obtain comparative difference data, judging whether the comparative difference data accords with a preset error type or not, and performing corresponding processing. According to the invention, fractional calculus processing is carried out on the received signal, then signal distortion is corrected by using a channel equalization method, and the quantum neural network is constructed to dynamically adjust the clock signal, so that clock synchronization is realized, a reliable time reference is provided for accurate processing of the signal, and the accuracy of signal decoding is improved.

An apparatus using in-memory compute (IMC) chiplet devices for inference-time compute acceleration. The apparatus is configured to accelerate the workload computations for neural network models, such as those for Large Language Models (LLMs) and reasoning models. The apparatus achieves high throughput and low latency using a chiplet design, digital IMC (DIMC) based engines, efficient die-to-die (D2D) interconnects, block floating point (BFP) numerics, and large high bandwidth on-chip memories. With modular chiplets and efficient interconnects, the accelerator apparatus can be easily scaled to accelerate workloads for models of different sizes. The DIMC configuration within the chiplet slices also improves computational performance and reduces power consumption by integrating computational functions and memory fabric. And by dynamically switching between precision levels based on real-time analysis of a target workload, computational efficiency can be optimized while maintaining the necessary level of accuracy for each step of the workload computation.

The invention discloses a cluster model acceleration method and device based on an FPGA, and relates to the technical field of model acceleration, and the method comprises the steps: converting a cluster simulation model into a digital circuit structure file, and burning the digital circuit structure file into an FPGA board card; splitting the digital circuit structure file into a plurality of independent calculation modules according to functions; packaging the calculation module into a plurality of IP cores based on the requirements of different individuals in the cluster; in response to input data received in the DDR of the FPGA board card, the hardware state machine triggers all the IP cores to execute corresponding tasks in parallel, and the calculation process of each IP core is controlled by taking a main clock of the FPGA board card as a reference; and each IP core writes the task processing result into a DDR (Double Data Rate) of the FPGA board card, and reads the DDR to obtain a simulation result of the cluster simulation model. The technical problems that an existing model acceleration method is poor in real-time performance and high in economic cost in a large-scale cluster simulation scene are solved, and therefore in the large-scale cluster simulation scene, high real-time performance of simulation can be guaranteed, and the economic cost can be effectively reduced.

Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.

A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.

Apparatuses, systems, and techniques to perform an application programming interface (API) to identify processor settings to be used when performing one or more software workloads. As an example, one or more processors comprising one or more circuits perform an API to identify processor settings to be used to configure processors assigned to perform a software workload based, at least in part, on one or more characteristics of that software workload.

The invention discloses a vehicle driving simulation test method and system based on digital twinning, belongs to the technical field of vehicle driving, and realizes real interaction of a driving behavior model and a control algorithm in a virtual scene by constructing a digital twinning body highly corresponding to an actual vehicle and a driving environment. Time stamps and coordinate information of all the modules are collected, time differences and space residual errors are extracted, a space-time semantic consistency index model is constructed, and the loading process is intelligently judged and optimized; when inconsistency is detected, adjustment is performed through clock synchronization and coordinate recalibration, a closed-loop optimization mechanism is formed, and high collaboration of the model and the environment is ensured, so that the accuracy, the stability and the credibility of the simulation system are improved, and the method is suitable for complex and changeable automatic driving test scenes.

Embodiments of the present disclosure describe techniques for implementing enhanced skew control for synchronizing two clock meshes in an IC or chip. A disclosed skew adjust control, methods, and systems enable effective and efficient operations to optimize a coarse delay setting to maintain for a functional mode of operation of the system, where only fine delay steps are applied to an adjustable one of the clock meshes, based on measured clock skew, to synchronize the clock meshes.

The invention discloses a service upgrading system, an electronic device, a method, a storage medium and a product, and relates to the technical field of computers, and the service upgrading system comprises a processor and a controller connected with the processor. Wherein the controller divides a monitored thread to obtain a first thread for carrying out an upgrade service and a second thread for carrying out a non-upgrade service, and the controller also obtains a total time slice and a retention time slice preset by the processor, and dynamically allocates an algorithm based on the total time slice, the retention time slice and the preset time slice; and determining a time slice allocated to the first thread, wherein the allocated time slice is used for representing the duration of the processor resources allocated to the first thread. And the processor generates a required clock signal in the time slice allocated by the first thread, wherein the clock signal is used for carrying out service upgrading. The stability of the clock signal generated by the controller is improved, and the success rate of service upgrading is further improved.

A digital frequency synthesizer includes a delay-locked loop (DLL) that generates time-delayed versions of a reference clock signal, a clock divider that executes an integer-division operation on one delayed clock signal to generate an integer-divided clock signal, and control circuitry that generates fractional data for enabling a fractional division. The digital frequency synthesizer further includes a first clock selector that selects one delayed clock signal as a DLL clock signal based on the fractional data, a delay chain that generates time-delayed versions of the DLL clock signal, and a second clock selector that selects one delayed clock signal as a selected clock signal based on the fractional data. A rising edge of the integer-divided clock signal is adjusted based on the selected clock signal to generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.

An audio playback method includes: calculating an estimated playback delay difference of a current audio data, wherein the estimated playback delay difference is a difference value between a set playback delay and an estimated playback delay of the current audio data on a playback device; in response to the estimated playback delay difference being between a first lower limit value and a first upper limit value, adjusting a playback rate of audio on the playback device based on the estimated playback delay difference; in response to the estimated playback delay difference being greater than the first upper limit value or less than the first lower limit value, deleting audio data from or adding audio data to an audio buffer based on the estimated playback delay difference; and adding the current audio data to the audio buffer to play audio data that is in the audio buffer.

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware-aware machine learning model training. An example apparatus includes a configuration determiner to determine a hardware configuration of a target hardware platform on which the machine learning model is to be executed, a layer generator to assign sparsity configurations to layers of the machine learning model based on the hardware configuration, and a deployment controller to deploy the machine learning model to the target hardware platform in response to outputs of the machine learning model satisfying respective thresholds, the outputs including a quantity of clock cycles to execute the machine learning model with the layers having the assigned sparsity configurations.

The invention discloses a time synchronization method of a system-on-chip, the system-on-chip and a vehicle. The time synchronization method of the system on chip comprises the following steps: determining daisy chain data transmission delay between a first hardware domain and a second hardware domain; determining a system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay; calibrating the clock of the second daisy chain counter according to the system clock difference, so that the clock of the second daisy chain counter is synchronized with the clock of the first daisy chain counter; determining a timestamp of the second subsystem based on first subsystem time information sent from the first hardware domain; wherein the first subsystem time information comprises a timestamp of the first subsystem and clock information of a first daisy chain counter; updating the system time of the second subsystem according to the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with the system time of the first subsystem; by adopting the method and the device, the time synchronization between the subsystems of the system on chip can be realized.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

According to the task scheduling and resource management system and method provided by the invention, full-link automatic management from peripheral event triggering to resource dynamic allocation and recovery is realized through close cooperation of the peripheral collaborative network, the dynamic power management module, the task scheduling module, the self-adaptive clock module and the exception monitoring unit. Compared with the prior art, the system not only can perform hardware-level scheduling in real time according to task priorities and system loads, but also can improve energy efficiency through regionalized power supply and clock frequency adjustment, supports rapid recovery and storage of task contexts, has a perfect fault monitoring and isolation mechanism, and is high in practicability. Therefore, the real-time performance, the energy consumption efficiency and the operation reliability of the system are obviously improved.

Scheduling and clock management for real-time system quality of service (QoS) is disclosed. In an implementations, a resource manager determines a target work rate based on respective job deadlines of a plurality of jobs on a processing platform. Determining the target work rate can include ordering the plurality of jobs based on the respective deadlines, determining an amount of work required to reach each of the respective deadlines, identifying one deadline among the respective deadlines as a most constraining deadline based on the amount of work required to reach that one deadline, and determining the target work rate based on the most constraining deadline. The resource manager adjusts a clock rate of the processing platform based on at least the target work rate.

An oscilloscope having a Nyquist frequency lower than an analog bandwidth includes an input configured to receive a signal under test; an analog-to-digital converter (ADC) to receive the signal under test, sample the signal under test at a sample rate, and produce digital samples of the signal under test; one or more processors configured to execute code that causes the one or more processors to: determine a set of candidate unit intervals by generating corresponding candidate histograms using the candidate unit intervals; determine a best unit interval from the candidate unit intervals based upon entropy measures of each candidate histogram; and reconstruct a representation of the signal under test using the digital samples and the best unit interval.

Apparatuses, systems, and techniques to perform an application programming interface (API) to identify processor settings to be used when performing one or more software workloads. As an example, one or more processors comprising one or more circuits perform an API to identify processor settings to be used to configure processors assigned to perform a software workload based, at least in part, on one or more characteristics of that software workload.