4770results about "Generating/distributing signals" patented technology

The invention discloses an LCD display screen display fault judgment method, and relates to the related technical field of LCD display screen detection. Comprising the steps of synchronous acquisition and preprocessing of multi-source signals, feature extraction, establishment of a fault judgment model, generation of a dynamic test mode, dynamic generation of a targeted test image according to a preliminary detection result to excite a potential fault, iterative optimization of a test sequence by a Q-learning algorithm, and fault diagnosis. The invention also discloses a system for judging the display fault of the LCD screen. The system comprises a multi-source data acquisition module, a central processing unit, a memory and a user interface. Various data including display data, driving voltage / current monitoring data, temperature distribution, environment parameters and the like are synchronously collected through the optical sensor, the electric signal probe, the thermal imaging module and the environment sensor, all-directional information of the LCD display screen in the operation process can be obtained, and limitation and misjudgment possibly caused by a single data source are avoided.

An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.

Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.

The invention discloses an RFSOC-based FAST core array distributed collaborative observation and data fusion method and system, and the method comprises the steps: S1, system initialization: a master node RFSOC generates a global clock, achieves the phase synchronization of multiple board cards through an SYSREF differential signal, and completes the calibration of a three-stage clock tree; s2, signal acquisition and preprocessing: directly sampling a 3-8GHz radio frequency signal through an ADC (Analog to Digital Converter), and performing digital down-conversion to obtain a baseband signal; s3, intelligent resource scheduling: identifying a signal type based on an ESN (Echo State Neural Network), and dynamically allocating FPGA logic resources through an improved ant colony algorithm; s4, heterogeneous calculation acceleration: executing a 128-channel digital beam forming pipeline on the FPGA; s5, cross-domain data fusion; s6, collaborative observation planning; and S7, outputting data. The method is suitable for multi-beam synthesis, cross-region joint observation and mass data real-time processing scenes, and provides key technical support for solving the frontier scientific problems such as rapid radio storm origin and black hole activity monitoring.

The invention discloses a multi-sensory interaction synchronization system and method based on a dynamic timestamp, and relates to the technical field of human-computer interaction. The system comprises a time reference module which is used for providing a unified time reference for all devices through a high-precision time source; and the signal coding module is used for coding the visual, auditory, tactile and olfactory signals into data frames in a unified format, and embedding dynamic timestamps in the data frames, and the dynamic timestamps are used for indicating the decoding time of the signals in the terminal equipment. Through the high-precision time reference, the dynamic timestamp and the dynamic compensation technology, millisecond-level synchronization of multi-modal signals is achieved, immersion is improved, by means of the cross-platform protocol adaptation and semantic web technology, the equipment integration cost is reduced, federated learning and edge computing are fused, data privacy and system robustness are enhanced, and the system performance is improved. And in combination with dynamic priority scheduling and semantic network technologies, complex scene interaction experience is adaptively optimized, and core technical support is provided for multiple fields.

An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.

Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

The invention discloses a waveform synchronization method and device, and the method comprises the steps: firstly generating a dot frequency signal which has the same frequency with a low-frequency reference clock and is synchronous with the low-frequency reference clock after a system is started, feeding back the dot frequency signal in the form of a clock after passing through a signal link, carrying out the digital phase discrimination with the low-speed reference clock, and adjusting the delay of the signal link. And the feedback clock and the reference clock are aligned in phase, so that the certainty of signal link delay is realized. By adopting the thought similar to a phase-locked loop, the problems of uncertain time delay and non-synchronization between channels between the DAC and the FPGA interface can be solved under the condition that an ADC is not used for collecting a feedback waveform and carrying out complex correction calculation, the hardware complexity and cost of the system are remarkably reduced, and the digital phase discrimination speed and the calibration speed are high. In addition, the precision of delay calibration mainly depends on the establishment and retention time of the D trigger, and very high precision can be achieved. The invention also discloses synchronous waveform generation equipment.

A multi-functional module system for a mobile device includes a docketing station and housing attachable to the mobile device. The housing includes an integrated wireless charging coil, and a plug head integrally formed with or attached to the housing. The plug head establishes a direct electrical / data connection between the housing and a port of the mobile device. The charging coil aligns with and charges a wireless-enabled accessory placed adjacent to the housing. The docking station includes an electrical connection interface to transmit power and / or data between the housing, the mobile device and a removable electronic module (REM) connected to the docking station. At least one port of the housing transfers power / data between an external device plugged into the port and the housing and / or the mobile device and / or the connected REM. The docking station provides a docking interface between the REM and housing via a magnetic coupling.

Die or chip interconnect clock skew compensation can be performed for a multi -IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi - IC module that is receiving data and clock signals from a second die or chip of the multi -IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.

The invention discloses an electronic lead seal data management method based on a block chain, relates to the technical field of internet data services, and aims to solve the problems of node data asynchronization, state updating failure and potential safety hazards of an intelligent contract in the prior art. The data consistency is ensured through a distributed clock synchronization algorithm and a version number verification mechanism; the reliability and fault tolerance of state updating are improved by adopting an improved Byzantine fault-tolerant algorithm and an asynchronous two-stage transaction submission mechanism; data integrity and traceability are guaranteed through a state machine detection mechanism and transaction log records; the security and maintainability of the smart contract are improved based on an automatic code auditing algorithm and a proxy contract mode of a graph neural network; real-time data monitoring and exception repair are realized by using an under-chain auditing mechanism and a cross-chain data consistency verification protocol; according to the invention, the data consistency, the system safety and the reliability of electronic lead seal data management are obviously improved.

A clock synchronization system and method are provided. The clock synchronization system includes: a pulse generation module, configured to receive an input first signal, perform sampling processing of the first signal to obtain a second signal, and generate a pulse signal according to the second signal; a voltage-controlled oscillator, configured to output a first output clock; the output frequency divider module, configured to perform frequency division on the first output clock, and synchronize, according to the pulse signal, the first output clock which has been subjected to the frequency division, so as to obtain a second output clock; and the synchronous output module, configured to receive the first output clock, the second output clock, the first signal, and the pulse signal, and perform synchronization processing on the first signal according to the first output clock, the second output clock and the pulse signal, so as to obtain a third signal.

In one embodiments, a first device includes a first n-pulse-per-second (nPPS) output interface to be connected to a second nPPS input interface of a second device via a first clock connection, and to send a first pulse at time A to the second nPPS input interface for receipt at time B, and a first nPPS input interface to be connected to a second nPPS output interface of the second device via a second clock connection, to receive a second pulse at time D from the second nPPS output interface sent at time C, and to log time D in a first memory, and delay computation circuitry to compute a clock connection delay in the first clock connection and / or the second clock connection based on time A, time D, and a time difference between receiving the first pulse in, and sending the second pulse from, the second device.

A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

The invention relates to an intelligent drawing method and system based on optical processing. The intelligent drawing method comprises the steps that holographic light field data, user interaction signals and environment parameters are collected in real time through a multi-dimensional sensor; performing time-frequency alignment and noise filtering on the multi-source heterogeneous data to generate holographic image data representing a multi-view projection deformation gradient and a user intention; based on the neural radiation field model and the dynamic deformation field function, adaptive compensation is carried out on projection geometric errors, phase correction parameters are generated, holographic layer energy distribution is optimized, and inter-layer crosstalk interference is inhibited; and a photon-electronic clock synchronization mechanism and a prediction rendering algorithm are combined to realize virtual-real space ultra-low delay interactive projection. According to the method, through deep fusion of optical processing and an intelligent algorithm, the problems of multi-view deformation accumulation, holographic layering crosstalk and too high interaction delay are solved, and the positioning precision, the projection definition and the real-time response performance of 3D painting in a complex scene are remarkably improved.

The invention discloses an intelligent motion capture system and method of a multi-mode sensor, and the method comprises the steps: creating and installing links among an optical module, an inertia module, a touch module, a synchronization core module and a to-be-detected object; sending a synchronous starting pulse signal based on the synchronous core module, setting the synchronous starting pulse signal as a clock reference starting point, and starting the optical module, the inertia module and the touch module based on the clock reference starting point; performing data acquisition on a to-be-measured object based on the optical module, the inertia module and the touch module to obtain an object acquisition information data set; and creating an acquisition original timestamp based on the synchronous start pulse signal, creating a sensor network delay model to dynamically adjust the acquisition original timestamp to obtain a calibration timestamp, and analyzing and correcting the time offset of the object data acquisition information. The method and the device have the effect of improving the accuracy of intelligent motion capture of the multi-mode sensor.

The invention provides a method for automatically calibrating collected data of high-precision measurement and control deformation monitoring equipment, and belongs to the technical field of wind tunnel inner profile measurement. Multi-equipment clock synchronization is realized by establishing a unified time reference system, and measurement data of different frequencies are processed by adopting a CPU-GPU heterogeneous parallel processing architecture, so that the measurement accuracy is improved. The method comprises the following steps: performing three-level alignment on time, space and precision dimensions by using a multi-level clustering algorithm, eliminating clock differences among equipment by using a clock drift correction equation set, establishing a space coordinate system conversion matrix to unify a global coordinate system, and performing adaptive data fusion according to a precision weight by using a Kalman filtering fusion algorithm. And a data quality evaluation system is established to ensure the accuracy of a calibration result, a high-precision calibration data set is finally output, and the technical problem that the measurement precision is reduced due to space-time inconsistency of heterogeneous data of multiple devices is solved.

The present invention relates to the technical field of biological information, and particularly relates to a single-device multi-physiological-parameter synchronization and fusion method and a multi-device multi-physiological-parameter synchronization apparatus. The single-device multi-physiological-parameter synchronization and fusion method comprises the following steps: constructing a one-to-one wireless transmission system; constructing a one-to-many wired transmission system; initiating a synchronization instruction; verifying information; and matching the information, so as to align first collection data packets of sensor modules. In the present invention, synchronization information is sent to several sensor modules at the same time by means of a collection main control module, and by means of a plurality of pieces of timestamp information, the collection main control module performs time mapping on collection data packets sent by a plurality of sensor modules without using the same clock source to connect the plurality of sensor modules in series, such that sensor selection is not limited, and a sampling rate can be adjusted in real time, thereby ensuring a relatively high efficiency of synchronization between the plurality of sensor modules.

In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.

The invention provides a signal decoding method based on a PSI5 interface, and relates to the technical field of signal decoding, and the decoding method comprises the following steps: processing and adjusting a received PSI5 signal to obtain an accurate identification signal; and extracting a clock signal from the PSI5 signal, designing a clock compensation algorithm according to the quantum neural network, and dynamically adjusting the clock signal to obtain clock synchronization data. And determining a data frame boundary, and decoding the accurate identification signal to obtain original data. And performing comparative analysis on the original data and the PSI5 signal to obtain comparative difference data, judging whether the comparative difference data accords with a preset error type or not, and performing corresponding processing. According to the invention, fractional calculus processing is carried out on the received signal, then signal distortion is corrected by using a channel equalization method, and the quantum neural network is constructed to dynamically adjust the clock signal, so that clock synchronization is realized, a reliable time reference is provided for accurate processing of the signal, and the accuracy of signal decoding is improved.

An apparatus using in-memory compute (IMC) chiplet devices for inference-time compute acceleration. The apparatus is configured to accelerate the workload computations for neural network models, such as those for Large Language Models (LLMs) and reasoning models. The apparatus achieves high throughput and low latency using a chiplet design, digital IMC (DIMC) based engines, efficient die-to-die (D2D) interconnects, block floating point (BFP) numerics, and large high bandwidth on-chip memories. With modular chiplets and efficient interconnects, the accelerator apparatus can be easily scaled to accelerate workloads for models of different sizes. The DIMC configuration within the chiplet slices also improves computational performance and reduces power consumption by integrating computational functions and memory fabric. And by dynamically switching between precision levels based on real-time analysis of a target workload, computational efficiency can be optimized while maintaining the necessary level of accuracy for each step of the workload computation.

The invention discloses a cluster model acceleration method and device based on an FPGA, and relates to the technical field of model acceleration, and the method comprises the steps: converting a cluster simulation model into a digital circuit structure file, and burning the digital circuit structure file into an FPGA board card; splitting the digital circuit structure file into a plurality of independent calculation modules according to functions; packaging the calculation module into a plurality of IP cores based on the requirements of different individuals in the cluster; in response to input data received in the DDR of the FPGA board card, the hardware state machine triggers all the IP cores to execute corresponding tasks in parallel, and the calculation process of each IP core is controlled by taking a main clock of the FPGA board card as a reference; and each IP core writes the task processing result into a DDR (Double Data Rate) of the FPGA board card, and reads the DDR to obtain a simulation result of the cluster simulation model. The technical problems that an existing model acceleration method is poor in real-time performance and high in economic cost in a large-scale cluster simulation scene are solved, and therefore in the large-scale cluster simulation scene, high real-time performance of simulation can be guaranteed, and the economic cost can be effectively reduced.

The utility model relates to a phase interpolator circuit, a clock recovery circuit and a chip, and the phase interpolator circuit mainly comprises a first clock filter which is used for filtering a high-frequency harmonic wave of a first clock signal to generate a first filtering signal; the second clock filter is used for filtering the high-frequency harmonic wave of the second clock signal to generate a second filtering signal; the phase mixer is coupled to the first clock filter and the second clock filter and is used for generating a phase mixed signal according to the first filtering signal and the second filtering signal; and the alternating current coupling output circuit is used for receiving the phase mixed signal and generating an interpolation clock signal according to the phase mixed signal. The phase interpolator circuit can support phase interpolation operation in a wide frequency range, the output linearity performance is optimized, the sensitivity of INL and DNL to power supply amplitude changes is weakened, the duty ratio of the output interpolation clock signal can be optimized, and the interpolation clock signal can support a high-speed interface half-rate transmission mode.

Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.

Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

Systems and methods for Out-of-Band (OOB) networking for heterogeneous computing platforms in low-power states. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform and a network device integrated into or coupled to the heterogeneous computing platform, and the network device may be configured to: wake up from a low-power state while a host processor of the heterogeneous computing platform remains in the low-power state, and access a cloud service through an OOB channel to check a status of an OOB command buffer while the host processor remains in the low-power state.

A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.