1772results about "Generating/distributing signals" patented technology

The invention provides a method for automatically calibrating collected data of high-precision measurement and control deformation monitoring equipment, and belongs to the technical field of wind tunnel inner profile measurement. Multi-equipment clock synchronization is realized by establishing a unified time reference system, and measurement data of different frequencies are processed by adopting a CPU-GPU heterogeneous parallel processing architecture, so that the measurement accuracy is improved. The method comprises the following steps: performing three-level alignment on time, space and precision dimensions by using a multi-level clustering algorithm, eliminating clock differences among equipment by using a clock drift correction equation set, establishing a space coordinate system conversion matrix to unify a global coordinate system, and performing adaptive data fusion according to a precision weight by using a Kalman filtering fusion algorithm. And a data quality evaluation system is established to ensure the accuracy of a calibration result, a high-precision calibration data set is finally output, and the technical problem that the measurement precision is reduced due to space-time inconsistency of heterogeneous data of multiple devices is solved.

The invention provides a signal decoding method based on a PSI5 interface, and relates to the technical field of signal decoding, and the decoding method comprises the following steps: processing and adjusting a received PSI5 signal to obtain an accurate identification signal; and extracting a clock signal from the PSI5 signal, designing a clock compensation algorithm according to the quantum neural network, and dynamically adjusting the clock signal to obtain clock synchronization data. And determining a data frame boundary, and decoding the accurate identification signal to obtain original data. And performing comparative analysis on the original data and the PSI5 signal to obtain comparative difference data, judging whether the comparative difference data accords with a preset error type or not, and performing corresponding processing. According to the invention, fractional calculus processing is carried out on the received signal, then signal distortion is corrected by using a channel equalization method, and the quantum neural network is constructed to dynamically adjust the clock signal, so that clock synchronization is realized, a reliable time reference is provided for accurate processing of the signal, and the accuracy of signal decoding is improved.

A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware-aware machine learning model training. An example apparatus includes a configuration determiner to determine a hardware configuration of a target hardware platform on which the machine learning model is to be executed, a layer generator to assign sparsity configurations to layers of the machine learning model based on the hardware configuration, and a deployment controller to deploy the machine learning model to the target hardware platform in response to outputs of the machine learning model satisfying respective thresholds, the outputs including a quantity of clock cycles to execute the machine learning model with the layers having the assigned sparsity configurations.

According to the task scheduling and resource management system and method provided by the invention, full-link automatic management from peripheral event triggering to resource dynamic allocation and recovery is realized through close cooperation of the peripheral collaborative network, the dynamic power management module, the task scheduling module, the self-adaptive clock module and the exception monitoring unit. Compared with the prior art, the system not only can perform hardware-level scheduling in real time according to task priorities and system loads, but also can improve energy efficiency through regionalized power supply and clock frequency adjustment, supports rapid recovery and storage of task contexts, has a perfect fault monitoring and isolation mechanism, and is high in practicability. Therefore, the real-time performance, the energy consumption efficiency and the operation reliability of the system are obviously improved.

An example chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh.

Disclosed are a system on chip, method and device supporting time synchronization, and a storage medium, which relate to the technical field of time synchronization, the system on chip synchronizes the time of an STBM in the system on chip with the time of an off-chip master clock through a first processor core according to a first preset period; based on the first time of the STBM after time synchronization, calibrating a hardware clock of the first network card to obtain a first time reference; calibrating the time of the STBM based on the first time to obtain a second time reference; synchronizing, by the second processor core, the time of the second network card with the time of the first time reference based on a first time difference between the first network card and the second network card; and synchronizing the system time with the time of the second time reference based on a second time difference between the second time reference and the system time of the operating system. According to the system, double time references can be obtained, sub-microsecond-level synchronization precision is realized, and the strict requirement of a high-precision time synchronization scene on time synchronization precision is met.

A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

The invention discloses a self-calibration and self-recovery method for an MEMS gas sensor, relates to the technical field of gas sensors, and solves the problem that in the prior art, once the sensor is mounted, the sensor is difficult to detach for calibration. According to the invention, the storage chip in which data is not lost after power failure is used as a parameter storage medium, the MCU reads parameters from the storage chip after initialization starting each time, timing is carried out according to a timer in the MCU, and automatic calibration is carried out each time set time is reached, so that the problem that data of a traditional single-chip microcomputer chip is easy to lose is avoided, and the reliability of a system is ensured. In addition, due to the fact that the off-chip storage chip is used, even if the system is powered off and stops working due to some reasons in the working process, stored parameters cannot be lost, and stability of the system is guaranteed. In addition, according to the invention, a timer is also utilized, under the condition that the system works normally, parameters are self-calibrated every 72 hours, and the problem that the system precision is reduced due to zero drift in long-term work is avoided.

A stacked apparatus using in-memory compute (IMC) chiplet devices for inference-time compute acceleration. The apparatus is configured to accelerate the workload computations for neural network models, such as those for Large Language Models (LLMs) and reasoning models. The apparatus achieves high throughput and low latency using a chiplet design, digital IMC (DIMC) based engines, efficient die-to-die (D2D) interconnects, block floating point (BFP) numerics, and large high bandwidth on-chip memories. With modular chiplets in stacked configurations with memory devices and efficient interconnects, the accelerator apparatus can be easily scaled to accelerate workloads for models of different sizes. The DIMC configuration within the chiplet slices also improves computational performance and reduces power consumption by integrating computational functions and memory fabric. And by dynamically switching between precision levels based on real-time analysis of a target workload, computational efficiency can be optimized while maintaining accuracy.

An embodiment of an IC is provided. The IC includes a memory, a controller, an intrusion detector and a memory clear circuit. The memory is configured to store sensitive data. The controller is configured to access the memory. The intrusion detector is configured to detect whether an intrusion event is present in response to an input signal. The memory clear circuit is configured to clear the sensitive data of the memory when the intrusion detector detects the intrusion event.

The invention provides a DFT clock architecture establishment method and device and electronic equipment, and belongs to the technical field of EDA, and the DFT clock architecture establishment method comprises the steps that a structured data file corresponding to clock planning information of a chip is acquired, the structured data file at least comprises an index field used for identifying clock uniqueness and a type field used for indicating a clock type, and the index field is used for identifying the clock uniqueness; and a parameter field for indicating clock attributes; generating a corresponding clock information object based on the values of the index field, the type field and the parameter field; based on the clock information object, a first configuration file and a second configuration file are generated, the first configuration file is used for driving a DFT tool to execute circuit insertion, and the second configuration file is used for driving a comprehensive or static timing analysis tool. The problems of configuration ambiguity, floating point error, asynchronous path omission, inconsistent OCC insertion and the like caused by dispersed and unstructured DFT clock planning information and dependence on manual transmission can be solved.

A system includes a plurality of semiconductor chips that are stacked on top of each other and that include first and second semiconductor chips. The first semiconductor chip includes a clock signal generating circuit, a transmitting circuit, and a receiving circuit. The clock signal generating circuit generates a clock signal and a delayed version of the clock signal. The transmitting circuit transmits a first data signal in response to the clock signal. The receiving circuit receives a second data signal in response to the delayed version of the clock signal. For example, the receiving circuit receives the delayed version of the clock signal at substantially the same time that the transmitting circuit receives the clock signal.

An information handling system peripheral display presents visual images with a display panel. A timing controller board has an edge connector that interfaces with a scalar board edge connector when the scalar board couples with slots at posts of the back side. The scalar board couples display cable ports to accept display information from an information handling system and extends the display cable ports out of openings of the midplane. The scalar board communicates visual information to the adjacent timing controller board through the edge connector without the use of a cable. A power board couples with posts and slots adjacent the scalar board to engage a power connector with power pins into a socket of the power board. Power communicates from the power board through the scalar board to the timing controller board and then to a backlight through a pogo pin and contact pad interface.

This application provides a clock synchronization method and a control system for a control system. The control system includes a first controller and a second controller. The first controller includes a first clock unit and a second clock unit, and the second controller includes a third clock unit. The clock of the first clock unit is different from the clock of the third clock unit, and the clock of the second clock unit is the same as the clock of the third clock unit. The method includes: the first controller and the second controller adding a timestamp to sensor data using a first clock, wherein the first clock is either the clock of the first clock unit or the clock of the third clock unit, ensuring clock consistency of the sensor data, thereby improving the accuracy of subsequent business processing.

The invention provides an optical signal synchronous calibration device and method of an optical computing system. The device comprises an optical probe array, an AI coprocessor, an optical path tuning engine and a low-speed electric feedback line, wherein the optical probe array is arranged on a chip; the optical probe array detects optical signals of wavelength channels corresponding to the plurality of optical calculation units and converts the optical signals into electric signals; the AI coprocessor drives a corresponding optical calculation unit to emit a detection pulse according to a pre-distributed time slot index variable, extracts a phase error from the electric signal and calculates a final calibration amount based on the phase error; the optical path tuning engine performs an optical path tuning operation based on the final calibration amount to calibrate an error of the corresponding optical calculation unit; and the low-speed electric feedback line transmits the electric signal to the AI coprocessor and transmits the detection pulse to the chip. According to the invention, through cooperation of spatial distributed detection and board-level centralized processing, real-time calibration in a dynamic environment is realized.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

Aspects disclosed in the detailed description include a processor-based system configured to dynamically mitigate peak current demand of a shared power rail powering a memory system. The processor-based system includes a plurality of processing units which utilize the memory system. The memory system is powered by the shared power rail. The processor-based system monitors a current demand of the shared power rail from the plurality of processing units, determines whether the current demand for the shared power rail exceeds a peak threshold, and, in response to the current demand exceeding the peak threshold, throttle one or more operating parameters of at least one of the plurality of processing units to reduce or slow access to the memory system and, thus, the current demand over the shared power rail.

The invention relates to the technical field of chip design, and provides a clock constraint generation method, electronic equipment and a storage medium, and the method comprises the steps: building a relational database based on hierarchical design information of a chip, the relational database comprising an instantiated module relationship in the chip and a cross-module port connection relationship; determining a clock source from the relational database, and traversing a propagation path of the clock source in the relational database by taking the clock source as a starting point; and generating a clock constraint file of the chip based on the propagation path of the clock source. According to the method, the electronic equipment and the storage medium provided by the invention, the hierarchical design information is converted into the dynamic, queriable and traversal relational database, so that the clock propagation path is reconstructed, the clock constraint file is driven to be automatically generated, and on the premise that the complete hierarchical design information is reserved, the automatic generation of the clock constraint file is realized. The efficient, accurate and complete propagation path reconstruction is realized, and the clock constraint generation efficiency and accuracy are improved.

Described herein is a computer implemented method for correcting for clock drift of a system clock in a signal sampling device comprising the system clock and configured to sample a signal in real time, the method comprising: obtaining data relating to an environmental parameter of an environment of the signal sampling device; matching the data relating to the environmental parameter to an environmental scenario; selecting, from a model set, a model tagged with the matched environmental scenario; and correcting for clock drift of the system clock using the selected model. Also described herein is a method for preparing a model set for clock drift correction, a sampling device, and a computer implemented method for correcting for clock drift of the system clocks of an array of signal sampling devices.

There is disclosed herein methods for synchronizing clocks in power grid devices. A method performed by a clock-leader unit comprises receiving an indication of a new clock signal for a plurality of clock-follower units to follow, for use in synchronizing clocks of the plurality of clock-follower units, and sending an instruction to the plurality of clock-follower units to calibrate based on the new clock signal. The method then comprises obtaining a confirmation that the plurality of clock-follower units has completed calibration and, in response to obtaining the confirmation, sending an instruction to the clock-follower units to follow the new clock signal. By co-ordinating the transition of clock-follower units to following the new clock signal, a synchronization of time operations between the clock-follower units can be better maintained.

The invention relates to a square wave generation method and system based on a DDS signal transmitter, and belongs to the technical field of digital electronic signal synthesis. The method comprises the following steps: calculating a digital analog signal sampling frequency based on a square wave output frequency set by a user, and obtaining a digital fundamental frequency phase signal according to a phase-locked loop precision range; mapping the digital fundamental frequency phase signal into a sinusoidal amplitude signal according to a digital phase accumulation mechanism to obtain a digital-analog conversion clock, binarizing the sinusoidal amplitude signal, and outputting a square wave output period; dividing a square wave output period into a low level region and a high level region according to the precision range of the phase-locked loop, reading a square wave output frequency set by a user through a random storage address, and outputting a non-offset phase-locked square wave; and constructing an error accumulation self-checking architecture to calculate a frequency control word, and when detecting that the frequency control word has a decimal discarding error, recalculating the frequency control word.

Technology related to calibrating synchronization of a data signal to a forwarded clock signal is described. A circuit includes a receiver circuit and a clock-to-data synchronization circuit. The receiver circuit receives a data signal and includes two inverters and two resistors. The clock-to-data synchronization circuit receives the data signal and the clock signal and determines an indication of synchronization between the data and clock signals. The clock-to-data synchronization circuit adjusts, using the indication, a parameter of the receiver circuit to synchronize the data signal and the clock signal.

The invention discloses a clock synchronization system. The clock synchronization system comprises a trigger group and a frequency divider group, the trigger group comprises N triggers, and the frequency divider group comprises N frequency dividers; the trigger group receives N paths of clock signals and one path of SYNC pulse signal, the N paths of clock signals are respectively transmitted to the N frequency dividers, and the N paths of pulse signals output by the trigger group are respectively transmitted to the N frequency dividers, N is a positive integer greater than 1, through the technical scheme of the invention, the risk of generating a metastable state can be reduced, and the power consumption can be reduced at the same time.

Provided are a time synchronization method, apparatus and time synchronization system of an intelligent driving system, relating to the technical fields of autonomous driving, electronic technology, and time synchronization. The method includes: obtaining (S210) a second-level universal time and a corresponding Pulse Per Second signal; based on a first local timestamp of a captured Pulse Per Second signal, a second local timestamp of an execution time instant of an interrupt service routine, and a first global timestamp, determining (S220) a second global timestamp corresponding to a predetermined edge of the Pulse Per Second signal; based on a global timestamp of a current time instant and the second global timestamp, obtaining (S230) a sub-second time of the current time instant; based on the second-level universal time and the sub-second time, obtaining (S240) an accurate time of the current time instant.

Systems and methods are disclosed for clock phase calibration between source logic and a coupled serial data link transmitter, enabling low-latency synchronization into the transmitter. In calibration mode, a phase relationship is monitored between a first clock, driving the source logic, and a second clock, tightly synchronized with a serial clock of the data link. The first clock is adjusted to a first phase at which the first and second clocks are aligned. The first clock phase is set for operation mode based on the first phase. Monitoring uses a D-type flip-flop as a phase detector. Adjustment is in steps of half the serial clock period. Variations are disclosed.

A first network device includes a pair of clock tree circuits, a feedback path, and a transceiver. The pair of clock tree circuits is configured to generate output clock signals, which are complementary to each other. The feedback path includes a skew detection circuit and a gain amplifier. The skew detection circuit detects a skew in the output clock signals and generates a pair of voltage signals based on a voltage-to-current and a current-to-voltage conversion of the output clock signals. The pair of voltage signals is indicative of the skew between the output clock signals. The gain amplifier amplifies the pair of voltage signals and, based on the amplified pair of voltage signals, adjusts respective delays in the output clock signals. The transceiver, based on the output clock signals, controls transfer of data to or from a second network device that is separate from the first network device.

The invention relates to a clock management structure, a system on chip and electronic equipment, and the clock management structure comprises a phase-locked loop and an arbitration frequency division module connected with the phase-locked loop. The phase-locked loop is deployed in the PHY; the phase-locked loop is used for generating a phase-locked loop clock of X channels according to an externally input clock signal; the arbitration frequency division module is used for processing the phase-locked loop clocks of the X channels to generate an MAC interface clock, and synchronizing the MAC interface clock to an MAC interface and a port corresponding to each channel; wherein X represents the total number of channels corresponding to a plurality of ports between the PHY and the MAC. According to the clock management structure, the cross-clock domain design in the SoC design is greatly reduced, and the clock structure in the SoC is simplified, so that the area of the SoC chip is reduced.