168 results about "Microarchitecture" patented technology

The invention discloses a low-power-consumption single-emission out-of-order execution RISC-V processor, which comprises seven stages of pipeline architecture, namely an instruction fetch unit, an instruction buffer unit, a decoding unit, an emission unit for single instruction emission, a physical register file, an execution unit for parallel out-of-order calculation and a retirement unit in sequence, and the instruction fetch unit is used as the front end of the RISC-V processor; a five-level pipeline architecture formed by the decoding unit, the transmitting unit, the physical register file, the execution unit and the retirement unit is used as the rear end of the RISC-V processor; through the technical scheme, the invention provides a micro-architecture which is more balanced in performance and power consumption, so that the applicability of a processor core in a scene with high computing requirements and sensitive power consumption is improved.

The invention provides a node task migration and scheduling system based on digital twinning, and relates to the technical field of computer system structures and data processing. Computing resource interference in a multi-tenant sharing environment is quantized by sensing a cross-tenant noise coefficient and a state synchronization complexity entropy in a node micro-architecture; extracting track features of the mobile terminal, calculating spatial discrete variance, generating a self-adaptive migration decision hysteresis factor, and converting the migration decision hysteresis factor into decision damping to inhibit invalid high-frequency reciprocating migration; constructing a digital twin sandbox before physical cutover, cooperating with a chaos scene injection engine to inject a composite fault operator into a bottom layer, and performing actuarial calculation on service continuity retention after risk adjustment by using a fidelity integrator; and finally, a bottom layer controller is linked through safety baseline comparison to execute physical flow switching. According to the method, network boundary deduction is completed on the premise that physical bandwidth is not consumed, the interruption risk caused by state hard switching is avoided, and smooth transition of stateful services is effectively guaranteed.

The invention provides a time sequence scene-oriented chip architecture level power consumption evaluation method, which comprises the following steps of: S100, generating an original data set by utilizing micro-architecture design parameters of a chip to be designed and adding simulation excitation; removing redundant data in the original data set, merging to obtain a preprocessed data set, and training a preset LSTM-based power consumption prediction model; and adjusting the micro-architecture design parameters and the ESL model, regenerating input features, and inputting the input features into the trained LSTM-based power consumption prediction model to obtain a power consumption prediction result. According to the method, the multi-dimensional features are introduced, the influence of different workloads and architecture configurations on the power consumption is comprehensively considered, and the time sequence processing capability of the LSTM model is utilized, so that the time dependency relationship in power consumption fluctuation can be effectively captured, and the power consumption prediction precision is remarkably improved, especially in a dynamically changing time sequence scene.

Aspects disclosed in the detailed description include a processing unit for dynamically reconfiguring micro-architectural features of the processing unit in response to a workload being processed on the processing unit and a processing unit control unit configured to receive a plurality of signals from the processing unit. The plurality of signals are indicia of the workload being processed on the processing unit. In response, the processing unit control unit determines whether performance, power consumption, or both, of the processing unit may be improved by modifying a micro-architectural feature. In response to determining that performance or power consumption of the processing unit may be improved by modifying micro-architectural features, the processing unit control unit triggers the processing unit to modify one or more of its micro-architectural features. The processing unit, in response to being triggered by the processing unit control unit, modifies one or more of its micro-architectural features.

The invention provides a Bayesian optimization-based CPU micro-architecture parameter exploration scheme, and aims to realize end-to-end CPU design space exploration and optimization by constructing a multi-confidence CPU micro-architecture parameter exploration device, and the scheme integrates the advantages of simulation tools with different confidence degrees, and has the advantages of being simple in structure, convenient to use and high in efficiency. According to the technical scheme, low-cost accurate calibration of low-confidence simulation is achieved, more accurate feedback information is provided for the multi-confidence Bayesian optimization device, in addition, an appropriate confidence simulation tool is selected according to the real-time distribution characteristics of the data samples, and therefore the optimal balance of the accuracy and efficiency of CPU design parameter exploration is achieved. In general, the scheme effectively coordinates the contradiction of different confidence simulation tools in the aspects of accuracy and time consumption, and remarkably improves the exploration efficiency of the CPU micro-architecture design parameters.

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

A pipelined decoding microarchitecture design method for RISC-V vector instructions includes the following steps: S1, extracting an instruction packet according to a PC, performing preprocessing, and writing a preprocessing result, each instruction field and preprocessed instruction information into a cache; S2, reading the cache, obtaining pre-decoding result data and recognizing each configuration instruction; S3, transmitting the pre-decoding result data to an instruction buffer, and acquiring field information, a split quantity and predicted vtype information; and splitting each instruction into multiple microoperations, and constructing a queue to store each microoperation; and S4, transmitting first, by means of the queue, each configuration instruction, performing decoding and execution, acquiring vtype information generated after execution, and when the vtype information generated after execution is identical with the predicted vtype information, controlling the number of microoperations input to multiple decoders, and transmitting a decoding result to an instruction slot.

The invention relates to the technical field of confidential computing, and discloses a data credibility-oriented vehicle-mounted integrated security computing system and credibility construction method, which comprises the following steps of: establishing a static trust chain by using a hardware trust root, shielding external interruption in a credible execution environment, and controlling a performance monitoring unit; synchronously collecting real-time hardware micro-architecture events of the key business algorithm to generate a runtime feature vector; according to the method, the instruction stream during operation is anchored by utilizing the physical characteristics of the micro-architecture, the hijacking attack of the control stream is accurately identified in a ciphertext environment, the hijacking attack of the control stream is accurately identified, the hijacking attack of the control stream is accurately identified, the hijacking attack is accurately identified, and the hijacking attack of the control stream is accurately identified. Strong coupling verification of a calculation result and an execution behavior is realized, and logic safety of a vehicle-mounted platform is ensured.

Capability storage circuitry 30, 32, 60, 34 stores at least one capability specifying a capability value and capability metadata indicative of constraints on valid use of the capability value. Capability checking circuitry 44 determines whether a capability-controlled operation to be performed by the processing circuitry with reference to a target capability is allowed, based on whether the capability-controlled operation satisfies the constraints indicated by the capability metadata of the target capability, and triggers an error handling response when the constraints are not satisfied. Micro-architectural control circuitry 40, 42, 23 controls a micro-architectural control function, other than determining whether the capability-controlled operation is allowed, depending on the capability metadata specified by a hint capability used to provide a hint to the micro-architectural control function.

A single-instruction multi-thread processor micro-architecture device oriented to neural network parallel scheduling comprises a front-end instruction fetching module, an instruction cache module, a decoding module, an arithmetic logic operation unit, a multiplication and division module, a memory access unit and a data cache module, and the micro-architecture device allocates a unique thread number for each thread. Threads are organized into thread groups, and in each period, the fair alternate arbiter selects an instruction from an instruction buffer of the thread group and sends the instruction to a subsequent decoding stage. The micro-architecture not only solves challenges faced by end-side equipment when processing high-performance calculation requirements such as neural network reasoning, but also provides an effective solution capable of reducing energy consumption and improving calculation efficiency through an innovative architecture design. The method is of great significance in promoting development of end-side AI application.

The invention discloses a branch prediction unit power consumption management method and device, and the method comprises the steps: setting a multi-stage branch predictor and a low-power-consumption control logic coupled with the multi-stage branch predictor in a processor core micro-architecture, and enabling the multi-stage branch predictor to comprise three stages of predictors which are sequentially accessed in an assembly line, the hardware resource consumption and the prediction accuracy of each predictor are gradually increased from front to back; monitoring the prediction condition of each predictor in real time through low-power-consumption control logic, and closing all predictors behind the first predictor meeting the prediction requirement within a first preset time according to a front-to-back sequence; branch jump addresses are divided into high-order address fields and low-order address fields by BTBs in the multiple levels of predictors except the first-level predictor to be stored in different storage blocks, and label registers used for taking the high-order addresses as label indexes are arranged. The power consumption unit of each predictor can be finely controlled, the energy consumption is greatly reduced, system-level cooperation is not needed, and the universality is high.

The invention discloses a micro-architecture design space exploration method based on deep learning. The method comprises the following steps: acquiring micro-architecture parameters of a target processor, forming a design space, acquiring performance indexes of different design points in the design space, and dividing key modules based on the design points; creating a directed acyclic sub-graph according to the key module, and constructing a prediction model by using a graph attention network to obtain a parameter optimal solution meeting a design target in the directed acyclic sub-graph; splicing the directed acyclic sub-graphs into a global graph to obtain interconnection parameters of key modules, introducing federal learning to train a global prediction model, and predicting performance data of an optimal solution of the evaluation parameters based on the global graph; and when a performance evaluation result meets a preset performance standard, outputting a target configuration parameter of the target processor under each configuration dimension. According to the method, the micro-architecture design space is explored in the graph embedding space, decision support is provided for chip design, and the design efficiency and flexibility are improved by adopting the thought that different design stages and design modes are coordinated.

The invention belongs to the technical field of embedded system information security, and particularly discloses a program control flow protection system and method based on stack data confidentiality and integrity. According to the method, the key stream is generated and managed during memory access of the special hardware for micro-architecture level design, and quick encryption and decryption calculation of the stack key data is realized through the exclusive-or operation of the key stream and the stack data. The stack data confidentiality protection supports the burst transmission property of an AHB-Lite bus on which stack data transmission depends, and the execution overhead of a program control flow protection method is reduced; on the basis of data encryption, MAC codes are calculated and verified when stack data are written in and read out based on a stack data integrity verification architecture of the MAC codes, real-time detection of tampering of stack key data is achieved, and program control flow abnormity is found in time. Through parallel encryption and decryption and integrity verification of the stack data, protection of the program control flow is realized from the aspect of stack data protection.

The invention belongs to the technical field of cloud computing heterogeneous resource scheduling, and particularly provides a multi-architecture virtualization environment integration and unified operation and maintenance method and system, and the method comprises the steps: detecting the underlying hardware characteristics of a source architecture and a target architecture; generating a hardware semantic abstract model based on the underlying hardware characteristics; carrying out compatibility analysis on the cross-architecture virtual machine instruction stream, and identifying atomic operation semantic conflicts and interrupt routing logic conflicts; generating an instruction translation rule and a micro-architecture cleaning strategy; converting an instruction stream and cleaning a branch predictor of a source architecture and a residual state of an out-of-order execution buffer area; and synchronizing the cleaned micro-architecture state and the conversion instruction stream to the target virtual machine. According to the method and the system, instruction stream conversion in a virtual machine migration process can be dynamically matched with micro-architecture characteristics of a target architecture, seamless connection of execution environments in a cross-architecture migration process is realized, cross-architecture conflicts can be prevented, and the problems of migration conflicts and performance degradation of the virtual machine of a virtualization platform are solved.

The invention discloses a double-write-back embedded scalar processor micro-architecture, which belongs to the technical field of embedded scalar processors, and comprises an arbitration component for arbitrating a program counter value flowing into an assembly line; the instruction fetching part is used for acquiring instruction data; the decoding component is used for acquiring a memory access operation code and a memory access operand when the instruction is a memory access instruction, and acquiring a non-memory access operation code and a non-memory access operand when the instruction is a non-memory access instruction; the execution component is used for calculating a memory access address according to the memory access operand; executing the non-memory access instruction according to the non-memory access operation code and the non-memory access operand to obtain a non-memory access instruction execution result; the memory access component is used for executing the memory access instruction according to the memory access operation code and the memory access address to obtain memory access data; and the write-back component is used for executing write-back operation of the memory access instruction and / or the non-memory access instruction according to the memory access data and / or the non-memory access instruction. According to the double-write-back embedded scalar processor micro-architecture, the performance, reliability and flexibility of an embedded scalar processor can be improved, and power consumption can be reduced.

The invention belongs to the technical field of nonlinear heat conduction control, and particularly discloses a coating thickness real-time prediction control method integrating microarchitecture search and physical constraint, which comprises the following steps: establishing a coating heat conduction physical model; utilizing a Newton Leibniz formula to convert a two-dimensional nonlinear Volterra type integral equation corresponding to the coating heat conduction physical model into an equivalent equation set; constructing a micro neural architecture search space; designing a double-layer optimization objective function; and performing online thickness prediction and feedback control. According to the method, differential neural architecture search and a physical information neural network are combined, the problem of nonlinear integral equation solving of thickness distribution in the heat conduction process of the coating material in the high-temperature environment is solved, and self-adaptive prediction and control of the coating thickness are achieved.

A simulation method for simulating a target circuit design comprising a plurality of micro-architecture hyper-parameters. The method comprises decompiling a binary code to obtain a control flow graph comprising multiple basic blocks (101, 120); generating multiple basic block chains, BBCs, based on the plurality of basic blocks taking account of the micro-architecture hyper-parameters (102, 130); performing, for each BBC, cycle-accurate simulation (104, 150) based on the determined context (103, 140), to obtain cycle count information (150); storing the cycle count information into a database (105, 160); performing instruction-accurate simulation (106) using the binary code, to obtain instruction traces indicating executed BBC; retrieving, for each executed BBC, corresponding cycle count information from the database (107); and determining overall cycle count information of the binary code on the target circuit design by accumulating the retrieved cycle count information of the executed BBCs (108). In this way, a fast and accurate simulation can be achieved.

The embodiment of the application discloses a kind of collaborative evaluation method for exploring the upper limit of processor micro-architecture performance and related device, the method includes that various idealized micro-architecture components are constructed according to the collaborative process of ideal model by real processor model, processor micro-architecture performance is collaboratively evaluated, and collaborative process includes: real processor model sends instruction query and information request to ideal model, and the request carries the memory address of dynamic instruction;Ideal model executes dynamic instruction according to memory address and obtains target value in normal working state, and target value is returned as the response of the request to real processor model;Real processor model executes dynamic instruction and obtains actual value in execution phase;Target value and actual value are verified in submission phase, and verification result is obtained.Using the embodiment of the application, the theoretical performance upper limit of value prediction and other speculative execution techniques can be accurately quantified, and the real performance bottleneck of the entire processor system integrated with the technique can be identified.

This invention discloses a quantum-resistant method and system based on stateless signatures and execution isomorphism, belonging to the field of quantum-resistant cryptography. First, the sender generates an mKEM broadcast payload based on a modulus error rounding algorithm and signs it using a stateless hash signature algorithm. The receiver performs microsecond-level verification of the signature at the network card driver layer; if verification fails, the signature is silently discarded. After successful verification, a dedicated PQC hardware engine decapsulates the signature, implicitly outputting a pseudo-random scrap key if verification fails. The operating system executes an I / O-aware microarchitecture with isomorphic execution, forcing subsequent processes to maintain physical isomorphism in system calls, memory accesses, and peripheral bus activities, regardless of whether the key is real or scrap. This invention eliminates the risk of private key leakage caused by cloud-based state management through stateless signatures and completely eliminates distinguishable side-channel fingerprints across the entire link through physical-level execution isomorphism, achieving system-level quantum-resistant security in high-concurrency scenarios.

The invention relates to a low-overhead processor cache micro-architecture defense method and device and computer device.The low-overhead processor cache micro-architecture defense method comprises the steps that when a missing state keeping register module takes out a loading instruction waiting for data from a replay queue, a target branch mask of the loading instruction is obtained; the replay queue is used for storing an instruction which is stagnated due to miss of the cache; judging whether the loading instruction is in a speculative execution state or not according to the target branch mask; and when the loading instruction is in the speculative execution state, stopping a cache write-in operation corresponding to the loading instruction. Through the method and the device, the problem of sensitive information leakage caused by incapability of defending against the cache side channel attack is solved, defending against the cache side channel attack is realized, and sensitive information leakage is prevented.

The invention discloses a period precise simulator design method for a combinable core particle network, and relates to the technical field of core simulation testing, and the method comprises the steps: designing a simulation frame of a combinable core particle network simulator; wherein the simulation framework comprises a two-stage core particle network configuration unit and a multi-thread parallel simulation framework; carrying out combinable topology modeling, modular routing mechanism modeling and heterogeneous router micro-architecture modeling on the combinable core particle network; performing protocol layer protocol conversion modeling, protocol layer flow control mechanism modeling, adaptation layer retransmission mechanism modeling and physical layer electrical behavior modeling on the core particle interconnection protocol interface; based on the above design, the period precision simulator for the combinable core particle network is constructed. By designing the simulation framework, more accurate actual core particle network behaviors can be obtained; a higher simulation speed is realized through a multi-thread parallel simulation framework, multi-thread parallel accelerated simulation under a large-scale network is supported, and the simulation test efficiency is improved.

A simulation method for simulating a target circuit design comprising a plurality of micro-architecture hyper-parameters. The method comprises decompiling a binary code to obtain a control flow graph comprising multiple basic blocks (101, 120); generating multiple basic block chains, BBCs, based on the plurality of basic blocks taking account of the micro-architecture hyper-parameters (102, 130); performing, for each BBC, cycle-accurate simulation (104, 150) based on the determined context (103, 140), to obtain cycle count information (150); storing the cycle count information into a database (105, 160); performing instruction-accurate simulation (106) using the binary code, to obtain instruction traces indicating executed BBC; retrieving, for each executed BBC, corresponding cycle count information from the database (107); and determining overall cycle count information of the binary code on the target circuit design by accumulating the retrieved cycle count information of the executed BBCs (108). In this way, a fast and accurate simulation can be achieved.

The invention belongs to the technical field of intelligent scheduling, and particularly relates to a heterogeneous cloud container cluster scheduling model training method and scheduling method based on topology awareness, and the training method comprises the steps: obtaining a cluster topological graph; obtaining a state vector time sequence of the nodes based on the node operation data, wherein each state vector comprises a performance index representing bottom layer resource contention; obtaining a queue state matrix; processing the state vector time sequence by using a feature extractor to obtain a node initial embedding vector; processing the initial embedded vectors of all the nodes by using a graph attention network to obtain a cluster global topology vector; obtaining a joint observation state based on the cluster global topology vector and the queue state matrix; inputting the joint observation state to the Actor-Critic network to generate a scheduling strategy; the accumulated rewards are maximized through a near-end strategy optimization algorithm, and network parameters are updated; and connecting the feature extractor, the graph attention network and the decision network to form a scheduling model. And the topological relation between the nodes is globally sensed, the interference attribute of the micro-architecture is captured, and accurate scheduling is realized.

The application provides an RISC-V multi-core heterogeneous platform intelligent load balancing method and system, and relates to the technical field of resource allocation and scheduling. Micro-architecture performance data of each processing core in the RISC-V multi-core heterogeneous platform is acquired to construct a state vector; the micro-architecture performance data comprises instruction cycle number, cache miss rate at each level and memory pause proportion; the state vector is input into a pre-trained deep Q network model to generate optimal action instructions, so that the load balancing of thread resources and core capacity is realized; the optimal action instructions comprise thread migration, thread exchange and core frequency adjustment; the pre-training of the deep Q network model is performed on a parallel computing program running on the RISC-V platform; the environment is randomly disturbed before the program runs; the action is executed through a random strategy, and state, action and reward data are collected; an offline experience dataset is constructed to perform pre-training. Dynamic, cooperative and adaptive optimization of parallel computing of the RISC-V multi-core heterogeneous platform is realized.

The presently disclosed subject matter provides an approach to address the needs for microscale control in shaping the spacial geometry and microarchitecture of 3D collagen hydrogels. For example, the disclosed subject matter provides for compositions, methods, and systems employing N-sulfosuccinimidyl-6-(4′-azido-2′-nitro-phenylamino)hexanoate (“sulfo-SANPAH”), to prevent detachment of the hydrogel from the anchoring substrate due to cell-mediated contraction.

The invention discloses an ARM (Advanced RISC Machines) platform cache covert communication defense method based on noise loading injection, and the cache covert communication becomes possible due to the continuous expansion of a TEE (Trusted Execution Environment) attack surface and the vulnerability of a TrustZone technology in the aspect of micro-architecture isolation. On the basis of a TrustZone technology, a defense mechanism for cache covert communication is added, and a cache covert communication defense architecture based on noise loading injection is designed. Based on the architecture, a dynamic monitoring mechanism, a strategy optimization mechanism and a noise injection mechanism are provided. And the system security and the system performance are monitored through a dynamic monitoring mechanism. An optimal noise injection strategy is generated through a strategy optimization mechanism, and the noise injection frequency and intensity are calculated in real time. And data loading is carried out through a noise injection mechanism, and cache covert communication is resisted. According to the defense method, the security of the original architecture is improved, low performance overhead is realized, and the security and performance of the system are balanced.

The application provides a hidden PMU reverse engineering general framework based on differential analysis and simulation verification. The framework can efficiently analyze the function and underlying micro-architecture behavior of Intel processor hidden PMU events. By observing the count change of the entire event space during the execution of a carefully designed instruction fragment, the underlying micro-architecture behavior related to these events is inferred. Based on these initial inferences, a logically equivalent simulator is implemented to model these events. Through the differential analysis between the simulator count and the real CPU count, the simulator is gradually optimized to be consistent with the real CPU behavior, enabling us to reveal the micro-architecture features behind the hidden PMU events. The application has wide application prospects in the fields of performance monitoring, micro-architecture research and security detection, not only improving the hardware resource utilization efficiency of performance counters, but also significantly expanding the ability range of processor performance analysis.

The invention discloses a method and system for verifying an RISC-V processor and a computer readable storage medium. The method comprises the following steps: analyzing an RISC-V official manual and a micro-architecture user manual, and generating a static instruction-resource mapping table; and generating a first test instruction sequence for each instruction in the static instruction-resource mapping table, executing the first test instruction sequence by using an RISC-V processor simulation model constructed by a software simulator, and dynamically calibrating the static instruction-resource mapping table in the execution process. And traversing the instruction and resource mapping relationship in the calibrated static instruction-resource mapping table, analyzing RISC-V processor verification logic, and if a conflict is found, outputting a conflict report so as to complete defect repair before RTL code writing. According to the application, hardware behaviors can be accurately associated, the problem of disjunction of semantics and micro-architecture is solved, and conflict prediction in an architecture design stage and end-to-end automatic verification from instruction semantics to micro-architecture behaviors are realized.

Provided is a secured semiconductor device and method for securing such a device, the device comprising an additional secured bus for transfer of data from / to the central processing unit to / from a primary memory or an additional dedicated memory, the additional secured bus bypassing the micro-architectural load port and / or the micro-architectural line fill buffer, and / or the cache memory, and the instructions set of the central processing unit further implements two operations for a secured transfer, a first operation allowing to securely load data in the central processing unit from the primary memory through the additional secured bus, and a second operation allowing to securely store data from the central processing unit in the primary memory through the additional secured bus.