28 results about "Microarchitecture" patented technology

This invention discloses a quantum-resistant method and system based on stateless signatures and execution isomorphism, belonging to the field of quantum-resistant cryptography. First, the sender generates an mKEM broadcast payload based on a modulus error rounding algorithm and signs it using a stateless hash signature algorithm. The receiver performs microsecond-level verification of the signature at the network card driver layer; if verification fails, the signature is silently discarded. After successful verification, a dedicated PQC hardware engine decapsulates the signature, implicitly outputting a pseudo-random scrap key if verification fails. The operating system executes an I / O-aware microarchitecture with isomorphic execution, forcing subsequent processes to maintain physical isomorphism in system calls, memory accesses, and peripheral bus activities, regardless of whether the key is real or scrap. This invention eliminates the risk of private key leakage caused by cloud-based state management through stateless signatures and completely eliminates distinguishable side-channel fingerprints across the entire link through physical-level execution isomorphism, achieving system-level quantum-resistant security in high-concurrency scenarios.

This invention relates to the field of flexible sensing fibers, disclosing an elastomer thermally stretched neural probe with sacrificial layer constraint to suppress necking fracture, its preparation method, and its application. The method includes: hot-pressing an elastomer material with a sacrificial layer to form a preform; then hot-stretching it in a low-temperature polymer drawing tower while simultaneously feeding in conductive wires to obtain thermally stretched fibers; finally, removing the sacrificial layer to obtain the elastomer thermally stretched neural probe. This invention introduces a high-viscosity, high-storage-modulus sacrificial layer outside the core layer to form a hierarchical constraint-type microarchitecture preform with pre-formed channels. During the hot-stretching process, the sacrificial layer, as the main load-bearing component, bears most of the axial traction stress and uniformly transfers the deformation stress to the viscous core layer through interfacial mechanical coupling. This stress transfer mechanism effectively protects the fragile core layer, allowing it to thin synchronously with the outer shell without fracture, thereby achieving precise molding of refined conductive units.

Aspects disclosed in the detailed description include a processing unit for dynamically reconfiguring micro-architectural features of the processing unit in response to a workload being processed on the processing unit and a processing unit control unit configured to receive a plurality of signals from the processing unit. The plurality of signals are indicia of the workload being processed on the processing unit. In response, the processing unit control unit determines whether performance, power consumption, or both, of the processing unit may be improved by modifying a micro-architectural feature. In response to determining that performance or power consumption of the processing unit may be improved by modifying micro-architectural features, the processing unit control unit triggers the processing unit to modify one or more of its micro-architectural features. The processing unit, in response to being triggered by the processing unit control unit, modifies one or more of its micro-architectural features.

A processor core is accessed. The core is configured to execute instructions associated with an instruction set architecture (ISA). The core comprises a plurality of compute slices, a plurality of barrier register files, and a control unit. Each compute slice includes at least one arithmetic logic unit (ALU), a local register file, and is coupled to a successor compute slice and a predecessor compute slice by a barrier register file. Code associated with the ISA is evaluated, where the code includes a first loop. The evaluating includes generating iteration transfer information associated with the first loop. Each slice task within a plurality of slice tasks associated with the first loop is distributed to a compute slice. The processor core executes the plurality of slice tasks. Data forwarding between successive compute slices is based on the plurality of barrier register files and the iteration transfer information.

The embodiments of the present disclosure relate to a parameter adjustment method, a parameter adjustment apparatus, an electronic device, and a computer program product. The method comprises: during the process of a chip executing a service, reading at least one target parameter of the chip, wherein the at least one target parameter includes one or more of the following: a microarchitecture parameter, or a system-on-chip parameter. The method further comprises: acquiring at least one target service performance metric of the service. The method further comprises: during the process of the chip executing the service, adjusting the at least one target parameter on the basis of the at least one target service performance metric. In this way, during the process of a chip executing a service, a microarchitecture parameter and / or a system-on-chip parameter of the chip can be dynamically adjusted on the basis of a target service performance metric of the service, so that the adjusted microarchitecture parameter and / or system-on-chip parameter can help improve the target service performance metric. Thus, the performance of the service can be improved as the chip operates.

This application relates to the field of computer technology, providing a CPU microarchitecture performance evaluation method, a bare-metal performance evaluation tool, an electronic device, and a computer program product. The method, applied to the bare-metal performance evaluation tool, includes: configuring at least one event to be monitored and target test code based on the performance evaluation requirements of the CPU microarchitecture to be evaluated; controlling a virtual CPU to execute the target test code and collecting event execution data corresponding to all events to be monitored during code execution; the virtual CPU being created based on the CPU microarchitecture to be evaluated; and determining the performance evaluation information of the CPU microarchitecture based on the event execution data. This solution fills the gap in the lack of CPU microarchitecture performance evaluation methods in the pre-silicon stage, enabling the evaluation of CPU microarchitecture performance without the need for tape-out.

This invention discloses a distributed cloud-native computing task scheduling method integrating intelligent operation and maintenance, relating to the field of cloud computing technology. The method includes: collecting historical load data from online tasks and calculating the load prediction variance characterizing fluctuation risk; using kernel probes to extract micro-architectural features characterizing resource contention sensitivity in real time; calculating a hardware isolation budget index based on the product coupling relationship between the prediction variance and the micro-architectural features using a nonlinear mapping function; generating a restrictive three-level cache bitmask based on this index and writing it into the resource control group configuration of offline tasks to physically compress their usable cache paths. This invention transforms statistical prediction variance into the physical isolation boundary of the underlying hardware, achieving rigid redemption and dynamic adjustment of hybrid deployment resources while ensuring the performance stability of online tasks.

Disclosed are circuits for dynamically configuring configurable micro-architectural circuits based on associated operating point indicators.

This invention discloses an Aware+Fuzz method for enhancing processor data prefetch security to mitigate cache side-channel attacks, belonging to the field of processor chip microarchitecture design. This method includes an attack awareness module and an observation obfuscation module. During program execution, the attack awareness module dynamically detects key load instructions that may belong to the first stage of a cache side-channel attack and activates the observation obfuscation module. In subsequent program execution, the observation obfuscation module dynamically detects key load instructions that may belong to the third stage of the attack, records and learns the memory addresses probed by the attacker, triggers corresponding prefetching, and obfuscates the attacker's memory observations. The prefetched data disrupts the attacker's judgment of the victim program's memory usage, thereby significantly reducing the attacker's success rate and improving the security performance of the processor system.

This invention discloses a method for defending against cached covert communication on an ARM platform based on noise loading injection. Due to the expanding attack surface of TEEs and the vulnerabilities of TrustZone technology in microarchitectural isolation, cached covert communication has become possible. This invention adds a defense mechanism against cached covert communication based on TrustZone technology, designing a cached covert communication defense architecture based on noise loading injection. Based on this architecture, a dynamic monitoring mechanism, a strategy optimization mechanism, and a noise injection mechanism are proposed. The dynamic monitoring mechanism monitors system security and system performance. The strategy optimization mechanism generates the optimal noise injection strategy and calculates the noise injection frequency and intensity in real time. The noise injection mechanism loads data to resist cached covert communication. This defense method improves the security of the original architecture and achieves low performance overhead, balancing system security and performance.

This application relates to the field of computer technology and discloses a resource optimization and scheduling device for a distributed computer system, including a signal acquisition module, a feature calculation module, a resource control module, and a task scheduling module. The signal acquisition module reads memory bandwidth consumption data and generates a digital signal sequence; the feature calculation module converts the sequence into a frequency domain signal and calculates a high-frequency energy ratio index; the resource control module performs static configuration and dynamic gating based on this index, adjusting the number of cache paths and bandwidth threshold in the static logic, and triggering a hardware time-division gating mechanism when the bus is saturated to generate a pulse-width modulation signal to switch the high-bandwidth priority of the task; the task scheduling module calculates an orthogonal cost score based on the frequency domain features to select deployment nodes. This invention effectively identifies memory access patterns and avoids bus conflicts through frequency domain analysis and hardware time-division gating, solving the resource contention problem at the microarchitecture level.

The present disclosure provides a microcode splitting method and device of RVV instructions, electronic equipment and storage medium, by further introducing a sub-MOP splitting mechanism on the basis of ordinary MOP splitting, a single MOP corresponding to a special vector instruction is further split into multiple sequentially executed sub-MOPs, so that the execution unit can gradually complete the target operation by using the intermediate results generated by the previous sub-MOP, thereby realizing the execution of the special vector instruction without greatly modifying the existing execution unit structure. Thus, the hardware modification cost can be effectively reduced, the reuse degree of the existing vector microarchitecture can be improved, the register port pressure can be reduced, and the compatibility and engineering implementation feasibility of the processor for special RISC-V vector instructions can be improved.

The application relates to the technical field of processor verification, and provides a RISC-V branch predictor closed-loop verification method and system, which comprises the following steps: providing a plurality of test modes facing a branch predictor micro-architecture, each test mode corresponds to a branch behavior feature and has a parameterized configuration; receiving a random seed, selecting a target test mode from the plurality of test modes based on the random seed, and determining parameters for the target test mode; generating a corresponding RISC-V assembly test program according to the target test mode and the parameters, so as to perform closed-loop verification on the RISC-V branch predictor. Through the parameterized test mode facing the micro-architecture and the random seed driving mechanism, efficient closed-loop verification is realized, the problem that test excitation randomness is too high or simulation time is too long in the prior art is solved, and the verification efficiency is effectively improved.

A system and method for autonomous machine identity succession utilize a hardware-rooted semantic sentinel and an analog neuromorphic audit engine to ensure state integrity. The system detects micro-architectural threat signatures through continuous asynchronous voltage monitoring and gates cryptographic signatures via a low-impedance analog interlock circuit physically interposed on a processor signature-enable line. Behavioral integrity is verified through an adversarial “Proof of Logical Alignment” handshake, where proposed action vectors are audited via an analog memristor crossbar array utilizing physical current summation replicated through a high-impedance Wilson Current Mirror isolation barrier. The invention ensures the atomic migration of identities across heterogeneous hardware architectures through a “Handshake-and-Zeroize” protocol, utilizing a series-pass isolation switch and crowbar MOSFET circuit to provide irreversible thermodynamic destruction of the source state.

The application discloses a data resource contention risk prediction and optimization method based on LSTM and attention mechanism, and particularly relates to the technical field of computing resource management. First, the multi-dimensional performance index sequence of a cloud data center is collected, and the shared resource affinity of fusion time decay and resource access frequency is calculated as an auxiliary feature to construct an enhanced input for training an LSTM network. The attention mechanism fused with a contention diffusion speed factor is used to dynamically weight the key time slices and quantify the risk driving. The resource contribution mapping of the introduction of the causal test is used to determine the dominant contention resource, and the precise adaptive optimization action, such as virtual machine migration or path partition adjustment, is triggered accordingly, thereby improving the accuracy and interpretability of the resource contention risk prediction, realizing the closed-loop linkage from prediction to optimization, and solving the problems of difficult performance degradation prediction, inaccurate root location and low optimization efficiency caused by the implicit contention of micro-architecture level resources in the cloud data center.

The aspects disclosed in the specific embodiments include: a processing unit for dynamically reconfiguring the microarchitectural features of a processing unit in response to a workload processed on the processing unit; and a processing unit control unit configured to receive a plurality of signals from the processing unit. The plurality of signals are markers of the workload processed on the processing unit. In response, the processing unit control unit determines whether the performance, power consumption, or both of the processing unit can be improved by modifying the microarchitectural features. In response to determining that the performance or power consumption of the processing unit can be improved by modifying the microarchitectural features, the processing unit control unit triggers the processing unit to modify one or more of its microarchitectural features. The processing unit modifies one or more of its microarchitectural features in response to being triggered by the processing unit control unit.

The application relates to a micro-architecture design space exploration method and device, computer equipment, a storage medium and a computer program product, and relates to the technical field of Internet. The method comprises the following steps: obtaining design parameters in a micro-architecture design space of a target microprocessor; inputting the design parameters into a first model corresponding to each configuration dimension to obtain initial configuration parameters of the target microprocessor under each configuration dimension; inputting each initial configuration parameter into a task attention model to output corresponding parameter weights; fusing each parameter weight and each initial configuration parameter to obtain a correlation feature vector; and predicting target configuration parameters of the target microprocessor under each configuration dimension according to the correlation feature vector. The method can improve the accuracy of micro-architecture design space configuration prediction.

This specification discloses an instruction decoding module and its generation method, apparatus, and chip architecture simulator. The method for generating the instruction decoding module provides a way to generate the module based on a two-level decoding table using a computing device. This reduces the manpower required and resource consumption during the development of microarchitecture hardware, thereby improving the development efficiency. Specifically, the method first determines the grouped feature codes corresponding to each code position in the instruction encoding from the instruction feature set. Then, it groups the instruction encodings in the two-level decoding table according to the grouped feature codes to obtain an encoding search tree. Finally, the instruction decoding module is generated based on this encoding search tree. The entire generation process is simple and improves the generation efficiency of the instruction decoding module.

This invention provides a hierarchical power management system and its voltage sag suppression method, relating to the fields of power management and microarchitecture control technology. It includes at least one application processor core, a system control processor (SCP), and a power management interface. The application processor core integrates a digital voltage sag detector (DDD), power transfer protection (PDP) logic, and an extended activity monitoring unit (AMU); the AMU is configured to monitor the activation state of the PDP logic. The SCP periodically reads the AMU's count data, calculates the PDP intervention rate, and dynamically adjusts the processor core's supply voltage or the DDD trigger threshold based on this intervention rate, forming a closed-loop control. This invention enables cross-level linkage between core internal hardware protection and system-level power management, effectively suppressing performance loss caused by dynamic voltage sags and improving energy efficiency and system reliability.

The application discloses a micro-architecture design space exploration method based on Gaussian mixture regression, adopts a Bayesian optimizer to realize incomplete supervised learning, can reduce the labeling cost of a data set, and accelerates the training of a model by utilizing prior probability, adopts a Gaussian mixture regression model as a proxy model, can simultaneously calculate the predicted mean of a target value and the covariance between multiple targets, compared with other models, can better perform multiple target optimization, uses a Bayesian information optimization criterion to determine the final number of Gaussian components, realizes the function of dynamically optimizing the number of Gaussian components, and makes the model better approximate a real function, collects a function CEIPV in combination with the target value, considers the balance problem between targets while providing the observation points with the highest uncertainty, and realizes the operation of selecting an optimal micro-architecture outside the data set by a conjugate gradient method.

The application discloses a design space exploration method, system and computer program product for micro-architecture. The method comprises: inputting a set of micro-architecture parameters of a target hardware, a value range of the parameters and a plurality of preset condition regions into a trained design point generation model, wherein the condition regions are preference regions divided from a predefined target space; generating a plurality of design points for each preset condition region according to the micro-architecture parameters and the value range thereof by using the trained design point generation model in a sequential decision manner, wherein a design point comprises all parameters and a set of values thereof; combining all generated design points, and performing a Pareto dominance relationship comparison to screen out a non-dominated solution set to form a Pareto front approximation. The application can quickly generate a high-quality, reasonable and interpretable Pareto front.

The application provides a node task migration and scheduling system based on digital twinning, relates to the technical field of computer system structure and data processing, and quantifies the computing resource interference in the multi-tenant shared environment by sensing the cross-tenant noise coefficient and state synchronization complexity entropy in the node micro-architecture; extracts the spatial discrete variance of the mobile terminal trajectory feature to generate an adaptive migration decision hysteresis factor, which is converted into a decision damping to suppress the invalid high-frequency reciprocating migration; a digital twinning sandbox is constructed before physical cutting, a composite fault operator is injected into the bottom layer by a chaotic scene injection engine, and a fidelity integrator is used to calculate the risk-adjusted service continuity retention degree; finally, the bottom layer controller is executed by the safe baseline comparison linkage to perform physical flow cutting. The application completes network boundary deduction without consuming physical bandwidth, avoids the interruption risk caused by state hard switching, and effectively guarantees the smooth transition of stateful services.

A hardware-accelerated micro-architecture for encryption systems such as but not limited to McEliece that do not rely on substitution-permutation networks. The invention comprises dedicated hardware blocks for linear transformations (including matrix multiply and accumulate), arithmetic and logic operations, and data obfuscation through scrambling and permutation, all coordinated by a central sequencer. Input data is selectively routed through configurable data paths to undergo a sequence of matrix operations, such as multiplication with dynamically generated or stored matrix keys, to produce encrypted output. The micro-architecture is highly adaptable and may be deployed as integrated cores within any conventional processor (including GPUs, NPUs, CPUs, and DSPs), as standalone accelerators in FPGAs or ASICs, or as chiplets in multi-chip modules and chip-stacking configurations. By leveraging existing matrix operation hardware originally designed for graphics or AI, or through custom silicon, the invention delivers high-performance, energy-efficient McEliece encryption and decryption without the latency and overhead of substitution-permutation ciphers. The system supports both symmetric and asymmetric modes of McEliece, key encapsulation, authorization, and authentication, with dynamically configurable parameters for enhanced security. This approach enables efficient, scalable, and future-proof cryptographic acceleration tailored for matrix-based non-SPN encryption, particularly the McEliece framework, across communication, storage, and computing platforms.

Embodiments of the present disclosure relate to a method of adjusting parameters, an apparatus of adjusting parameters, an electronic device, and a computer program product. The method comprises reading at least one target parameter of a chip during execution of a service by the chip. The at least one target parameter comprises one or more of: a micro-architecture parameter, or a system-on-chip parameter. The method further comprises obtaining at least one target service performance indicator of the service. The method further comprises adjusting the at least one target parameter during execution of the service by the chip according to the at least one target service performance indicator. In this way, the micro-architecture parameter and / or the system-on-chip parameter of the chip can be dynamically adjusted according to the target service performance indicator of the service during execution of the service by the chip, so that the adjusted micro-architecture parameter and / or the system-on-chip parameter can help to improve the target service performance indicator. Therefore, the performance of the service can be improved along with the running process of the chip.