196 results about "Arithmetic logic unit" patented technology

An apparatus is provided that includes a network interface to transmit and receive data packets over a network; a memory including one or more buffers; an arithmetic logic unit to perform arithmetic operations for organizing and combining the data packets; and a circuitry to receive, via the network interface, data packets from the network; aggregate, via the arithmetic logic unit, the received data packets in the one or more buffers at a network rate; and transmit, via the network interface, the aggregated data packets to one or more compute nodes in the network, thereby optimizing latency incurred in combining the received data packets and transmitting the aggregated data packets, and hence accelerating a bulk data allreduce operation. One embodiment provides a system and method for performing the allreduce operation. During operation, the system performs the allreduce operation by pacing network operations for enhancing performance of the allreduce operation.

Provided are an apparatus and method for accelerating computation, and a chip. The apparatus for accelerating computation comprises: an instruction decoding module, a bit width selection module, a small bit width processing module, and a large bit width processing module. The instruction decoding module is configured to decode an inputted instruction, determine the bit width of the instruction on the basis of a decoding result, generate a control signal comprising bit width information of the instruction, and send the control signal to the bit width selection module. The bit width selection module is configured to forward the control signal to the small bit width processing module when the bit width of the instruction is a small bit width, and forward the control signal to the large bit width processing module when the bit width of the instruction is a large bit width. The small bit width processing module is configured to process the instruction by using a register file having a small bit width and a corresponding arithmetic logic unit. The large bit width processing module is configured to process the instruction by using a register file having a large bit width and a corresponding arithmetic logic unit.

The invention discloses a storage and calculation integrated server optimization method based on an NPU, relates to the technical field of server architecture, and discloses the storage and calculation integrated server optimization method based on the NPU by dynamically adjusting the configuration of an arithmetic logic unit, a multiplication and accumulation calculation unit and a cache module to generate a reconstruction calculation unit. By combining heterogeneous hardware performance evaluation and a task migration mechanism, dynamic optimal configuration and load balancing of computing resources are realized, the task execution efficiency can be improved, and the heterogeneous hardware collaborative energy efficiency ratio can be optimized.

The invention provides an arithmetic logic unit of a processor and a floating-point number calculation method, and belongs to the technical field of floating-point numbers. The arithmetic logic unit comprises a format conversion module and a mixed precision multiplier-adder, the format conversion module performs format conversion on a high-precision floating-point number to obtain a low-precision floating-point number, and retains an index lost in the conversion process as index auxiliary information, and when the mixed precision multiplier-adder performs multiply-add operation on the low-precision floating-point number, the mixed precision multiplier-adder performs multiply-add operation on the low-precision floating-point number. And the index auxiliary information is used for compensating the lost index, so that the precision loss of the floating-point number can be reduced when the mixed precision multiplier-adder is used.

The invention provides an arithmetic logic unit parallel processing system and method and electronic equipment, and relates to the field of chip architecture processing, and the arithmetic logic unit parallel processing system comprises an instruction transmitting unit, a write-back unit and a plurality of ALU groups containing a plurality of arithmetic logic units; wherein the instruction transmitting unit is respectively connected with the input end of each ALU group; the output end of each ALU group is connected with the write-back unit; the input end of each ALU group is respectively connected with the input ends of all the arithmetic logic units in the current ALU group; the output end of each ALU group is respectively connected with the output ends of all the arithmetic logic units in the current ALU group; according to the scheme, the reduction instruction and the vector arithmetic logic operation can be realized by using the same arithmetic logic operation component, the number and the area of the vector arithmetic logic operation component are reduced, and the utilization rate of the vector arithmetic logic operation component is improved.

A memory device includes a plurality of memory banks, and a processing-in-memory (PIM) block accessible to the plurality of memory banks, wherein the PIM block comprises a control circuit configured to receive a plurality of operation instructions from a host and, in response to a predicated instruction indicating a predication operation among the plurality of operation instructions, instruct an arithmetic logic unit (ALU) to perform the predication operation, a predicate register file (PRF) configured to store therein a predicate value determined by the predication operation, and the ALU configured to perform an operation according to a command signal translated by the control circuit based on the predicate value from an operation instruction that depends on the predicate value among the plurality of operation instructions.

According to an embodiment of the present disclosure, a processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading data to be processed. The target operand specifies a target storage location in the memory for writing a processing result. The processor also includes an arithmetic logic unit coupled to the instruction decoder and the memory. The arithmetic logic unit is configured to: read data to be processed from a source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write the processing result to a target storage location in the memory. In this way, the efficiency of vector calculations can be improved.

An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

The invention discloses a constant data loading method, a graphics processor and a medium. The constant data loading method comprises the following steps: storing data of at least part of data units in a constant cache into a target storage space; the target storage space comprises at least one vector register; acquiring a data access instruction, wherein the data access instruction is used for accessing target data in the constant cache; if it is detected that the target data is stored in a target storage space, compiling the data access instruction into an arithmetic logic unit instruction; the arithmetic logic unit instruction indicates the position of the target data in the target storage space. By adopting the scheme, the operation efficiency of the shader can be improved.

The invention discloses a tensor convolution calculation method and device, equipment, a storage medium and a program product, and relates to the technical field of application computers, and the method comprises the steps: obtaining to-be-transmitted tensor information of a source arithmetic logic unit, and constructing transmission data according to at least two tensor elements in the tensor information; transmitting the tensor element to the destination arithmetic logic unit based on the transmission; and performing convolution operation on the tensor elements in the target arithmetic logic unit. According to the embodiment of the invention, by adopting a mode of splicing the tensor elements, any additional data transmission device does not need to be additionally arranged between the arithmetic logic units, the optimization of transmission data is realized, and by reducing the transmission quantity of the tensor elements, the problem of transmission blockage is relieved, the utilization rate of transmission bandwidth is improved, and the transmission efficiency is improved. According to the method, different types of input data can be processed, the universality of convolution calculation is enhanced, convolution calculation of tensor elements is carried out based on the spliced transmission data, the convolution calculation speed is increased, and the calculation performance is improved.

According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input / output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.SPL

A processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand, and a target operand. The target opcode indicates a vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading to-be-processed data. The target operand specifies a target storage location in the memory for writing a processed result. The processor further includes an arithmetic logic unit configured to: read the to-be-processed data from the source storage location of the memory; perform, on the to-be-processed data, an arithmetic logic operation associated with the vector operation specified by the target instruction; and write the processed result to the target storage location of the memory.

The invention provides a precision target optimization method and system adaptive to a variable precision arithmetic logic unit, a medium, a terminal and a program product. The method comprises the following steps: acquiring an output feature set of each group of an upper layer; the precision generation network layer generates a corresponding precision target according to the output feature set, and the ALU calculation layer generates a prediction result according to the generated precision target; the teacher model generates a reference target and a real label according to the output feature set; constructing a total loss function according to the calculated task loss, precision generation loss and adversarial loss; performing back propagation optimization on the student model based on the constructed total loss function; repeatedly and iteratively training the student model until convergence to obtain a final student model; and deploying the final student model to generate an optimal precision target corresponding to each group. According to the method provided by the invention, the fine precision adjustment of the bit granularity can be realized, the adaptive ability of the model is enhanced, and the matching degree of the precision and the task demand is improved.

To provide native hardware support for complex operations such as a beam search operation, an integrated circuit device can be implemented with multiple computational circuit blocks coupled in series to form a pipeline. Each computational circuit block includes an arithmetic logic unit (ALU) circuit having a first numeric input, a second numeric input, a primary result output, and a secondary output. The ALU circuit is programmable to perform an arithmetic operation on the first numeric input and the second numeric input to generate the primary result output, and provide one of the first numeric input or the second numeric input to the secondary output, which is fed back to the ALU circuit.

A memory device includes a first scalar register file storing a first input fragment, a second scalar register file storing a second input fragment, an arithmetic logic unit (ALU), and a control circuit. The control circuit is configured to perform, using the ALU, a first operation between the first input fragment and a first weight fragment based on a first operation command received from a host, and to perform, using the ALU, a second operation between the second input fragment and a second weight fragment based on a second operation command received from the host.

The invention belongs to the technical field of processor architecture design, and particularly discloses a 3D stacked and interconnected processor, system and device. According to the method, the computing logic, the interconnection logic and the storage logic on the single processor are decoupled and split to different chips, and larger data bit width can be provided by adding storage control logic and routing nodes on the interconnection chips, so that higher on-chip interconnection bandwidth is provided. In addition, more computing units can be arranged according to the saved internal area and winding resources of the computing chip, so that the computing power of the processor is improved; moreover, a storage control logic unit and an arithmetic logic unit can be arranged in the interconnection chip, so that the transmission frequency of data between the computing chip and the storage chip is reduced, and the bandwidth utilization rate of the processor is improved.

Techniques and architecture are described for a method that includes an in network compute (INC) manager receiving from switches of a fat tree configured network, arithmetic logic unit (ALU) capacity of the switches. Based at least in part on the ALU capacity of the switches and bandwidth, the INC manager determines one or more switches within each tier that are capable of supporting the processing units and based at least in part on the determining, the INC manager selects a first switch as a root, wherein the first switch is included within a tier of switches having intermediate tiers of switches located between the tier and the plurality of processing units within the fat tree configured network. The INC manager creates one or more paths of switches within each of the intermediate tiers from the root to the plurality of processing units to provide a constrained disjoint spanning tree of switches.

The invention discloses a data processing method, a processor and electronic equipment, and relates to the technical field of data processing. The method is applied to a processor, the processor comprises an arithmetic logic unit used for supporting basic polynomial fusion operation, and the basic polynomial fusion operation comprises polynomial multiplication and polynomial addition operation at the same time; the data processing method comprises the following steps: in response to a plurality of received input parameters to be subjected to polynomial fusion operation, generating an instruction sequence which corresponds to the input parameters and is used for completing the polynomial fusion operation on the basis of a basic fusion instruction set matched with an arithmetic logic unit; the basic fusion instruction set comprises a plurality of basic polynomial fusion operation instructions used for controlling the arithmetic logic unit to execute corresponding basic polynomial fusion operation, and the instruction sequence comprises at least one basic polynomial fusion operation instruction in the basic fusion instruction set; and running the instruction sequence to obtain a running result.

In an example, a processor for machine learning calculations is described. An adapter input circuit is operable to receive an input tensor. The adapter input circuit includes channels. A first channel of the channels is operable to process samples of the input tensor to generate pre-processed samples and to obtain locations of the samples. A location processor, coupled to the first channel, is operable to determine output locations in response to the locations. An arithmetic logic unit (ALU), coupled to the channels, is operable to calculate output samples from the pre-processed samples. An adapter output circuit, coupled to the location processor and the ALU, operable to process the output locations and the output samples to generate an output tensor.

The present invention relates to an apparatus and method for configuring a warp in a vector operation system. The apparatus includes: general-purpose registers; an arithmetic logic unit; a warp instruction scheduler; and a plurality of warp resource registers. The warp instruction scheduler allows each of a plurality of warps to include a part of relatively independent instructions in the program core according to the warp allocation instruction in the program core, and allows each of the plurality of warps to access all or specified local data in the general-purpose registers through the arithmetic logic unit according to the configuration during software execution, and completes the operations of each of the above warps through the arithmetic logic unit. The present invention can more widely adapt to different applications, such as big data, artificial intelligence operations, etc., through the above-described components that can allow software to dynamically adjust and configure general-purpose registers for different warps.

A graphics processing unit (GPU) for clustering of machine learning (ML) functional components, including: a plurality of compute units; a plurality of ML clusters, wherein each of the ML clusters comprises at least one arithmetic logic unit (ALU), and wherein each of the ML clusters is associated with a respective subset of the compute units; and a plurality of memory modules each positioned on the GPU adjacent to a respective ML cluster of the plurality of ML clusters, wherein each ML cluster is configured to directly access one or more adjacent memory modules.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes: parsing sequential FHE logic gate code; transforming the FHE logic gate code into a set of code modules, each code module in the set of code modules having an input and an output that is a function of the input and not passing control to other functions; creating node wrappers around each code module; configuring at least one of the main processing cores to implement an equivalent logic element of each element in a streaming mode of operation, wherein a data stream flowing out of a corresponding arithmetic logic unit flows into main memory and into other arithmetic logic units among a plurality of arithmetic logic units.

The embodiment of the invention discloses a computing chip, a computing method, a computing device, a storage medium and a program product. The computing chip comprises a computing core, the computing core comprises an arithmetic logic unit, the arithmetic logic unit comprises a first storage unit and a computing unit, and data circulation exists between the computing unit and the first storage unit in the fusion computing process. According to the technical scheme, the fusion calculation efficiency can be improved.

This invention belongs to the field of computer technology and relates to an angle calculation system based on CORDIC instructions. The system includes an IFU (Instruction Fetch Unit) and an EXU (Execution Unit). During the instruction fetch phase, the IFU reads CORDIC instructions from the instruction memory according to the address of the PC. The EXU includes a decoding module, an arithmetic logic unit, a load-memory unit, and a write-back unit. This invention extends the CORDIC angle calculation instruction set based on the RISC-V architecture and designs a complete pipelined hardware structure, supporting trigonometric function operations. It has a complete CORDIC operation path hardware circuit structure, reusing the same operation path for different operation processes, improving hardware resource utilization. It overcomes the limitation of convergence of the calculation result range when performing angle calculation based on the CORDIC algorithm by pre-storing special angle results to reduce calculation time and optimize the circuit operating frequency.

This invention presents a computer processing system and method designed to execute cryptographic operations while providing selective protection against side-channel attacks. It comprises a configuration of unprotected and protected hardware modules, the latter of which is equipped with data isolators, and a protected arithmetic logic unit (ALU) for secure data processing. The system enhances cryptographic security by selectively transmitting and computing input shares to generate side-channel protected output shares, ensuring robust protection during cryptographic operations.

The invention discloses a memory device and an operation method performed by the same. The memory device includes: a first scalar register file storing a first input segment; a second scalar register file storing a second input segment; an arithmetic logic unit (ALU); and a control circuit. The control circuit is configured to perform a first operation between the first input segment and the first weight segment using the ALU based on a first operation command received from the host, and perform a second operation between the second input segment and the second weight segment using the ALU based on a second operation command received from the host.

The present disclosure relates to digital signal processing blocks. A digital signal processor (DSP) chip is disclosed. The DSP chip includes an input stage for receiving a plurality of input signals; a pre-adder coupled to the input stage and configured to perform one or more operations on one or more of the plurality of input signals; and a multiplier coupled to the input stage and the pre-adder and configured to perform one or more multiplication operations on one or more of the plurality of input signals or an output of the pre-adder. The DSP chip also includes an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier. The ALU is configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, an output of the pre-adder, or an output of the multiplier. The DSP chip also includes an output stage coupled to the ALU, the output stage configured to generate one or more output signals based at least in part on one or more outputs of the ALU or at least one of the plurality of input signals.

The invention relates to a multi-thread dynamic task scheduling circuit, a computing chip and a computing system, which are integrated in a parallel computing chip, and comprise a plurality of thread management units which are respectively used for storing context information of each task thread, reading an instruction stream from a memory through an internal instruction reading and transmitting unit, and decoding and transmitting the instruction stream; the arithmetic logic unit is used for executing arithmetic and logic operation instructions of the thread management unit so as to realize dynamic parameter derivation during operation; the task distribution unit is used for arbitrating the task configuration information transmitted by the plurality of thread management units and distributing the task configuration information to each processing unit in the chip; and the synchronization unit is used for synchronizing primitives through hardware so as to realize synchronization among the plurality of thread management units and synchronization between the thread management units and the processing unit. Each thread is programmable and adapts to complex scenes such as dynamic image sizes and dynamic calculation processes.

The invention discloses a memory device, an operating method thereof, and an in-memory processing device. The memory device includes an in-memory processing (PIM) block configured to perform an operation between a weight value and an input value, the weight value being represented by a weight scaling factor and a weight element, the input value being represented by an input scaling factor and an input element, where the PIM block includes: a first scaling register file storing the input scaling factor; a second scaling register file storing a weight scaling factor; a scalar register file (SRF) storing input elements; a plurality of arithmetic logic units (ALU) configured to perform a first operation between the input scaling factor and the weight scaling factor and a second operation between the input element and the weight element in parallel in response to an operation command received from a host; and an accumulator configured to accumulate and store operation results of the first operation and the second operation.