10 results about "Read-modify-write" patented technology

A memory device includes a memory cell array including normal cell blocks and at least one error correction code (ECC) cell block, which include a plurality of rows; a scrub control circuit configured to perform an error check operation on each of the plurality of rows; and a write-back prevention circuit configured to store, based on local error signals for the normal cell blocks and the at least one ECC cell block during the error check operation, a severe address for a row in which a severe error occurs, and selectively perform a write-back operation on the row corresponding to the stored severe address during the error check operation or a read-modify-write (RMW) operation.

An apparatus comprises decoding circuitry configured to decode instructions; and processing circuitry configured to perform data processing operations in response to the instructions decoded by the decoding circuitry. In response to a shared memory update task offloading instruction, the decoding circuitry is configured to control offloading, to extension processing circuitry, of a shared memory update task to be performed by the extension processing circuitry asynchronously with respect to other data processing operations performed by the processing circuitry, the shared memory update task comprising at least one atomic read-modify- write update to shared memory data.

A bitfield compare-and-update instruction separates compare and exchange operations on the same lock state variable. When executing the bitfield compare and update instruction, the processing system compares a portion of the lock state variable to a previously-loaded value and, in response to a match, updates a different portion of the lock state variable.

Apparatuses, systems, and methods for shared codeword in two-pass access operations. The memory may use a read read modify write write (RRMWW) cycle to write data and metadata to the array. Metadata and a data codeword are read out as part of two read access passes and combined into a shared codeword. Error correction is performed on the shared codeword, and then the corrected shared codeword is modified with write data and metadata. Updated parity is generated based on the modified shared codeword and the modified data and updated parity and the metadata are written as two write access passes.

Methods, apparatus, systems, and articles of manufacture are described for facilitating fully pipelined read-modify-write support in level one data caches using storage queues and data forwarding. An example apparatus includes a first storage region (214), a second storage region (218), a storage queue (212, 216) coupled to the first storage region (214) and the second storage region (218), the storage queue (212, 216) usable to receive a first memory operation specifying a first set of data, process the first memory operation to store the first set of data in at least one of the first storage region (214) and the second storage region (218), receive a second memory operation, and feed back the first set of data for the second memory operation prior to storing the first set of data in the at least one of the first storage region (214) and the second storage region (218).

The invention relates to a memory device and an operating method thereof. A memory device includes: a memory cell array including a normal cell block and at least one error correction code (ECC) cell block, the normal cell block and the at least one error correction code (ECC) cell block including a plurality of rows; a cleaning control circuit configured to perform an error checking operation on each of the plurality of rows; and a write back prevention circuit configured to store a serious address of a row where a serious error occurs based on local error signals of the normal cell block and the at least one ECC cell block during the error check operation; and selectively performing a write-back operation on a row corresponding to the stored severe address during an error check operation or a read-modify-write (RMW) operation.

An internal error-checking circuit includes a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit, and an error correction circuit. The clock generation circuit generates and outputs a self-refresh clock signal in response to a self-refresh enable signal; the internal command generation circuit counts the self-refresh clock signals when the error-checking enable signal indicates that an internal error-checking function is enabled and generates and outputs one internal error-checking command signal when the count value of the self-refresh clock signal is a first preset value; the address generation circuit counts the internal error-checking command signal to generate and output an internal error-checking address; the control logic circuit controls, in response to the internal error-checking command signal, the error correction circuit to sequentially execute a single internal read-modify-write operation on the target memory cells corresponding to the internal error-checking address in memory arrays.

A system is provided that includes a compression engine, a metadata processor, and a memory having a burst length. The compression engine compresses source data according to a compression ratio to form compressed data. The metadata processor processes the compressed data to form metadata having a size that is smaller than the burst length. The metadata processor generates autofill data responsive to the compression ratio and concatenates the autofill data with the metadata to form a metadata burst having a same size as the burst length. A memory controller may then write the metadata burst to the memory without triggering a read-modify-write operation.

Apparatuses, systems, and methods for shared codeword in two-pass access operations. The memory may use a read read modify write write (RRMWW) cycle to write data and metadata to the array. Metadata and a data codeword are read out as part of two read access passes and combined into a shared codeword. Error correction is performed on the shared codeword, and then the corrected shared codeword is modified with write data and metadata. Updated parity is generated based on the modified shared codeword and the modified data and updated parity and the metadata are written as two write access passes.

The invention relates to a method and apparatus for facilitating pipelined read-modify-write support in a cache. Methods, apparatus, systems, and articles of manufacture are described for facilitating fully pipelined read-modify-write support in a level 1 data cache using storage queues and data forwarding. An example apparatus includes a first storage area (214), a second storage area (218), a storage queue (212, 216) coupled to the first storage area (214) and the second storage area (218), the storage queue (212, 216) being operable to receive a first memory operation specifying a first set of data, processing the first memory operation to store the first set of data in at least one of the first storage area (214) and the second storage area (218), receiving a second memory operation, and storing the first set of data in the at least one of the first storage area (214) and the second storage area (218) before storing the first set of data in the at least one of the first storage area (214) and the second storage area (218). The first set of data is fed back for the second memory operation.