28 results about "Semaphore" patented technology

Apparatuses, systems, and techniques to facilitate graph code synchronization between application programming interfaces. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause graph code to wait on a semaphore used by another API.

Apparatuses, systems, and techniques to facilitate graph code synchronization between application programming interfaces. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause graph code to wait on a semaphore used by another API.

Apparatuses, systems, and techniques to perform an application programming interface (API) to add one or more graph nodes to a software graph, wherein the API is to cause a semaphore wait node to be added to a software graph based, at least in part, on a dependency type indicated by the API. In at least one embodiment, one or more nodes are added to a graph in accordance to one or more dependency types.

The invention provides a data processing method and device, electronic equipment and a storage medium. The method comprises the following steps: initializing a first semaphore and a second semaphore; calling a calculation thread to calculate the ith data block to obtain an ith calculation result; updating the value of the first semaphore to i; calling the first communication thread to load the (i + 1) th data block in the process of calling the calculation thread to calculate the ith data block, and acquiring (i-1) th network data; under the condition that the first communication thread obtains the (i-1) th network data, the second semaphore is updated to be i-1; when the first semaphore is greater than or equal to i and the second semaphore is greater than or equal to i-1, accumulating the ith calculation result and the (i-1) th network data to obtain ith accumulated data; and sending the ith accumulated data to the next computing node. According to the invention, the data calculation performance can be improved and the communication delay can be reduced.

The application discloses an AT instruction analysis method, a terminal and a computer readable medium, and relates to the field of electronic communication. The method comprises the following steps: reading an instruction line from a circular buffer queue ring_buf; under the premise that the instruction line data is correct, querying and calling an element matched with the data line in a URC table, executing a function corresponding to the element, releasing a second semaphore resp_notice, and completing the analysis of the AT instruction; when the URC table does not store the element matched with the data line, querying whether the last line of a string of a processing result fed back after the execution of the AT instruction by a data transmission module is a correct identifier OK or a failure or error identifier, if the correct identifier OK, marking a response state resp_status as successful and releasing the resp_notice semaphore, and completing the analysis of the AT instruction; if the failure or error identifier, marking the response state resp_status as a failure and releasing the resp_notice semaphore, and completing the analysis of the AT instruction. The application realizes the analysis of AT instructions of different data transmission modules.

A compiler creates a dependency graph for functions in an input program. The dependency graph includes nodes corresponding to commands within the functions and edges corresponding to dependencies between commands. The compiler performs forward reachability analysis on the dependency graph to eliminate redundant dependencies. The compiler also adds a minimum set of back edges to the dependency graph to enforce circular resource dependencies in the input program. Then, based on the contents of the dependency graph, the compiler assigns synchronization primitives (such as semaphores) provided by the multiprocessor computing system to commands within the functions of the input program.

This invention discloses a method for protecting inter-thread communication using semaphores in a Linux system, comprising the following steps: After the Linux system starts, semaphores S1~S2 are created. n Create threads T1~T 2n Create inter-thread semaphore protection flags F1~F n n is a positive integer; the semaphores S1~S2 are implemented using the system-provided sem_init function. n The initialization is performed using the system-provided pthread_create function to implement threads T1~T. 2n Initialization uses the system-provided assignment operator to set the inter-thread semaphore protection flags F1~F1. n Initialized to 0. This invention effectively solves the synchronization problem and false permission problem in inter-thread communication by adding an inter-thread semaphore protection flag and further determining whether it is really necessary to activate the thread of the communication object by judging the value of the inter-thread semaphore protection flag, thus ensuring the effectiveness and reliability of inter-thread communication.

The invention discloses an inter-process communication method, electronic equipment and a storage medium, and relates to the technical field of communication. According to the scheme, the method comprises the following steps: executing semaphore waiting operation for an associated theme in a shared memory in a receiving end process so as to enter a blocked state and release processing resources; in a sending end process, target communication data is written into a target theme in a shared memory, a semaphore associated with the target theme is triggered to be updated to generate a target event notification, so that all receiving end processes blocked in the semaphore exit a blocked state, and the target event notification is sent to the receiving end process in the receiving end process receiving the target event notification. And obtaining target communication data from the target theme. In the scheme, the receiving end process is kept in the blocked state when no data is processed, and processor resources are not occupied; meanwhile, semaphore notification and data transmission are both completed in the shared memory, data copying and context switching between a kernel mode and a user mode are avoided, and therefore low processor resource occupation and low communication delay are achieved.

A method for serving machine learning (ML) model over at least two pipes includes defining a function that receives at least two process pipes as arguments, and defining another class. The other class is used for creating and storing future objects and setting the result from another thread. The method also includes releasing a semaphore to avoid overloading of a second pipe once the data is sent to the other thread, and writing an asynchronous function to a first pipe or an input pipe in order to send the data to the other thread.

A compiler creates a dependency graph for a function in an input program. The dependency graph includes nodes corresponding to commands in the function and edges that correspond to dependencies between the commands. The compiler performs a forward reachability analysis on the dependency graph to eliminate redundant dependencies. The compiler also adds a minimized set of back-edges to the dependency graph to enforce loop-carried resource dependencies in the input program. The compiler then allocates synchronization primitives provided by a multiprocessor computing system, such as semaphores, to the commands in the function of the input program based on the contents of the dependency graph.

Apparatuses, systems, and techniques to facilitate graph code synchronization between application programming interfaces. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause graph code to wait on a semaphore used by another API.

The application discloses a scheduling method and device of asynchronous tasks, equipment, a storage medium and a program product, and relates to the technical field of servers. The method comprises the following steps: in response to receiving a processing request of a calculation task, generating task queue information corresponding to the calculation task; acquiring a first semaphore and a second semaphore corresponding to at least one type of asynchronous task, wherein the first semaphore is used for indicating the task quantity of the asynchronous tasks processed by a task processor, and the second semaphore is used for indicating the task quantity of the asynchronous tasks to be processed submitted by a calculation processor; determining whether the first semaphore and the second semaphore corresponding to the type of asynchronous task satisfy a preset condition variable, if yes, waking up an asynchronous task thread, reading task parameters corresponding to the type of asynchronous task from the task queue information through the asynchronous task thread, and executing the type of asynchronous task according to the task parameters. The method can improve the resource utilization rate of a server cluster.

The invention provides an embedded real-time operating system-oriented high-reliability inter-thread synchronous communication method and related equipment, and belongs to the field of communication. The method comprises the following steps: initializing a synchronous resource and a thread portrait, and establishing a mapping table of a semaphore pool and a lock object; carrying out synchronization overhead modeling and estimation, and recording thread waiting time, lock occupation duration and switching times by using a sampling window to form dynamic statistical data; setting a synchronization performance threshold value and an abnormal logic judgment rule; co-scheduling of semaphores and locks is executed, thread requests are sorted in a combined mode according to priorities, waiting time and resource occupancy rates, and the semaphores are dynamically distributed; health assessment and adaptive optimization are carried out, and a semaphore distribution strategy and a lock priority are automatically adjusted according to a synchronization performance deviation value; and if abnormity is detected, the synchronization module triggers a protection mechanism, redistributes the thread scheduling table and sends out alarm information. According to the method and the device, the embedded real-time operating system can have higher reliability and self-adaptive capability in a high-concurrency environment.

A test data uploading method, device and system are disclosed. Based on a first test vector, a corresponding test board card is controlled to perform a first test operation, and the first test operation includes writing test output data corresponding to the first test operation into a first storage area of a memory of the test board card. During the execution of the first test operation by each test board card, in response to receiving a first semaphore, test output data in a second storage area of the memory of the test board card is synchronously written into shared memory, and the test output data in the second storage area is test output data corresponding to a second test operation performed before the first test operation. In response to the test output data corresponding to the second test operation being successfully written into the shared memory, a second semaphore is sent to an upper computer, and the upper computer reads the test output data corresponding to the second test operation from the shared memory according to the second semaphore, so that test data uploading is realized during the test process, and the data uploading efficiency is improved.

The application provides a method and medium for interface conversion from a VxWorks system to an embedded Linux system, which comprises: constructing a compatible layer in a user state, rewriting key system function APIs of the VxWorks, such as task management, message queue, semaphore and watchdog, and calling Linux native system functions or implementing corresponding logic by itself in the internal, and finally compiling the implementation code into a static library or a dynamic library. An application program only needs to link the library and include the corresponding header file, so as to be compiled and run in the embedded Linux system without modifying the core source code. The application realizes seamless transplantation in the user state without modifying the operating system kernel and configuration, significantly reduces the transplantation cost and system stability risk, and is suitable for various deployed Linux environments.

The invention discloses a PLC task scheduling method and device, electronic equipment and a storage medium. According to the specific implementation scheme, when the semaphore of a clock reference task is detected, a plurality of first-type tasks are triggered; and when it is detected that the first type of tasks meeting the half-cycle offset scheduling condition exist, performing half-cycle offset scheduling on the first type of tasks. According to the technical scheme, the first type of tasks meeting the half-cycle offset scheduling conditions are subjected to half-cycle offset scheduling, resource competition and scheduling conflicts caused by multi-task concurrence can be effectively avoided, and therefore the efficiency and reliability of PLC task scheduling can be improved.

Accelerating and improved fairness for semaphores is described. In one or more implementations, a computing device includes a plurality of cores and one or more computing resources, exclusive access to which is limited, e.g., to a single core at a time. In one or more implementations, the computing device also includes core selection circuitry configured to identify a first core from the plurality of cores exclusively accessing the one or more limited computing resources and configured to instruct a second core from the plurality of cores to release the exclusive access of the first core to the one or more computing resources.

Accelerating and improved fairness for semaphores is described. In one or more implementations, a computing device includes a plurality of cores and one or more computing resources, exclusive access to which is limited, e.g., to a single core at a time. In one or more implementations, the computing device also includes core selection circuitry configured to identify a first core from the plurality of cores exclusively accessing the one or more limited computing resources and configured to instruct a second core from the plurality of cores to release the exclusive access of the first core to the one or more computing resources.

The device described herein, which provides an interface between a plurality of master devices and a slave device, includes: a first timer configured to begin timing when a first access request is received from a first master device via a bus, and to be reset when a semaphore is allocated to the first master device; a second timer configured to begin timing when a second access request is received from a second master device via the bus, and to be reset when a semaphore is allocated to the second master device; and a controller configured to provide a first message to the first master device via the bus when a first expiration interval is measured by the first timer.

The invention discloses rectification task distribution equipment capable of being monitored in real time and a distribution method thereof, and the equipment comprises a signal reading module which is used for reading the total number of semaphores when a list distribution instruction is detected; the judgment module is used for judging whether to-be-distributed data exists or not; and the thread calling and distributing module is used for calling a thread according to the semaphore if the data to be distributed exists, performing list distribution based on the thread, and releasing the thread after the distribution is completed. According to the rectification task distribution equipment capable of being monitored in real time and the distribution method of the rectification task distribution equipment, the number of threads executed by multiple threads is limited, and meanwhile, after semaphores are recycled, execution results of the multiple threads are waited to be processed. Within the machine performance range, the distribution rate can be quickly expanded only by configuring the number of the semaphores, and the distribution rate is linearly improved. When the machine performance reaches the bottleneck, the performance can be improved by sharing the semaphore.

The invention provides a code compiling method and device, electronic equipment and a readable storage medium, and relates to the technical field of processors, the method comprises the steps of obtaining an assignment statement in a to-be-compiled code and a register corresponding to each variable in the assignment statement; if a conflict register with a plurality of corresponding variables exists in the register, setting a shadow register and a semaphore for each variable corresponding to the conflict register; compiling the to-be-compiled code into a first hardware description language code comprising a shadow register and a semaphore; the shadow register is used for writing a variable value of a variable corresponding to the shadow register; the semaphore is used for sequentially writing the variable values in the shadow register into the conflict register according to the priority of the variables after the variable values are written into the shadow register. According to the method, the problem of multi-source driving errors when the same variable is assigned by a plurality of assignment statements in the code compiling process can be solved.

The application discloses a multi-core communication method and device based on hardware-assisted semaphores, equipment and medium, and relates to the technical field of computers. The method comprises the following steps: determining a target hardware-assisted semaphore from a preset semaphore state bitmap based on queue request information; creating a target remote procedure call communication queue, and determining queue metadata related to the target hardware-assisted semaphore and the target remote procedure call communication queue; registering the queue metadata to a lock-free hash table based on an atomic operation, so as to establish a binding relationship between the target hardware-assisted semaphore and the target remote procedure call communication queue; and based on the binding relationship, completing multi-core communication of different subsystems through the target remote procedure call communication queue and the target hardware-assisted semaphore. It can be seen that the application can avoid the problem of asynchronous allocation and creation of semaphores and queues, avoid waste caused by long-term idling of resources, effectively improve the communication running efficiency in a multi-core environment, and guarantee the real-time response capability of the system.

This application discloses a method, apparatus, electronic device, and storage medium for semaphore anomaly localization, belonging to the field of computer technology. It records semaphore metadata corresponding to management operations on each semaphore based on a target data structure. The semaphore metadata includes the semaphore identifier and variable address of each semaphore in the target system. When a semaphore anomaly occurs in the target system, the abnormal semaphore identifier is obtained. Based on the abnormal semaphore identifier, the target variable address corresponding to the abnormal semaphore identifier is searched in the semaphore metadata. The corresponding target code segment is located based on the target variable address. This allows for real-time tracing from the abnormal semaphore identifier to the target code segment in the program code after a semaphore anomaly occurs in the target system, improving the efficiency of semaphore anomaly localization, shortening anomaly investigation and repair time, and thus improving system maintenance efficiency.

The invention provides a spin lock implementation method and device based on hardware semaphore, equipment and a medium, and relates to the field of embedded operating systems, the method comprises the following steps: binding a spin lock with the hardware semaphore, and allocating a counting register to the spin lock; if the first core requests to acquire the spin lock, verifying whether the current holder of the hardware semaphore is the first core; if yes, reading a count value for validity check, and if valid, adding 1 to the count value and returning; if the core is not the first core, hardware semaphore locking is called; after the hardware semaphore is obtained, whether a current holder is a first core is verified, if yes, whether a count value is 0 is verified, and if yes, 1 is added to the count value, and a memory barrier instruction is inserted; if the first core requests to release the spin lock, verifying whether the first core is a holder of the spin lock; if yes, subtracting 1 from the count value, judging whether the count value is 0 or not, and if yes, calling hardware semaphore for unlocking to complete lock release. The scheme can reduce system power consumption.

Apparatuses, systems, and techniques to perform an application programming interface (API) to add one or more graph nodes to a software graph, wherein the API is to cause a semaphore wait node to be added to a software graph based, at least in part, on a dependency type indicated by the API. In at least one embodiment, one or more nodes are added to a graph in accordance to one or more dependency types.

The invention provides a video generation method and device for an Android operating system and a medium. The method comprises the following steps: in a Vulkan exchange chain initialization stage, creating a rendering main thread and a display special thread; an Empty Semaphore and a Full Semaphore are established, and the Empty Semaphore and the Full Semaphore are established; in the operation stage, the rendering main thread obtains the idle frame buffer through the exchange chain and executes the rendering process of the current frame; the display thread monitors an Empty Semaphore state in real time and submits frame data to a Surface Flinger for display after detecting a non-null signal, the Full Semaphore state is directly detected after the rendering main thread completes rendering of the current frame, and if the Full Semaphore state is not full, an idle frame buffer is obtained, and the rendering process of the next frame is executed. According to the method provided by the invention, the time delay caused by frame insertion can be effectively reduced under the condition that an Android underlying driver does not need to be modified.

This application provides a code compilation method, apparatus, electronic device, and readable storage medium, relating to the field of processor technology. The method includes: obtaining assignment statements in the code to be compiled, and registers corresponding to each variable in the assignment statements; if there are conflict registers with multiple corresponding variables in the registers, setting a shadow register and a semaphore for each variable corresponding to the conflict registers; compiling the code to be compiled into first hardware description language code including shadow registers and semaphores; the shadow registers are used to write the variable values ​​of the variables corresponding to the shadow registers; the semaphores are used to sequentially write the variable values ​​in the shadow registers to the conflict registers according to the priority of the variables after the variable values ​​are written to the shadow registers. The method of this application can solve the multi-source drive error problem when multiple assignment statements assign values ​​to the same variable during code compilation.

A method for controlling a neural network circuit that is provided with a first memory, a convolution operation circuit that performs a convolution operation, a second memory, a quantization operation circuit, a second write semaphore, a second read semaphore, a third write semaphore, and a third read semaphore, wherein the method for controlling the neural network circuit involves making the convolution operation circuit implement a convolution operation based on the third read semaphore and the second write semaphore.