501 results about "External storage" patented technology

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

The invention provides an instruction cache and a prefetching method thereof. The instruction cache comprises a hit detection module, an instruction prefetching module and an operation module. The hit detection module checks whether a current instruction fetching request of a current thread bundle is hit. The instruction prefetching module dynamically determines an instruction prefetching range corresponding to the current instruction fetching request according to the execution progress of the current thread bundle. The operation module accesses the external storage to prefetch the instruction data corresponding to the instruction prefetch range. And in response to the fact that the hit detection module judges that the current instruction fetching request is hit, the operation module feeds back instruction data corresponding to the current instruction fetching request to the current thread bundle. And in response to the fact that the hit detection module judges that the current instruction fetching request is missed, the operation module accesses external storage so as to feed back instruction data corresponding to the current instruction fetching request to the current thread bundle.

The invention discloses a video data transmission method and system based on an FPGA, and relates to data transmission. The method comprises the steps that a video data stream is acquired, and a time sequence signal of the video data stream is analyzed; writing the parallel data into an external memory to form a frame buffer area; packaging the read video data into a data packet meeting a USB3.2 transmission protocol; packaging the data packet based on a USB3.2 link layer protocol; and converting the USB3.2 protocol transmission frame into a differential signal, and transmitting video data in the USB3.2 protocol transmission frame according to the differential signal. In view of data loss caused by mismatching of a video input rate and a USB output rate in the prior art, by establishing an annular buffer structure and adopting a dynamic pointer management and waterline threshold monitoring mechanism, rate adaptive matching of a video data stream is realized, and continuous and stable transmission of video data is ensured.

The invention discloses a self-attention mechanism calculation method, a calculation array, a calculation device, a calculation system and a computer readable storage medium. The self-attention mechanism calculation method is applied to a self-attention mechanism calculation array, the self-attention mechanism calculation array comprises a plurality of product accumulators, the plurality of product accumulators form a systolic array, and the self-attention mechanism calculation method comprises the following steps: performing calculation through the plurality of product accumulators according to a feature tensor and a weight tensor to obtain an intermediate tensor; and a result tensor is calculated according to the intermediate tensor through a plurality of product accumulators. Therefore, frequent memory access of the intermediate tensor between the self-attention mechanism calculation array and the external memory is avoided, the calculation efficiency is improved, and the problems of intermediate tensor multiplexing and storage optimization are solved.

There is provided a method for providing a service by an artificial intelligence(AI) agent with a multi-turn. A cost for performing tasks of an AI agent is reduced and a speed of performing the tasks is improved by maintaining only messages for the most recent j turns as originals and using summary message for each of messages of previous turns of the most recent j turns. Further, a risk of information loss in a multi-turn of the AI agent is eliminated by storing original messages corresponding to the summary messages in an external storage and thus allowing the original messages to be accessed when necessary.

A parameter-setting program operates on an information terminal 50 that may perform wireless communication with a combustion device 10. The parameter-setting program may cause the information terminal 50 to execute: processing to cause, when a parameter is to be set for one combustion device 10, the information terminal 50 or an external storage device to store the parameter inputted into the information terminal 50; processing to cause, when, after the storing, the parameter is to be set for another combustion device, the information terminal 50 to display an option to instruct the information terminal 50 to write the stored parameter into the other combustion device 10; and processing to write the stored parameter into the other combustion device 10 when the option is selected.

The invention discloses a big language model dialogue system for Token-level resident memory and a use method. The big language model dialogue system comprises an inference engine module, a big language model module, an independent memory model module and an external storage module, relates to the technical field of big language model memory enhancement, after a current dialogue Token sequence is received, whether historical dialogue information is needed or not is judged through a big language model module, and if yes, the historical dialogue information is called from an external storage module through an independent memory model module, so that information displayed by finally responding to the Token sequence is more complete, and user experience is improved. The problems that a model cannot completely retain and utilize long-distance historical information, so that questions cannot be answered and information is forgotten are solved; an external storage module is arranged, and model parameters of an independent memory model module and Token-level data of all historical conversations are resided through a memory mapping technology; and zero occupation of the GPU video memory is realized.

Systems and methods for enabling availability of backup data during restoration of a distributed database system are provided. An external storage system stores a plurality of backup files each comprising backup data and one or more backup metadata files. A plurality of ranges are generated and stored among a plurality of computing devices based on the backup files and metadata files. A plurality of virtual data files are generated and stored in the ranges, where each range of the ranges comprises one or more of the virtual data files, where the virtual data files for a respective range identify physical data configured to be stored by the respective range comprising at least a portion of the backup data of one or more of the backup files. The ranges are configured to serve, based on the virtual data files, a request directed to reading or writing the physical data.

An electronic device is provided. The electronic device includes a housing configured to form at least a portion of an exterior appearance of the electronic device, a socket accommodated in the housing corresponding to a tray hole formed in the housing, a tray inserted into the socket through the tray hole and configured to support an external storage medium, a microphone accommodated in the housing, and a hole (H1) formed in the housing or the tray, wherein, when a pin is inserted through the hole (H1), the tray is separated from the socket, and wherein a sound from the outside of the electronic device is introduced through the hole (H1) to be transmitted to the microphone.

The invention discloses a control system supporting concurrent access of multiple hosts, a storage device and a medium, and relates to the technical field of data storage, the system runs on a control module externally connected with the storage device, and the system comprises a communication connection management unit used for establishing connection with multiple hosts through at least two host interfaces; the access request receiving unit is used for receiving access requests sent by different hosts through an uplink port of the multi-host switching chip, and the access arbitration and scheduling unit is used for carrying out real-time arbitration and unified scheduling on the requests according to a preset strategy; and the instruction forwarding and execution unit forwards an arbitrated instruction to the storage unit for execution through a downlink port, and the system further integrates a cache consistency management unit, a configurable arbitration strategy unit, a multi-mode storage space management unit and the like, so that the data consistency, the access efficiency and the system reliability during multi-host concurrent access are ensured. According to the scheme, efficient and safe parallel access of a plurality of hosts to a single storage device is realized.

The invention provides a data processing method and device of a processor, equipment, a medium and a program product. The method comprises the steps of loading an mth data block in a first matrix to a first cache position of an internal memory through a first thread in a thread group of a processor, and loading an nth data block in a second matrix to a second cache position of the internal memory; loading the (n + 1) th data block in the second matrix from the external memory to a third cache position of the internal memory through the first thread, and performing multiplication operation on the data blocks in the first cache position and the data blocks in the second cache position through the second thread; and loading the (n + 1) th data block in the second matrix from the internal memory to a second cache position of the internal memory through the first thread, and performing multiplication operation on the data block in the first cache position and the data block in the third cache position through the second thread. According to the invention, the calculation speed of multiplication in the processor can be improved.

The invention relates to the technical field of chips, and provides a tensor memory accelerator and a tensor memory acceleration method.The tensor memory accelerator comprises an instruction distribution unit and a plurality of tensor memory acceleration engines capable of conducting parallel processing; wherein the instruction distribution unit is used for distributing a tensor memory acceleration instruction to idle engines in a plurality of tensor memory acceleration engines for execution, each tensor memory acceleration engine is provided with a descriptor storage unit for storing descriptors, and each tensor memory acceleration engine is used for storing the descriptors according to multiplexing identification information in the tensor memory acceleration instruction. And multiplexing the descriptors from the corresponding descriptor storage units or obtaining new descriptors from the external memory. According to the invention, each tensor memory acceleration engine can selectively multiplex descriptors from the local or obtain new descriptors from the outside, so that instruction-level parallel processing and effective multiplexing of descriptor information are realized.

The invention discloses a read-only memory program correction system and method, and relates to the technical field of computers, the read-only memory program correction system comprises a program comparison module, a program correction module and an address management module; the program comparison module is used for obtaining a standard signature value and an actual signature value and comparing the standard signature value with the actual signature value to obtain a comparison result of each program segment; the program correction module is used for controlling the system on chip to obtain a correction program corresponding to the target program segment from the external storage device and storing the correction program into the target storage unit; and the address management module is used for mapping an address field of the target program segment in the read-only memory into a target address field of the correction program in the target storage unit. When the wrong target program segment is started, the wrong target program segment is directly corrected and replaced by the correction program through the mapping relation, so that segmented correction and replacement of the wrong program segment are realized, the risk that the replaced correction program is physically attacked or tampered is reduced, and the reliability and safety of the starting program are improved.

A fluid pump includes a motor disposed within an outer housing. The motor includes a stator and a rotor in electromagnetic communication with the stator. Windings are disposed on the stator that receive an electric current for defining the electromagnetic communication. A pump element is attached to the rotor via a drive shaft. The pump element operates with the rotor to deliver a fluid through a hydraulic fluid path. A plurality of sensors measure information related to at least one of the stator, the windings, the rotor, the pump element, the fluid and the hydraulic fluid path. A controller is in communication with the windings for delivering the electric current to the windings. The controller is also in communication with the plurality of sensors for measuring and recording the information and communicating this information to one of an external memory and an external controller.

Methods are provided comprising: mapping a portion of a local primary memory to an address space of a virtualization instance at a client device, wherein the address space is addressable by a processor of the client device, and wherein the virtualization instance is executed via the processor of the client device; mapping a first portion of external memory to the address space, wherein the external memory is memory that is external to the client device but treated as primary memory at the client device, and wherein a second portion of the external memory is not in any address space addressable by the processor of the client device; providing a performance indication data structure indicating a performance difference between the portion of the local primary memory mapped to the address space and the first portion of external memory mapped to the address space; and causing data to migrate between the external memory and the local primary memory based on the performance indication data structure by the virtualization instance, wherein the data is caused to migrate by the virtualization instance and / or a logic configured to operate with the virtualization instance.

The application discloses a kind of high-performance distributed mass vector similarity search system and method, including Faiss Driver, several Faiss Worker and Etcd system;Faiss Driver is used to receive the query request of user end, and the query request is forwarded to the selected Faiss Worker by proxy, and is configured to perform loading configuration Etcd monitoring, exit pre-processing, service discovery and master-slave election task;Faiss Worker is the unit for executing query calculation in search system, and is configured to perform configuration management, shutdown processing, timing task, load index and query calculation task, for calculating similar vector retrieval and updating online or offline index file;Etcd system is used to save Faiss Worker list, master-slave state of Faiss Worker, health status of Faiss Worker, external storage module address of index file and index file list.The application introduces proxy forwarding service mechanism and master-slave node registration mechanism, and can efficiently process vector query calculation request.

The application discloses a master-slave space mining robot adaptive control system based on IAVOA, which comprises the following steps: a master-slave kinematic model of the space mining robot is established according to the structure and motion characteristics of the space mining robot, and then a trajectory tracking control system of the space mining robot is established; in the controller design process, the direct feedback linearization theory is adopted to realize the global accurate linearization of the nonlinear system of the space mining robot, and the kinematic problem of the space mining robot is greatly simplified; the optimal initialization of the algorithm population is realized by introducing the Henon chaotic mapping population initialization and elite population strategy; the external storage library can help the vulture population to select more solution space, and avoid generating a large number of same non-inferior solutions; the adaptive optimization adjustment of the control parameter of the space mining robot control system can be realized, the complex working environment on the surface of the asteroid can be effectively coped with, and the accurate control of the motion of the system on the space mining robot can be realized.

An input / output unit communicates with a memory located outside a data processing device to provide a sub-processing function to perform data processing using a memory located inside the data processing device and a memory located outside the data processing device. Delay due to access to the memory located outside the data processing device by a processing unit of the data processing device may be reduced, and processing performance by the data processing device may be improved.

The invention relates to the field of data transmission, in particular to a one-way data transmission device which comprises a data transmission chamber and an optical disc recycling bin communicated with the data transmission chamber through an optical disc recycling opening. The data transmission room is provided with an external network unit, an internal network unit, a transfer bin and a signal transmission module; the external network unit is used for reading data from an external storage medium, recording the data in a pre-stored optical disk, transferring the optical disk to a transfer bin, and triggering the signal transmission module to send a signal to the internal network unit; and the intranet unit is used for transferring the optical disc in the transfer bin to the preset CD driver according to the signal, reading data from the optical disc in the preset CD driver, and transferring the optical disc from the preset CD driver to the optical disc recovery port. An absolute physical isolation barrier is established between the internal network and the external network, one-way, automatic and safe ferrying of data from the external network to the internal network is achieved, the risk of data leakage is effectively eradicated, and the safety and reliability of data transmission between computers of the internal network and the external network are improved.

Provided are an apparatus and method for verifying forgery of a medical image using a hash value based on meta information of the medical image.SOLUTION: The forgery verification apparatus 400 includes a memory configured to store patient-specific DICOM files and a processor functionally connected to the memory, and the processor is configured to, when issuance of a DICOM file is requested, search for the requested DICOM file among the patient-specific DICOM files, generate an issuance number associated with the issuance, extract a part of meta information of the DICOM file, generate a first hash value using the part of the meta information and the issuance number, and store the first hash value in the memory in association with the issuance number. While providing a copy of a DICOM file to an external storage device, a first hash value is inserted into a designated tag area of the copy as forgery verification information.SELECTED DRAWING: Figure 1

A safe access method, a safe access device, a safe access electronic apparatus and a safe access storage media for external storage devices are provided. By reporting and processing without relying on real-time network connections, and still maintaining effective management of access to portable external storage devices even when there is no network or the network is unstable, thereby reducing potential risks and avoid frequent returns due to risky hardware and reduce the burden of network communications in the enterprise, immediately being disabled the portable external storage device once a digital certificate to be verified is found to be non-compliant, reducing a chance of spreading virus infection for improving the efficiency of information security management through quick response, and destroying the digital certificate to be verified to prevent the certificate from being stolen by others after confirming the safety of the external storage device, thus further ensuring the company's data security, the system and the method can effectively reduce misjudgment and ban of legitimate hardware through verification of digital certificates, and can achieve the effect of reducing the inconvenience caused by users frequently disabling legitimate devices.

Embodiments of the present application relate to the technical field of communication, and provide a communication method, related devices and storage media. The method comprises: receiving an address translation service (ATS) request from an endpoint (EP). Querying an address translation protection table (ATPT) according to an input / output virtual address (IOVA) to be translated. If the HPA corresponding to the IOVA to be translated does not exist in the ATPT, sending a page scheduling request to a central processing unit (CPU), the page scheduling request being used to instruct the CPU to allocate an HPA for the IOVA to be translated. Querying the ATPT according to the IOVA to be translated again to obtain the HPA corresponding to the IOVA to be translated. Sending an ATS response to the EP. In the embodiments of the present application, when the RC receives the ATS request initiated by the EP and does not query the valid mapping of the IOVA, the RC does not send a failure response to the EP, but triggers the CPU to perform page scheduling, loads the required page from the external storage and updates the page table mapping. The EP can receive a successful response and obtain the HPA mapped by the IOVA, implement address access, thereby reducing the number of interactions with the RC, saving the process, reducing the delay, and improving the address translation efficiency.

A memory device is provided. The memory device includes: a buffer memory; and a memory controller configured to: obtain map data and meta data for recovering the map data from at least one external storage device; store the map data and the meta data obtained from the at least one external storage device in the buffer memory, the buffer memory being allocated for the at least one external storage device; translate a logical address corresponding to the at least one external storage device into a physical address of the buffer memory; and send the map data and the meta data to the at least one external storage device in response to detecting a sudden power-off event.

This nursing care work assistance system for assisting in nursing care work comprises: a data aggregation unit that aggregates data related to nursing care; and a processing unit that performs data processing by using the data. The data aggregation unit stores metadata and a subnet of the data stored in an external storage of the system. The data aggregation unit accesses the data in the external storage by using the subnet and stores the data in a concealed state. The nursing care work assistance system further comprises a processing model aggregation unit that aggregates processing models that are used by the processing unit for the data processing. The processing model aggregation unit stores the processing models in a concealed state.

The application discloses a file loading method, device and equipment. The method comprises the following steps: in response to an instruction of starting a first application of an electronic device, a kernel layer of the electronic device loads a target file used for running the first application from an external storage of the electronic device to a physical memory of the electronic device; and in a starting process of the first application, the first application loads the target file obtained from the physical memory. The file loading method provided by the application can improve the file loading efficiency.

The application relates to a real-time data sorting system, which comprises a control unit, an input data preprocessing unit, a sorting module and a data buffer and output unit, the control unit is used for realizing the control of the input data preprocessing unit and the sorting module, the input data preprocessing unit is used for determining whether the sorting module can receive new external data and is used for judging whether sequence data is input into the sorting module, the sorting module is used for sorting the sequence data input into the sorting module, and the data buffer and output unit are used for information buffering and outputting the sorted data. The number of times of reading input data from an external memory is reduced, the data communication amount and data access overhead are reduced, the operation cost of the sorting operation is reduced, the efficiency is improved, and the sorting operation of any scale can be supported with the smallest FPGA resource consumption.

The invention belongs to the field of GPGPU chip design, and particularly relates to a GPGPU thread block scheduling method and system based on data space locality, and the method comprises the steps: carrying out the statistics of Bank feature information of access data of all thread blocks, and classifying the thread blocks accessing the same Bank into the same Bank group according to the Bank feature information; preferentially distributing the thread blocks of the same Bank group to the same programmable multiprocessor until the resources of the programmable multiprocessor are saturated; setting a private row cache space for each Bank in each programmable multiprocessor; when the data in the private line cache space is updated, synchronously updating the corresponding data in the L1 cache, the L2 cache and the DRAM; counting the hit rate of the private line cache in real time, and closing the private line cache function when the hit rate is lower than a preset threshold value. High-delay external storage access is reduced, the data reuse rate is improved, and the execution efficiency is remarkably improved.

This application provides a data encryption method and an SoC for use in a SoC. The method includes: receiving external data to be written through an interface module, and dividing the external data into consecutive data blocks in a first order; generating corresponding dynamic keys for each data block based on its content characteristics through a processing module; encrypting the corresponding data blocks using the dynamic keys through the processing module to obtain encrypted data blocks; scattering the encrypted data blocks into a second order according to a pre-set rule and encrypting them again using a pre-stored fixed key to obtain encrypted external data; and writing the encrypted external data to an external storage device through the processing module. In this embodiment, the dynamic keys are determined by the content characteristics of each data block; different data generates different keys, and even if partial ciphertext is obtained, the decryption method for other blocks cannot be deduced.

Encryption system with an application-specific integrated circuit (ASIC) which has a permanent memory for the non-volatile storage of the operating system (OS) of a processor and software modules for encrypting the data memory of the processor and which has a hardware-implemented encryption algorithm, characterized in that a security module (SM) is integrated in the ASIC for autonomous booting of the operating system (OS), consisting of: - a symmetric cryptosystem (SK) for processing symmetric keys, - an asymmetric cryptosystem (AK) for the use of public and private keys, - a module for generating cryptographic hash functions (KH), - a module for the secure exchange of keys using hardware-implemented key exchange protocols (SP), - a key storage (SS) for the secure storage of root keys (WS), which are protected by appropriate measures in the physical structures of the ASIC and - a key management system (SMS) for the secure introduction of authenticated-encrypted key packets, and that the security module (SM) communicates with a central processing unit (CPU) via a communication interface (CS1), and that the central processing unit (CPU) communicates with at least one internal storage (IS) and one external storage (ES), as well as with at least one internal persistent storage (IP) and one external persistent storage (EP), such that the operating system (OS) is loaded by a second-stage bootloader (SSB) stored in the external persistent storage (EP), and then the operating system (OS) loads the applications, the second-stage bootloader (SSB) itself being decrypted and loaded by a first-stage bootloader (FSB) stored in the internal persistent storage (IP), and a public key (PUBOS) to verify the operating system (OS).and a symmetric key (KOS) to decrypt the operating system (OS), and that the contents of the internal memory (IS) and the external memory (ES) are decrypted by the security module (SM) during read accesses by the central management unit (CMU) or other modules integrated on the ASIC, and re-encrypted during write accesses by the same.

The application discloses a DSP starting program loading method, device and equipment and a storage medium, wherein the method comprises the following steps: when a DSP chip is powered on, target codes are moved from an external memory to an internal program storage area of the DSP chip; the target codes moved to the internal program storage area are compared with the target codes in the external memory; when the target codes in the internal program storage area are inconsistent with the target codes in the external memory, the inconsistent code segments in the target codes in the internal program storage area are re-written according to the target codes in the external memory, and when the target codes are consistent, other codes and data except the target codes in the external memory are loaded to the DSP chip. The application guarantees that the loaded target codes for DSP configuration are consistent with the target codes in the external memory, and then other codes are loaded, so that the high reliability of the program is ensured.