967 results about "External storage" patented technology

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and / or an external memory.

The invention provides a flexible convolution operation accelerator based on a systolic array. The flexible convolution operation accelerator is used for solving the technical problem that the hardware scale of an existing convolution operation accelerator is difficult to flexibly adjust according to different hardware platforms. The system comprises an input cache module, a pulsation matrix, an accumulation logic unit and an output cache module which are connected in sequence, the input cache module comprises a weight cache module and an image cache module, and the weight cache module and the image cache module are both connected with the pulsation matrix. The weight cache module, the image cache module, the pulsation matrix, the accumulation logic unit and the output cache module are all connected with the controller, and the controller and the output cache module are both connected with an external memory through a BUS. The systolic array and the flexible cache module are utilized, the functions of data storage and data format conversion can be achieved at the same time, hardware logic overhead is reduced, high memory access efficiency is achieved, and configuration of the accelerator scale and various convolution parameters is supported.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

The invention provides a dual-storage system starting method and device. An architecture in which a master control chip SOC works cooperatively with an external memory DDR, a nonvolatile memory SPI NOR and an SD card is adopted. After the SOC is powered on, a BootROM guide code is executed, a system is initialized, ID Blocks containing a DDR initialization program and an SPL secondary loading program are sequentially obtained and verified from multiple storage media, the DDR initialization program is loaded, DDR is initialized, and the SPL secondary loading program is loaded to the DDR to run. The method comprises the following steps of: firstly, loading an SD (Secure Digital) card, then loading U-Boot firmware, completing initialization of residual hardware and security mirror verification, then detecting and verifying a kernel mirror format and Header information in the SD card, then loading a Linux kernel, an equipment tree and a ramdisk, mounting rootfs to an RAM (Random Access Memory) space, and mounting the SD card as a user data storage space. According to the method, high reliability of system guiding is ensured through the SPI NOR, large-capacity storage and flexible upgrading are achieved through the SD card, and the comprehensive performance of the embedded system in the aspects of reliability, storage expansibility and cost effectiveness is remarkably improved.

The invention relates to a video acquisition and transmission method and device for converting a 10-gigabit network into a PCIe (Peripheral Component Interconnect Express) interface. The method comprises the following steps: receiving a video stream through a double 10-gigabit network optical module, carrying out protocol analysis and preprocessing through an FPGA (Field Programmable Gate Array), realizing multi-path alternate reading and writing by utilizing DDR3 ping-pong cache, dynamically distributing the video stream to multiple devices through a three-path PCIe 3.0 * 4 interface and an XDMA (Extensible Direct Memory Access), and optimizing the transmission priority in combination with a load state. The device comprises two paths of SFP + optical modules, a Xilinx Virtex7 series FPGA chip (integrated with a 10-gigabit network MAC, a PCIe XDMA IP core and a DDR3 controller), three paths of PCIe 3.0 * 4 interfaces and an external DDR3 memory. The system has the advantages that the double 10-gigabit network input and multi-PCIe channel collaborative architecture breaks through the single-channel bandwidth bottleneck; the intelligent ping-pong cache and the AXI arbitration strategy reduce the data conflict risk; and dynamic bandwidth allocation optimizes real-time performance.

The invention discloses a method and a system for automatically generating a business APP of a fusion terminal, which are applied to the technical field of smart power grids, and the method comprises the following steps: accessing an external storage device to a target fusion terminal; the management APP of the target fusion terminal obtains basic information of a service APP needing to be generated, and sends the basic information to the packaging APP and the guarding APP; the packaging APP selects a corresponding adaptive template from a template library according to the adaptive data, and performs parameter configuration on the selected adaptive template to form a service APP needing to be generated; the management APP is locally deployed and operated in the target fusion terminal; and the guarding APP maintains the running service APP according to the configuration data. According to the method, code development is not needed, and the service APP is automatically configured and generated; meanwhile, automatic operation and maintenance of the generated service APPs are achieved, the service APPs which are not needed temporarily are directly deleted from the fusion terminal, and storage resources of the fusion terminal are effectively saved.

The invention relates to the technical field of parallel computing chips, in particular to a multiprocessor management method and device based on a parallel computing chip and a medium. The method comprises the steps that a plurality of stream processors are organized according to a hierarchical arrangement mode, a hierarchical SM cluster is formed, and each stage of SM core only keeps cache consistency with a lower stage of SM core directly controlled by the SM core; data of an external storage module enters a scheduling core through an L2 cache, and the scheduling core splits the data into thread bundles and dynamically allocates the thread bundles to a target SM core; when the thread processing demand of the target SM core exceeds the current capacity, starting a lower-level SM core according to a preset hierarchy rule, and expanding the processing capacity step by step; and skipping an unprocessed thread bundle over the current SM core through a thread bundle scheduler, splitting the unprocessed thread bundle, transmitting the split unprocessed thread bundle to a lower-level SM core, and merging calculation results of the lower-level SM core step by step through a shared memory. According to the invention, extra resources allocated by the system can be reduced, and the whole system is more efficient and ordered on the basis of ensuring consistency.

Technology for a hybrid memory system that allows host access both non-volatile storage and volatile memory (e.g., RAM). The hybrid memory system may send a command to the host requesting that the host select a mode of access that may include a first mode in which the host has access to only the volatile memory and a second mode in which the host has access to at least the non-volatile storage. While in a mode in which the host has access to the volatile memory, the hybrid memory system may analyze data packets received from the host to determine whether a data packet is a request to access the volatile memory or the non-volatile storage. Responsive to a determination that the host is seeking access to the volatile memory the hybrid memory system converts the packet from the host to a packet suitable to access the volatile memory.

The invention discloses a distributed caching method and system and an acceleration method for large model reasoning service. The system comprises a confidential virtual machine cluster, a zero-trust distributed caching system and a FUSE client. The zero-trust distributed cache system comprises a data strategy service, a data engine plug-in, a distributed file system and a trusted access service. And the FUSE client is deployed at the confidential container end, and establishes secure connection with the trusted access service based on the remote proof and the identity legality confirmation proof of the corresponding confidential container so as to provide a plaintext data access service for the corresponding confidential container. According to the scheme, a distributed cache implementation scheme is provided for the confidential computing container cluster, and the problem of performance loss caused by repeatedly reading, encrypting and decrypting the same data from an external storage system is avoided while the data security is guaranteed by using the large-scale confidential container cluster; and the storage access efficiency in scenes such as model training and reasoning is improved.

The invention relates to the technical field of data processing, in particular to a mobile terminal data intelligent backup method and device, a mobile terminal and a storage medium. The mobile terminal data intelligent backup method comprises the steps that when a preset triggering condition is monitored, such as an NFC label approaching event and / or at least one additional triggering condition, safety verification is executed, and a backup task is triggered if verification is passed. Wherein the NFC label is only used for waking up the backup application program of the mobile terminal. And after a backup task triggering instruction is received, writing the to-be-backed-up data into the external storage device successfully connected with the mobile terminal according to the intelligent backup strategy. According to the data backup method and device, intelligent triggering is achieved through the NFC near field sensing characteristic, the expansion requirement of the external storage device is considered, backup can be conducted according to the intelligent backup strategy, the personalized backup requirement under the complex scene is met, and the convenience and applicability of data backup are improved.

The invention provides an instruction cache and a prefetching method thereof. The instruction cache comprises a hit detection module, an instruction prefetching module and an operation module. The hit detection module checks whether a current instruction fetching request of a current thread bundle is hit. The instruction prefetching module dynamically determines an instruction prefetching range corresponding to the current instruction fetching request according to the execution progress of the current thread bundle. The operation module accesses the external storage to prefetch the instruction data corresponding to the instruction prefetch range. And in response to the fact that the hit detection module judges that the current instruction fetching request is hit, the operation module feeds back instruction data corresponding to the current instruction fetching request to the current thread bundle. And in response to the fact that the hit detection module judges that the current instruction fetching request is missed, the operation module accesses external storage so as to feed back instruction data corresponding to the current instruction fetching request to the current thread bundle.

A data processing method and apparatus, and a computing device. The method is executed by a data processing system, after obtaining cache data, when determining that the cache data volume of the cache data is greater than the available memory space capacity of the memory of a locally deployed server cluster, the data processing system can automatically spill out part of the cache data into an external memory, so as to prevent the data processing system from frequently reporting OOM errors, thereby improving the stability of the data processing system.

The invention discloses a restart control method and device of a server processor, a storage medium and electronic equipment, and relates to the field of servers, and the method comprises the following steps: detecting the running state of the server processor, and storing a recovery file for the server processor according to the running state of the server processor, then the server processor is controlled to recognize the first controller as an external storage medium, and then the server processor is controlled to restart the external storage medium as a starting item which is preferentially executed in the starting process, so that the server processor can directly obtain a recovery file from the first controller when needing to be restarted; the executive program contained in the recovery file can guide the temporary operating system after the server processor is restarted, and the temporary operating system can provide an operating environment required by system recovery for the server processor, so that the technical problems of poor restarting reliability and the like of the server processor are solved; the technical effect of improving the restart reliability of the server processor is achieved.

The invention discloses a fault recording method and device, an inverter and energy storage equipment, and the fault recording method comprises the steps: controlling a write-in position pointer in a temporary fault buffer area to carry out index number self-increasing in a fault recording process when the execution frequency of an interruption control period reaches a fault recording condition and timestamp information is received, determining a residual wave recording space according to the current write-in index number and the current initial index number of the initial position pointer; and when the target equipment has a fault and the residual wave recording space is smaller than a first preset data volume, stopping fault wave recording, and storing the fault wave recording data through an external storage medium. Through the mode, the operation data of the target equipment in each interruption control period is refreshed in the temporary fault buffer area, and the index numbers of the storage data points are continuously updated, so that the data before and after the fault are efficiently and reliably recorded, and the fault analysis is quickly and effectively carried out.

According to the multi-user hierarchical data cloud storage sharing method and system based on secret sharing provided by the invention, storage protection is provided for an encryption key by using a secret sharing mechanism, so that the security of the key can be effectively ensured; different shared user groups and shared data grading contents are set according to different key shares, and attribute encryption can be equivalently realized; the access control server performs processing such as interpolation, slicing and transposition on an external storage key share, so that proxy re-encryption can be efficiently and equivalently realized; the secret key share is simultaneously used for realizing the processes of shared user group setting, shared data grading encryption, shared user and access control server bidirectional authentication, proxy re-encryption and the like, so that password resources are fully utilized. In addition, a key generation center is not needed, the interaction process of roles in the system is reduced, and the working process is simplified; and only simple Hash operation is needed, so that the generation of password resources is quicker, and the calculation is simpler and more efficient.

The utility model relates to an MCU simulation debugger with high-voltage isolation protection. The MCU simulation debugger comprises a USB power supply communication circuit module, a first DC step-down circuit, a DC-DC power isolation module, a second DC step-down circuit, a main control chip minimum system, a burning code external storage FLASH control circuit, an off-line burning BURN key detection circuit, a JTAG simulation / IIC burning interface isolation module and a three-section dial switch. A dial switch state detection module; and a machine burning control interface. The JTAG simulation / IIC burning interface isolation module realizes 1500Vrms electrical isolation of a debugging board card and simulator equipment, online simulation debugging of resistance product firmware can be realized, and a software developer does not need to care about the electrical isolation condition of the debugging board card and only needs to concentrate on debugging codes; multi-interface and multi-level high-speed simulation and burning are supported, level switching of a debugging board card is rapidly achieved through a dial-up gear, and the level compatibility of the simulator is improved.

The invention provides a computing system, a multi-round session reasoning method and device and a computing device cluster, and belongs to the technical field of cloud computing. In the system, an external storage device stores a historical key value cache of a completed session, and the capacity of the external storage device is far greater than the capacity of an HBM in an accelerator, so that the hit rate of the historical key value cache can be improved, and key value cache re-calculation is avoided; moreover, when the accelerator processes the session, the host can preload the historical key value cache of the session to be processed in the task queue from the external storage device to the memory of the host, and when the accelerator carries out the ith layer calculation on the session, the accelerator can preload the historical key value cache required by the (i + 1) th layer calculation from the memory of the host, the calculation process and the data loading process are synchronously performed, and the calculation process does not need to wait for data loading completion, so that the time overhead of accessing the external storage device by the accelerator can be hidden, and the efficiency of multi-round session reasoning is improved.

The present disclosure discloses a fault recovery method. The method includes: in response to a server being powered on or reset, starting baseboard management controller firmware from one or more flash memories storing the baseboard management controller firmware; in response to a failure of the starting the baseboard management controller firmware from the flash memories, starting a boot loader from a flash memory in which the boot loader is burned; in response to the boot loader being successfully started, obtaining backup baseboard management controller firmware from an external storage device through the boot loader, and burning the backup baseboard management controller firmware to any one of the flash memories; and in response to the burning being completed, resetting the server, and enabling the flash memory to start the backup baseboard management controller firmware from the flash memory in which the backup baseboard management controller firmware is burned.

The invention discloses a compiling optimization device and method supporting Page Attention and a medium, and belongs to the field of compiling optimization devices.The device comprises a multi-core AI accelerator, and each calculation core comprises a tensor component, a vector component, a DMA component and an IMM component; the compiling optimization device is optimized through the following modules: (a) a KV Cache management module, which is used for storing page table items corresponding to different KV Cache blocks according to a batch sequence and generating standardized page table items; (b) a DMA control module which supports a linear reading and remapping mode, carries discrete KV Cache blocks from an external memory to an on-chip weight buffer area in a segmented manner according to an index table, and hides data loading delay by adopting a double-buffer technology; and (c) a multi-batch reasoning scheduling module which dynamically allocates computing resources according to the data scale in a code stage. According to the invention, through deep cooperation of a hardware architecture and functional logic, the problems of low KV Cache management efficiency, complex multi-batch dynamic scheduling and insufficient computing resource utilization rate on an ASIC platform are solved.

The invention discloses a ZYNQ series FPGA self-repairing structure based on a self-adaptive redundancy strategy, which comprises a logic end and a processor end, the logic end and the processor end perform signal interaction through an AXI bus, and a PCAP interface is adopted to complete the configuration of the logic end. The logic end is divided into a plurality of logic function areas, and each area comprises three identical function cells and an interconnection cell. And the processor end comprises a self-repairing controller, a fault responder, a read-back refreshing controller and an external memory DDR (Double Data Rate). The invention provides a ZYNQ self-repairing design method based on the structure, functional cells can change redundancy modes according to different radiation environments, detection and repairing of cell-level and molecular-level faults are achieved, reliability and flexibility of operation of a ZYNQ series FPGA system are improved, and therefore the universal ZYNQ self-repairing design method is provided for design and development personnel.

The invention discloses a data search processing method and a host. A host processor obtains a query vector and a centroid of each to-be-searched graph; the to-be-searched graph is constructed for the query scene, so that the number of candidate vectors of the corresponding to-be-searched graph is determined according to the query vector and the centroid; a query request is sent to the hardware accelerator, the query request comprises query vectors and the number of candidate vectors, the hardware accelerator distributes the query request to different search units, and candidate vector search is conducted on the corresponding graphs to be searched in the external storage through the different search units.

A processing system includes a memory controller subsystem connected to a communication channel configured to be connected to an external memory, wherein the communication channel comprises a data signal, and a master circuit is configured to send write and read requests to the memory subsystem. The memory controller subsystem comprises first and second memory controllers. In response to receiving a write request, each memory controller generates a respective first or second communication for storing the respective data to the respective memory address by generating a respective first or second data signal used to transmit the respective memory address and the respective data. Conversely, in response to receiving a read request, each memory controller generates the respective first or second communication for receiving data associated with the respective memory address by generating the respective first or second data signal to transmit the respective memory address and receive the respective data.

The invention discloses a video data transmission method and system based on an FPGA, and relates to data transmission. The method comprises the steps that a video data stream is acquired, and a time sequence signal of the video data stream is analyzed; writing the parallel data into an external memory to form a frame buffer area; packaging the read video data into a data packet meeting a USB3.2 transmission protocol; packaging the data packet based on a USB3.2 link layer protocol; and converting the USB3.2 protocol transmission frame into a differential signal, and transmitting video data in the USB3.2 protocol transmission frame according to the differential signal. In view of data loss caused by mismatching of a video input rate and a USB output rate in the prior art, by establishing an annular buffer structure and adopting a dynamic pointer management and waterline threshold monitoring mechanism, rate adaptive matching of a video data stream is realized, and continuous and stable transmission of video data is ensured.

The present disclosure discloses a fault recovery method. The method includes: in response to a server being powered on or reset, starting baseboard management controller firmware from one or more flash memories storing the baseboard management controller firmware; in response to a failure of the starting the baseboard management controller firmware from the flash memories, starting a boot loader from a flash memory in which the boot loader is burned; in response to the boot loader being successfully started, obtaining backup baseboard management controller firmware from an external storage device through the boot loader, and burning the backup baseboard management controller firmware to any one of the flash memories; and in response to the burning being completed, resetting the server, and enabling the flash memory to start the backup baseboard management controller firmware from the flash memory in which the backup baseboard management controller firmware is burned.

Disclosed are systems, apparatuses, methods, and computer-readable media for configuring network groups without software-based processing and management. A method includes: validating veracity of a secure enclave based on a secure identify of the secure enclave using the instructions of a secure enclave predriver stored in a memory integral to a processor; establishing a secure connection with the secure enclave; retrieving at least one authentication key from the secure enclave; retrieving at least a portion of a bootstrapper from a secure storage based on the instructions of the secure enclave predriver; validating a veracity of the bootstrapper based on the at least one authentication key; initializing an external memory using the instructions of the bootstrapper; copying a bootloader from the secure storage into the external memory; validating a veracity of the bootloader based on the at least one authentication key; and executing the bootloader.

The invention discloses a self-attention mechanism calculation method, a calculation array, a calculation device, a calculation system and a computer readable storage medium. The self-attention mechanism calculation method is applied to a self-attention mechanism calculation array, the self-attention mechanism calculation array comprises a plurality of product accumulators, the plurality of product accumulators form a systolic array, and the self-attention mechanism calculation method comprises the following steps: performing calculation through the plurality of product accumulators according to a feature tensor and a weight tensor to obtain an intermediate tensor; and a result tensor is calculated according to the intermediate tensor through a plurality of product accumulators. Therefore, frequent memory access of the intermediate tensor between the self-attention mechanism calculation array and the external memory is avoided, the calculation efficiency is improved, and the problems of intermediate tensor multiplexing and storage optimization are solved.

The invention discloses a UVM automatic verification method for loading an external memory function on a chip, and belongs to the technical field of integrated circuit design and verification. According to the method, test excitation is divided into configuration information filled by a user and control information automatically generated through a formula to generate a configuration file, the configuration file is read by means of a memory model, data is configured to a specified register after a chip is powered on, and cross-channel data verification is achieved through an analysis module, a driving module and a data checking module. And randomly selecting one node from broadcast nodes for a register configured by the broadcast, and reading back data for comparison. According to the method, the limitation of single-link verification is broken through, a closed loop of configuration generation-simulation execution-cross-channel verification is formed, end-to-end automatic verification is realized, verification efficiency and reliability are improved, manual configuration errors are reduced, abnormity is accurately positioned in real time, and verification completeness and efficiency are balanced.

There is provided a method for providing a service by an artificial intelligence(AI) agent with a multi-turn. A cost for performing tasks of an AI agent is reduced and a speed of performing the tasks is improved by maintaining only messages for the most recent j turns as originals and using summary message for each of messages of previous turns of the most recent j turns. Further, a risk of information loss in a multi-turn of the AI agent is eliminated by storing original messages corresponding to the summary messages in an external storage and thus allowing the original messages to be accessed when necessary.

The present application belongs to the technical field of cloud computing and provides a computing system, a multi-round session inference method, an apparatus and a computing device cluster. In the system, an external storage device stores a historical key value cache of a completed session. As the capacity of the external storage device is far greater than the capacity of an HBM in an accelerator, the hit rate of the historical key value cache can be increased, thereby avoiding recomputing the key value cache. In addition, when the accelerator processes a session, a host can preload a historical key value cache of a session to be processed in a task queue from the external storage device to an internal memory of the host; when performing i-th layer computing on the session, the accelerator can preload from the internal memory of the host the historical key value cache required for the (i+1)-th layer computing. As the computing process and the data loading process are synchronously performed, the computing process does not need to wait for the completion of data loading, such that the time overheads of the accelerator accessing the external storage device can be hidden, improving the efficiency of multi-round session inference.

The present application provides a storage space allocation method and a server. The method is applied to a server. Upon reception of a configuration request, the server registers the external storage of a server cluster into the storage space of the server cluster on the basis of the configuration request to obtain a target storage space, thereby realizing capacity expansion of the storage space of the server cluster by using the external storage of the server cluster. Upon reception of a storage space allocation request, the server uses the target storage space to provide a corresponding storage space, so as to store a temporary file generated in the process of realizing a service function. In the method provided by the present application, the external storage of a server cluster is used to realize expansion of storage resources of the server cluster, and the internal storage and external storage of the server cluster can be invoked to provide a storage space for a computing node, thereby effectively supporting the realization of a service function, improving the success rate of task execution, and avoiding task execution failure due to insufficient storage resources.