5203results about "Architecture with single central processing unit" patented technology

The invention relates to the technical field of data processing, in particular to a storage and calculation integrated parallel processing system and method. The method comprises the following steps of obtaining original stored data and performing topological skeleton projection, generating a projection skeleton structure to realize characteristic hierarchical integration, determining a weight relation matrix based on multi-scale space fusion data, realizing matching of a memory and a calculation unit through gradient optimization adjustment, and obtaining a multi-scale space fusion matrix. And the mining storage and calculation unit activates the chain type interaction relationship of the mapping data and performs recursive self-calibration, generates self-calibration update data, predicts a heterogeneous access channel and reconstructs a data access link, and finally performs task recombination and pipeline scheduling and eliminates parallel conflicts, thereby obtaining an efficient parallel processing result. According to the method, high efficiency and intelligentization of storage and calculation are realized, and reliable support is provided for execution of complex calculation tasks.

The invention belongs to the technical field of artificial intelligence chip acceleration, and provides an acceleration method for an expert hybrid model to execute an operation task and related equipment. The method comprises the steps that a to-be-processed operation task is acquired, a target expert network used for executing the to-be-processed operation task in an expert hybrid model is determined, and network parameters of all first expert networks in the expert hybrid model are stored in an on-chip memory of an accelerator chip, network parameters of each second expert network in the expert hybrid model are stored in an off-chip memory of the accelerator chip; calling a first network parameter of a first expert network in the target expert network from the on-chip memory, and calling a second network parameter of a second expert network in the target expert network from the off-chip memory; and executing the to-be-processed operation task through a target expert network in the expert hybrid model based on the first network parameter and the second network parameter. Through the technical scheme provided by the invention, the acceleration efficiency of executing the operation task by the expert hybrid model can be improved.

The invention provides a many-core cache consistency system, a many-core cache consistency method, electronic equipment, a storage medium and a product, and the system is based on a network-on-chip architecture, and a plurality of nodes, corresponding routers and distributed directories deployed in the routers are introduced. Each node comprises one or more processor cores and a distributed last-stage cache, and a memory address is divided into a plurality of address blocks and is associated with the distributed last-stage cache through a dynamic address mapping rule. The distributed directories and the distributed last-stage caches are in one-to-one correspondence and used for recording the states of cache lines, the router is responsible for receiving and responding to requests from local or remote nodes, querying the distributed directories and updating the states of the cache lines, and efficient management of cache consistency is achieved. The technical scheme belongs to the technical field of communication, effectively solves the problems of high load and communication delay of a main node in a traditional cache consistency protocol, and improves data consistency and access efficiency in a multiprocessor system and a large-scale parallel computing environment.

The invention relates to the technical field of microprocessors, and discloses a safety debugging method of an embedded microprocessor and the embedded microprocessor, the method comprises the following steps: implanting a random module in the microprocessor, constructing a resistance network array through random distribution of silicon substrate lattice defects to generate a disordered sequence, and if microprocessor data access is carried out, starting the random module; if physical intrusion is detected, a debugging session is established, three types of physical characteristics are synchronously generated to construct a composite key, a triple dynamic confusion layer is constructed in the microprocessor, the dynamic confusion layer and the composite key construct physical logic linkage protection, a probe access instruction logic address is called, if physical intrusion is detected, a probe triggers an invisible check point, and the probe accesses the invisible check point. The integrity of an execution environment is verified, if abnormal debugging is detected, a hardware defense mechanism is triggered, an access attack model is established, confusion parameters are trained and optimized, and a module interconnection mode is changed, so that the learning cycle of an attacker is broken, and the risk of attacking a processor in a machine learning mode is reduced.

The invention discloses an image processing data analysis platform based on a memristor storage and calculation integrated architecture, and relates to the technical field of data identification, and the platform comprises an XC7Z020 FPGA control module which is connected with an OV5640 camera image acquisition module, a memristor array calculation module and an Internet of Things module. According to the image processing data analysis platform based on the memristor storage and calculation integrated architecture, through deep fusion of the memristor storage and calculation integrated architecture and a dynamic optimization technology, the speed, energy efficiency and reliability of image processing are remarkably improved. The data handling bottleneck of the traditional von Neumann architecture is eliminated, the processing speed is improved compared with that of the traditional GPU scheme, and meanwhile, the system energy consumption is reduced. Weight distribution and fragmentation processing strategies are adjusted through real-time feature feedback, so that the recognition accuracy in a complex industrial scene is improved, the throughput is broken through, and the real-time processing requirement of a high-resolution image is met.

The invention discloses an RFSOC-based FAST core array distributed collaborative observation and data fusion method and system, and the method comprises the steps: S1, system initialization: a master node RFSOC generates a global clock, achieves the phase synchronization of multiple board cards through an SYSREF differential signal, and completes the calibration of a three-stage clock tree; s2, signal acquisition and preprocessing: directly sampling a 3-8GHz radio frequency signal through an ADC (Analog to Digital Converter), and performing digital down-conversion to obtain a baseband signal; s3, intelligent resource scheduling: identifying a signal type based on an ESN (Echo State Neural Network), and dynamically allocating FPGA logic resources through an improved ant colony algorithm; s4, heterogeneous calculation acceleration: executing a 128-channel digital beam forming pipeline on the FPGA; s5, cross-domain data fusion; s6, collaborative observation planning; and S7, outputting data. The method is suitable for multi-beam synthesis, cross-region joint observation and mass data real-time processing scenes, and provides key technical support for solving the frontier scientific problems such as rapid radio storm origin and black hole activity monitoring.

The invention discloses a FeFET-based XNOR calculation unit, an array and a working method of the FeFET-based XNOR calculation unit. The unit comprises a FeFET transistor F1, a FeFET transistor F2 and an NMOS transistor M0. The source electrode of the F1 is connected to a bit line BL, the source electrode of the F2 is connected to a bit line BLB, the grid electrode of the F2 and the grid electrode of the F1 are jointly connected to a word line WL, and the drain electrode of the F2 and the drain electrode of the F1 are jointly connected to a node X. The grid electrode of the M0 is connected with the node X, the drain electrode is grounded, and the source electrode is connected to the shared charge line Scl. F1 and F2 are configured to store a weight bit, and by applying a read voltage to WL and applying a voltage corresponding to an input bit to BL and BLB, a voltage level of Scl outputs an XNOR logic calculation result. The array includes a plurality of XNOR computing units arranged in m rows * n columns. WL and Scl ends of each unit are shared in each column, and BL and BLB are shared in each row. According to the invention, the control peripheral circuit of the array word line is simplified, the variability of current is effectively avoided, and the problems of hardware overhead and the like are effectively solved.

The invention relates to the field of satellite navigation anti-interference and the technical field of computers, and discloses a multi-processor core communication method and device, electronic equipment and a storage medium, and the method comprises the steps that a second processor core writes target information into a shared memory, and obtains a first idle channel number; the second processor obtains a first interrupt signal based on an interrupt trigger register corresponding to the first idle channel number; the first processor core reads target information in a shared memory according to the first interrupt signal; the first processor core processes the target information to obtain a processing result, and writes the processing result into the shared memory to obtain a second idle channel number; the first processor core obtains a second interrupt signal based on an interrupt trigger register corresponding to the second idle channel number; and the second processor core reads the processing result in the shared memory according to the second interrupt signal, and writes the processing result into the cache region. The multi-processor core communication method is suitable for different operating systems and is high in transportability.

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

The invention relates to an AI computing subsystem, end-side equipment and a control method of the end-side equipment, and the AI computing subsystem comprises at least one FLASH storage chip which is used for pre-storing weight parameters of at least one AI network model; the at least one DRAM storage chip is used for storing weight parameters and activation functions of the AI model; and the logic chip is connected with the FLASH storage chip and the DRAM storage chip, responds to an external instruction, reads data of the FLASH storage chip so as to write the data into the DRAM storage chip, and / or reads weight parameters and activation functions stored in the DRAM storage chip and executes a calculation task. The SoC system only needs to send parameters or start commands of the AI network, and the whole network runs in the AI computing subsystem; and the most complex part of the AI network part can be deployed in the AI computing subsystem, and the SoC system only needs to compute the simple operator of the part, so that the SoC system has larger space to complete other responsible tasks.

The invention discloses an RISC-V chip multi-core heterogeneous design method and system applied to a power grid, and belongs to the field of artificial intelligence chip design. The design method comprises the steps that a power grid task is input, and data exchange and task scheduling are conducted between an AI core and a CPU core in a self-adaptive mode according to the power grid task; according to data exchange and task scheduling requirements, parallel computing is carried out through the special hardware unit and the optimized instruction set; through dynamic power management, the load is monitored and calculated in real time, and the power states of the AI core and the CPU core are dynamically adjusted; a plurality of parallel communication channels are provided through a network-on-chip NOC communication architecture, and a network topology structure is introduced into a chip, so that communication and data transmission among processing units are realized. According to the method, the extension characteristic of an open source instruction set is fully utilized, hardware design and software design are combined, the operational capability is improved, and the problems of bandwidth bottleneck and delay of a traditional bus architecture in a multi-core system are solved.

The invention discloses a large language model accelerator architecture based on a three-dimensional NAND flash memory, and belongs to the technical field of calculation, reckoning or counting. The architecture comprises a three-dimensional NAND flash memory used for executing feedforward neural network calculation; the auxiliary calculation unit is used for executing attention mechanism calculation; the DRAM chip is used for storing attention mechanism related weights and KV cache; and the interconnection resource is used for realizing data interaction among the components. Wherein the three-dimensional NAND flash memory comprises a logic chip and an NAND array chip, the logic chip is used for controlling and executing calculation, and the NAND array chip is used for storing weights and participating in calculation. The invention further provides a scheduling method based on KV cache awareness. The scheduling method comprises decomposition and dynamic allocation of calculation tasks. Through collaborative design of the hardware architecture and the scheduling method, the memory wall bottleneck in large language model calculation can be relieved, the energy consumption is reduced, and the overall calculation performance is improved.

The embodiment of the invention provides a read-write request processing method, a protocol conversion module, electronic equipment and a storage medium, and relates to the technical field of chips. The method comprises the steps that a protocol conversion module is arranged in a processor cluster, an original read-write request is converted into a first read-write request conforming to a CHI protocol through a first conversion module in the protocol conversion module, and a corresponding transmission channel is distributed to the first read-write request; and the request queue module orderly sends the received first read-write request, and the second conversion module recombines the first read-write request information to a second read-write request conforming to the CHI protocol, and allocates a corresponding channel for the second read-write request. According to the embodiment of the invention, the internal data channel (AXI or similar AXI) is directly converted into the CHI interface in the processor cluster, the internal circuit resources of the processor cluster are reused, the circuit area is saved, and the access path time delay is reduced.

The invention discloses a chip design method, system and device based on a multi-core heterogeneous architecture and a medium. The method comprises the steps that the type and number of heterogeneous computing cores are determined according to a target application scene, and a task scheduling unit is configured; designing an on-chip interconnection structure of a heterogeneous computing core by adopting a hybrid topological structure, and verifying and adjusting a dynamic task scheduling strategy and the on-chip interconnection structure through hardware simulation; configuring a power management unit according to the energy efficiency optimization target, wherein the power management unit is used for controlling the working state of the heterogeneous computing core; operating data of the heterogeneous computing core are collected in the post-silicon verification stage, a firmware updating scheme is generated according to the operating data, and firmware updating is conducted according to the firmware updating scheme. By optimizing the chip design process under the multi-core heterogeneous architecture, the performance, the energy efficiency ratio and the reliability of the chip are improved, and the method can be widely applied to the technical field of chip design.

The invention provides a priority resetting method of a cache line and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips, the method comprises the following steps: detecting that a cache group contains a cache line of a first priority state (namely, the priority is greater than a preset level), and in addition, detecting that the cache group contains the cache line of the first priority state (namely, the priority is greater than the preset level); detecting a request state between the processing core and the cache when the target duration (namely the interval duration from the previous access of the data request carrying the priority prompt to the cache group) is greater than the preset duration; when the request state is that the data request sent by the processing core is not detected, spontaneously initiating a priority resetting process, and adjusting the priority of the cache line in the first priority state in the cache group to a preset level; in this way, hardware can automatically reset the priority of the cache line, the situation that the cache line with the high priority occupies the cache space for a long time is avoided, the cache space reserved for non-important data access is improved, the overall performance of the cache is improved, and meanwhile processing of a data request (normal access) of a processing core is not affected.

A queue storage management system under an RDMA network comprises a data management module, a network transmission module, a data storage module and a queue management module which run on an FPGA platform. The data management module is bidirectionally interconnected with the network transmission module, the data storage module and the queue management module respectively; the data management module comprises a main control processing sub-module, a logic control sub-module, a data caching sub-module and a data checking and processing sub-module; the main control processing sub-module is respectively and bidirectionally interconnected with the logic control sub-module, the data caching sub-module and the data checking and processing sub-module, and is used for controlling the overall working logic of the system, including data storage management, scheduling of data transmission, working state control, dynamic allocation of system resources, abnormal state processing and starting of a fault-tolerant mechanism; the method can be more flexibly deployed in various application scenes; for multi-level abstraction of an interface, network layer queue processing and storage layer queue processing are hidden for a user level, a user does not need to care about how to process queues in a data transmission process, and only needs to care about correctness of instruction transmission, so that the system is easy to deploy and use, and has the advantages of high operation efficiency, flexible deployment and high efficiency. And the availability is high.

The embodiment of the invention discloses an inference method and device for a large language model, which are used for reducing bandwidth consumption of inference of the large language model. The method comprises the steps that a parallel reasoning system receives reasoning tasks of a large language model, wherein the reasoning tasks comprise a calculation-intensive task and a self-attention calculation task; the processor executes calculation-intensive tasks, generates intermediate data and sends the intermediate data to the near-memory calculation module, and the calculation-intensive tasks comprise one or more of the following tasks of the large language model: a feedforward neural network calculation task, a projection task and a layer normalization task. And the near memory calculation module executes a self-attention calculation task according to the intermediate data to generate a near memory calculation result. And the processor generates a reasoning result corresponding to the reasoning task based on the proximity calculation result.

The present disclosure relates to a data processing method, a processor, a chip, and an electronic device. The method comprises: on the basis of an obtained control instruction, a control logic unit sequentially reads, from a memory to a dot product unit array, loop tiling data of data to be processed; the dot product unit array performs multiply-accumulate operation on the loop tiling data of the data to be processed that is received each time, and determines a loop tiling result of the data to be processed that is received each time; and on the basis of a plurality of loop tiling results obtained from the dot product unit array, the control logic unit determines a logic operation result of the data to be processed. The embodiments of the present disclosure can convert, into the reading and logic operation of multiple pieces of loop tiling data of the data to be processed, the reading and logic operation of the data to be processed, so that data with larger size can be processed under the condition that the hardware resources of the processor are not changed, and the pressure on the storage bandwidth is reduced.

The invention provides a computing device. The computing device comprises a PCB (Printed Circuit Board), a computing chip and one or more optical modules, the computing chip is arranged on the PCB and comprises one or more input and output high-speed interfaces. Each input / output high-speed interface has one or more input high-speed ports and one or more output high-speed ports. Each output high-speed port performs parallel-serial conversion on a parallel signal in the computing chip to output a first electric signal, and each input high-speed port performs serial-parallel conversion on a received second electric signal serving as a high-speed serial signal. The one or more optical modules are arranged on the PCB, and each port in the electric input and output interface of each optical module is electrically connected with the corresponding input or output high-speed port in the computing chip through wires in the PCB. Each optical module converts the received first electrical signal into a first optical signal and converts the received second optical signal into a second electrical signal.

The invention belongs to the field of machine learning, and discloses an FPGA (Field Programmable Gate Array) superposition processor acceleration system and method based on state space duality, which comprises a sparse predefined data acquirer, a reconfigurable systolic array, a partial sum cache, an element-by-element operation cache, a function calculation module, an on-chip memory management module and the like. Zero elements are eliminated through the sparse predefined data acquirer, redundant data are reduced, and redundant calculation is remarkably reduced; the reconfigurable systolic array flexibly supports multiple calculation modes, and the utilization rate of hardware resources is increased; the part and the cache realize cross-cycle accumulation and element-by-element operation cache integration results, the function calculation module completes nonlinear operation, and the on-chip memory management module optimizes result cache, so that on-chip operation of SSD calculation is ensured, off-chip memory access is remarkably reduced, and reasoning efficiency and energy efficiency are improved; by adopting the system, the memory occupation is effectively reduced, the element-by-element calculation efficiency is improved, and the sparse calculation redundancy is reduced, so that the reasoning process of the Mamba2 model is remarkably accelerated.

The invention discloses a parallel processor dynamic resource allocation system and method based on reconfigurable hardware, and relates to the technical field of computer chips, and the system comprises a workload monitoring module which is responsible for monitoring the workload type and the resource demand of a task processed by a parallel processor in real time, and determining the task type and the resource demand by identifying the task type and the resource demand; a monitoring result is fed back to the resource allocation control module; the resource allocation control module is responsible for generating a corresponding resource allocation control signal based on feedback information of the workload monitoring module and dynamically configuring the reconfigurable hardware module; the reconfigurable hardware module is responsible for realizing efficient adaptation to diversified tasks through a plurality of reconfigurable units formed by programmable logic devices according to different working load dynamic reconfiguration functions and connection modes; and the data caching and transmission module is responsible for cross-module data circulation and global data storage. Different task requirements can be accurately adapted, and the resource utilization rate is improved.

This disclosure describes systems on a chip (SOCs) that prevent trim attempts. The SOCs include one-time programmable (OTP) memory and an engine configured to determine if the one-time programmable (OTP) memory has been trimmed; and if the one-time programmable (OTP) memory has been trimmed, to prevent trimming of the OTP memory.

The invention discloses an in-memory computing array and an operation method thereof, and belongs to the technical field of semiconductors and CMOS hybrid integrated circuits. A 2T1R in-memory computing array based on subthreshold current is designed, each unit in the array is composed of a memristor, a gate tube T1 and a reading tube T2, write-in and erase operations are similar to a 1T1R array architecture, but read-out is carried out through the transistor T2 working in a subthreshold region, the reading current generated by the reading tube is small, and the read-in and erase operations can be carried out through the memristor, the gate tube T1 and the reading tube T2. And the parallelism degree of in-memory calculation is increased, and ultrahigh parallel calculation of 100-1000 orders of magnitude can be realized. And meanwhile, the reading current of the reading tube T2 is in exponential correlation with the gate voltage, so that a larger switching current ratio can be obtained, and a reading window of the in-memory calculation unit is amplified. Compared with a 1T1R array architecture, more complex in-memory calculation operation can be realized, and an operation strategy can be flexibly selected, so that more efficient multiply-accumulate operation is realized.

The invention relates to a final-stage cache design method based on near memory calculation, and belongs to the technical field of near memory calculation. And compared with a near memory processor near a traditional main memory, data access and calculation can be carried out more quickly, and the calculation throughput rate can be improved. According to the near storage calculation, a near storage processor and a last-stage cache storage array are directly designed in an integrated mode, faster memory access is achieved through an internal bus interconnection mode, and the problem of a storage wall between the calculation speed and the memory access speed and the problem of a power consumption wall of data handling are relieved to a certain degree. The last-stage cache controller cooperates with the embedded processor, and can dynamically coordinate between a standard cache function and a calculation mode. Through a synchronization mechanism in a last-stage cache controller, a memory access request from a host CPU and a calculation task executed by an embedded processor in a last-stage cache are transparently balanced, so that efficient near-memory calculation under cache consistency is realized.

Systems and methods for capabilities and interfaces in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node, and where each node is configured to communicate, to the orchestrator, one or more exposed capabilities and one or more exposed interfaces usable to access the one or more exposed capabilities without any involvement by any Operating System (OS) of the IHS.

The invention relates to the technical field of direct current motor servo drive control, and provides a Zynq AXI4 bus-based real-time transmission system and a control method thereof, and the system comprises a Zynq system on chip, a DDR3 common data area, an AXI4 bus interconnection architecture and a dynamic partition manager. By implementing the scheme, firstly, the multi-channel characteristic of the AXI4 bus is utilized, special transmission channels are distributed for different types of data, and parallel data interaction is realized; secondly, a dynamic partition manager is deployed at a PL end, a DDR3 public data area is dynamically divided into a plurality of partitions in real time according to needs, multi-task parallel is achieved, and the real-time performance of the system is improved; thirdly, the read-write operation on the DDR3 in each control period is split into a plurality of state machines through precise scheduling of the state machines, the state machines are combined into a state loop to be mounted to an AXI4 bus, it is ensured that key tasks are completed on time, and the certainty of the system is improved; fourthly, the size and the number of partitions in the DDR3 are dynamically adjusted through a dynamic partition manager, and the storage efficiency is improved.

Provided are systems, methods, and apparatuses for artificial intelligence query processing by processing-near-memory storage. In one or more examples, the systems, devices, and methods include receiving, at a first processing-near-memory (PNM) storage device, data and processing, at the first PNM storage device, first values from the data with transposed query values from the data. In one or more examples, the systems, devices, and methods include determining, at the first PNM storage device, a probability distribution of a result of the processing and generating, at the first PNM storage device, an activation value based on the probability distribution, the activation value indicating a correlation between units of text in a query associated with the data.

The invention discloses an ANN accelerator system based on multi-core storage and calculation integration and a control method, and the system comprises an on-chip network module which serves as an interconnection channel between storage and calculation integration cores and is used for combining calculation results of the multiple storage and calculation integration cores; the synchronous main controller is used for sending an instruction to the decoder according to the process that the network-on-chip module combines the calculation results of the plurality of storage and calculation integrated cores; the decoder is used for receiving an instruction of the synchronous main controller and converting the instruction into a configuration parameter; the configuration register is used for storing configuration parameters and transmitting the configuration parameters to the asynchronous control module, the on-chip routing module and the storage and calculation integrated core; and the asynchronous control module is used for receiving the configuration parameters transmitted by the configuration register and performing time sequence control on the process of merging the calculation results by the network-on-chip module according to the configuration parameters. According to the method, storage and calculation integrated data flow control with reconfigurable parallelism is optimized, and the efficiency of neural network reasoning is greatly improved.

The invention discloses an X-waveband low-cost wave control system and method based on an FPGA, and belongs to the technical field of phased-array antennae, and the system comprises an FPGA module which is used for receiving and analyzing a control instruction from an upper computer, and executing a processing thread of a corresponding mode according to an analysis result; a FLASH module is mounted outside the FPGA module and used for achieving real-time programming curing and reconfiguration of storage parameters, the FPGA module is connected with a plurality of T / R assemblies in parallel through a plurality of data lines, the T / R assemblies on a single data line are mounted in a daisy chain mode, multi-channel data frames are sequentially sent into a first assembly shifting register in a serial mode, and the first assembly shifting register is connected with a second assembly shifting register in parallel. And the first T / R component serially outputs the data frame and transmits the data frame to the next component, and when the data frame shifts into a register of the corresponding T / R component, the data frame is read by controlling a time sequence.

The invention relates to an accelerator and an acceleration method based on Top-K sparse moment vector multiplication. The accelerator comprises a first acceleration unit and a second acceleration unit. The first acceleration unit is used for data preprocessing and sparse matrix coding, and the second acceleration unit is used for executing Top-K sparse matrix vector multiplication so as to solve the process of the first K results with the maximum values in the operation results of multiplication of a sparse matrix and a dense vector; wherein the first acceleration unit comprises a preprocessing module and a coding module; the data preprocessing step of the preprocessing module comprises quantization, sparse reconstruction and shuffling; the broadband demand of data transmission is reduced based on the quantization step of the sparse matrix; pruning non-zero elements which have small influence on sorting based on a sparse reconstruction algorithm; carrying out shuffling operation on the sparse matrix after sparse reconstruction so as to avoid a Top-K aggregation phenomenon; and the coding module is used for recoding the preprocessed sparse matrix. The method has the remarkable effects that the end-to-end performance is improved by 153.3 times, 2.5 times and 3.4 times respectively.