1380results about "Register arrangements" patented technology

The invention provides an optimization method for improving parallelism and performance of hardware executing RISC-V vector instructions, which comprises the following steps: S1, an instruction fetching and decoding stage step: the step comprises an instruction fetching link and a decoding link, and the instruction fetching link reads instructions from a memory according to a program sequence and stores the instructions into an instruction queue; the decoding link comprises the steps of analyzing an instruction, identifying whether the instruction is a vector mask instruction or a vector length control instruction, and if the instruction needs an old value of a destination register, marking that the instruction needs to carry an old value dependency identifier, belonging to the technical field of optimization methods. According to the method, the instruction is transmitted without waiting for the old value of the target vector register to be ready, the instruction can be transmitted in advance after a certain condition is met, and the correct old value is obtained, so that the aim of improving the parallelism and the performance of hardware for executing the RISC-V vector instruction is fulfilled.

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: calling a preset instruction if a current instruction is recognized as an indirect jump instruction; the instruction code of the preset instruction comprises a first operand and a second operand; the first operand points to the first register, and the second operand points to the second register; the target PC value is stored in the first register; the second register is used for storing a calculation result of the preset instruction; the preset instruction executes preset calculation logic to calculate a target index value corresponding to the target PC value in the hash table, and the target index value is written into a second register; the target index value is read from the second register, whether the target PC value hits the hash table or not is inquired through the target index value, and the next instruction is executed based on the inquiry result. According to the embodiment of the invention, the instruction translation number of the high-frequency instruction can be reduced, and the execution efficiency of the binary translator is improved.

The embodiment of the invention provides an instruction processing method and device, a storage medium and an electronic device.The method comprises the steps that a first type of to-be-processed instructions are determined from multiple to-be-processed instructions according to preset instruction codes, and a first vector parameter is updated into a second vector parameter in an updating mode corresponding to the first type of to-be-processed instructions; and splitting a long vector instruction in other to-be-processed instructions into a plurality of micro-operations based on the second vector parameter, and renaming the other to-be-processed instructions according to the plurality of micro-operations, the other to-be-processed instructions being instructions except the first type of to-be-processed instructions in the plurality of to-be-processed instructions. According to the method and the device, the problem that an execution part circuit in a processor is too complex and too large in area and power consumption due to the appearance of a long vector in a vector instruction in the related technology is solved, and the effects of reducing the design complexity of the execution part circuit and realizing better processing frequency in a limited area are achieved.

The invention provides an alarm method of a register chip, a storage medium and an electronic device. According to the alarm method of the register chip, each bit of the register chip corresponds to one kind of alarm information, a to-be-detected target bit can be determined according to to-be-detected information corresponding to the current register chip; therefore, the alarm operation can be executed according to the alarm information corresponding to the target bit under the condition that the target bit is detected to be abnormal. Therefore, the alarm information of the register chip can be flexibly configured through the target bit, all possible conditions can be covered as much as possible, the problem of flexibly configuring the alarm information of the register chip can be solved, the effect of improving the detection accuracy and flexibility of the register chip is achieved, the chip fault detection rate is increased, and the detection efficiency is improved. And the operation stability and accuracy are ensured.

An apparatus for facilitating support of 8-bit floating point format operands in a computing architecture is disclosed. In one embodiment, the apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, where the decoded instruction is a matrix instruction that operates on an 8-bit floating point operand to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for an 8-bit floating point operand according to an 8-bit floating point data format indicated by the decoded instruction; and a pulsation dot product circuit to execute the decoded instruction using pulsation layers, each pulsation layer comprising one or more sets of interconnected multipliers, shifters and adders, each set of multipliers, shifters and adders to generate a dot product of 8-bit floating point operands.

The invention provides a universal measurement and control system data flow control bus architecture method and system, and relates to the technical field of measurement and control, and the method comprises the steps: distributing independent address spaces for a plurality of driving modules through a main control module, building a parameter mapping table and a buffer region, and enabling a plurality of test channels to share an interrupt signal and store the interrupt signal in an interrupt vector register; generating an interrupt signal based on a relationship between the buffer data volume and a threshold; sequencing according to the channel priority reference value, and dynamically adjusting the priority based on the load rate; and the main control module determines an interrupt source according to the interrupt vector and dynamically adjusts a prefetching strategy according to the measurement and control data flow. The system data processing efficiency and the resource utilization rate are improved.

The invention relates to the technical field of processor design and test, and discloses an instruction sequence generation method for verifying floating point operation of a processor, which comprises the following steps: constructing a floating point test coverage model, generating a floating point test database, and constructing a basic RISC-V instruction sequence generator; adding a register updating mechanism bound with a memory on the basis of the basic instruction RISC-V sequence generator, and generating initialized data of the memory; and injecting the generated instruction machine code and the memory initialization data into the memory of the processor to be verified for simulation, and comparing the execution track obtained by simulation with the execution track of the instruction set simulator to find potential errors in the processor. According to the method, an efficient coverage model is constructed to generate representative floating point test data, a floating point data path of the processor can be verified more comprehensively, the defects of an existing method in the aspect of floating points in the RISC-V instruction generation process are overcome, and potential design defects in the processor are found.

The invention discloses a processor, a graphics card, equipment and a resource allocation method and device, and belongs to the technical field of computer resource management. The processor comprises a thread group assembling unit, a thread group scheduling execution unit and at least two processing units, the thread group assembling unit is used for assembling the tasks into one or more thread groups based on the attribute information of the tasks in a task assembling stage; and allocating computing resources for one or more thread groups with the thread group granularity, wherein each thread group is allocated with a processing unit; the thread group scheduling execution unit is used for scheduling one or more thread groups to the processing unit corresponding to each thread group for execution according to a unified scheduling rule, and the unified scheduling rule is a scheduling rule shared by different types of tasks; and the at least two processing units are used for executing the scheduled thread groups. And the computing resources are allocated according to the thread group granularity, so that the execution efficiency of the processor is improved.

The embodiment of the invention discloses a taint analysis method and device, computer equipment and a storage medium, and belongs to the technical field of information security. In the application, the coprocessor of the computer equipment comprises a plurality of registers, and the plurality of registers not only can be used for storing stain information corresponding to a plurality of general registers in a main processor of the computer equipment, but also can be used for storing stain information corresponding to a program memory space of a target program currently executed by the main processor. Therefore, when the coprocessor performs taint propagation on the first instruction, the taint information of the operand of the first instruction can be accessed by accessing the plurality of registers, and compared with the mode of accessing the taint information by accessing a memory, the operation is simpler, the speed is faster, and the performance overhead is smaller.

The embodiment of the invention provides a matrix multiplication and accumulation operation unit and method, a hardware accelerator and electronic equipment, and the matrix multiplication and accumulation operation unit comprises a data loading storage engine, a tensor register file and a matrix multiplication engine. The data loading and storage engine is used for loading data of a plurality of matrixes to be subjected to matrix multiplication and accumulation calculation; the tensor register file is used for storing data of a plurality of matrixes acquired from the data loading storage engine; the tensor register file comprises at least three tensor register groups, each tensor register group comprises a plurality of tensor registers, and different tensor register groups are used for storing data of different matrixes in the plurality of matrixes; and the matrix multiplication engine is used for carrying out matrix multiplication accumulation calculation based on the data of the plurality of matrixes stored in the tensor register file. According to the embodiment of the invention, more efficient MMA calculation is realized under the conditions of low cost, low power consumption and less occupied space.

The embodiment of the invention provides a vector data processor, an instruction processing method, a system on chip and computing equipment, the vector data processor comprises a data access unit and a vector floating point unit, the data access unit comprises a temporary register, and the vector floating point unit comprises a vector register; the data memory access unit is used for responding to a vector memory access instruction, performing memory access of target vector data on a memory and updating a temporary register based on the target vector data, and the vector memory access instruction is obtained by splitting a mask vector memory access instruction; and the vector floating point unit is used for reading the target vector data from the temporary register and writing back the corresponding target element in the target vector data to the vector register based on the mask vector. The hardware design is optimized, the complexity is effectively reduced, the power consumption is controlled, the performance frequency is effectively improved, the area of a vector data processor is reduced, and the innovative scheme provided by the embodiment of the specification can be used for an RISC-V instruction set chip.

The invention provides an instruction execution method, a processor, electronic equipment and a storage medium, the method is applied to the processor, the processor comprises a first execution unit, a second execution unit and a pipeline register, and a first execution instruction of an atomic instruction group is obtained through the first execution unit; writing a first execution result of the first execution instruction into the pipeline register in response to the first execution instruction; a second execution instruction of the atomic instruction group is obtained through the second execution unit, and the first execution result is read from the pipeline register as the source operand of the second execution instruction in response to the second execution instruction, so that the instruction execution method, the processor, the electronic equipment and the storage medium can reduce the access frequency of the general register and improve the access efficiency of the general register. Processor power consumption and register port conflicts can be reduced.

The invention relates to the technical field of artificial intelligence chips, and provides a register resource management method and device, equipment and a storage medium, and the method comprises the steps: obtaining register resource information needed by an operator; based on the register resource information, target register addresses are searched from register resource pools of all the thread bundles, and the target register addresses are register addresses which are the same in address and are not used in the register resource pools of all the thread bundles; and allocating the target register address to the operator, so that each thread bundle shares the target register address when executing the operator. According to the method, through an intelligent register resource searching and distributing mechanism, independent application in the processing logic of each thread bundle is not needed, and only one-time application outside the logic of the thread bundle is needed, so that the requirements of different logic among multiple thread bundles and application of same address register resources can be met, and the expense of register resource application is reduced.

The invention provides an optimization method for sharing one group of physical registers by multiple groups of logic registers, which comprises the following steps: S1, defining a shared physical register file, the step comprises a physical register structure link and a quantity constraint link, the physical register structure link comprises N vector physical registers with VLEN bit width, and the quantity constraint link comprises N vector physical registers with VLEN bit width; each vector physical register can be divided into VLEN / FLEN floating point physical registers; in order to solve the problem of hardware redundancy caused by independence of a floating point register and a vector register in an RISC-V architecture, instruction pipeline sharing of floating point and vector expansion is realized through a scheme that multiple groups of logic registers share a physical register, and the hardware redundancy is avoided. And hardware overhead is reduced.

Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.

The invention discloses an agent method for high-frequency polling of an operating system, electronic equipment and a storage medium, and relates to the technical field of computers, the method is applied to a co-core operating system running at a co-core end of a baseboard management controller, and the method comprises the following steps: responding to a polling agent command generated by a main core operating system running at a main core end of the baseboard management controller; and performing polling on the at least one register to be polled based on the polling agent command, and sending a polling result of each register to be polled and an interrupt signal to the main core operating system so as to wake up the current service process of the main core operating system through the interrupt signal. Therefore, the co-core operating system is used for replacing the main core operating system to carry out high-frequency polling work, and after the main core operating system sends the polling agent command, the current service process is controlled to sleep, so that the problem that a central processing unit is occupied for a long time and cannot process other tasks due to the fact that the main core operating system carries out high-frequency polling is solved; the technical effect of reducing system resource consumption is achieved.

The invention provides an atomic instruction execution method and device, relates to the technical field of computers, and is used for improving the expandability of atomic instructions. The method comprises the steps that an atomic instruction is obtained, the atomic instruction comprises first instruction information, and the first instruction information is used for indicating at least one of an address register, a source register and a destination register; wherein the address register is used for storing an address to be operated, and the source register is used for storing an operand; respectively acquiring the address to be operated and the operand from the address register and the source register according to first instruction information; and executing an atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and storing an obtained execution result in the destination register.

The invention provides a binary translation system applied to an X86 program, which is used for translating a source program following X86 semantics into a target program following other semantics, and comprises a data acquisition module used for acquiring the source program; the disassembling module is used for dividing a source program into a plurality of basic blocks and analyzing subsequent basic blocks corresponding to each basic block; the backward data flow analysis module is used for sequentially analyzing each instruction in each basic block from back to front so as to obtain a target definition set and a target subsequent use set corresponding to each instruction in the source program; and the translation module is used for eliminating redundant instructions of high-order zero clearing or high-order retention of the general register generated in translation. According to the technical scheme, the register state of the general register corresponding to each instruction of the source program is analyzed through the backward data flow analysis module so as to eliminate redundant instructions generated in the translation process.

The embodiment of the invention provides a processor random verification program generation method and device, equipment and a storage medium, and the method comprises the steps: generating a target processing instruction for a target instruction which may generate an unpredictable execution result during loop execution in a loop instruction sequence; inserting the target processing instruction into a specified position in the loop instruction sequence; the target processing instruction is used for processing an operand in a source register of the target instruction before the target instruction is executed in each cycle execution process, so that the target instruction generates a predictable execution result in the cycle process. Thus, the execution result of the target instruction in the loop instruction sequence can be predicted, it is not needed to avoid the instruction with the execution result unpredictable in the instruction sequence, the instruction types in the loop instruction sequence are enriched, the verification efficiency of the microprocessor is improved, and the verification efficiency of the microprocessor is improved. And the quality of the random verification program and the convergence speed of the function verification coverage rate are improved.

The invention provides a processor program address buffering method and device, and belongs to the technical field of processors, and the processor program address buffering device comprises the following components: an instruction fetching unit, a program address comparison unit, a program address buffer area, a program address buffer area tail value register, an instruction transmitting and executing unit and a reordering buffer area; the instruction fetching unit is in control connection with the program address comparison unit, and the program address comparison unit is in control connection with the program address buffer area, the program address buffer area tail value register, the instruction transmitting and executing unit and the reordering buffer area. In order to solve the problem that the disadvantage of the method is obvious in design iteration of instruction fetching and decoding width increasing and assembly line stage increasing of the superscalar processor, the invention provides a judgment basis for whether a program address is written into a program address buffer area or not through a program address comparison unit; the program addresses of all instructions are not written into the program address buffer area, so that the number of implementation table entries of the program address buffer area can be smaller.

The invention relates to a data processing device and method, a processor and a chip, and relates to the technical field of computers, the data processing device comprises a processing module and a driving module; the processing module obtains address information of each thread in a first instruction when judging that the instruction to be processed is the first instruction, the first instruction is a multi-thread parallel loading instruction, and the address information of different threads is mutually independent; the driving module determines a parallel loading result according to address information of each thread in the first instruction, the address information is used for determining an off-chip address and an on-chip address of each thread, and the thread is used for loading data at a position indicated by the off-chip address to a position indicated by the on-chip address. According to the embodiment of the invention, multi-thread parallel execution of different data accesses can be realized, and the calculation efficiency is remarkably improved.

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

The invention discloses a sparse polynomial multiplication accelerator circuit applied to an HQC algorithm, and belongs to the field of post quantum cryptography algorithm hardware acceleration. Comprising a sparse polynomial non-zero coefficient index register set, a state register set, a multiplication and addition unit, a control state machine and an address generation module. The sparse polynomial non-zero coefficient index register set is used for storing indexes of sparse polynomial non-zero coefficients and providing the indexes for the control state machine, and the control state machine further inputs the obtained indexes to the address generation module; the state register group is used for configuring and representing the working state of the accelerator, storing information of registers and providing information for the address generation module and the control state machine; the address generation module is used for calculating address information and feeding back a result to the control state machine; and the control state machine reads the coefficient of the dense polynomial from the external RAM and inputs the coefficient into the multiplication and addition unit for calculation, and after the multiplication and addition unit completes calculation, the control state machine writes a calculation result into the external RAM.

Provided in the embodiments of the present disclosure are a matrix multiply accumulation (MMA) operation unit and operation method, and a hardware accelerator and an electronic device. The MMA operation unit comprises a data load / store engine, a tensor register file and a matrix multiplication engine, wherein the data load / store engine is used for loading data of a plurality of matrixes to be subjected to MMA computation; the tensor register file is used for storing the data of the plurality of matrixes that is acquired from the data load / store engine; the tensor register file comprises at least three tensor register groups, each tensor register group comprising a plurality of tensor registers, and different tensor register groups being used for storing data of different matrixes among the plurality of matrixes; and the matrix multiplication engine is used for performing MMA computation on the basis of the data of the plurality of matrixes that is stored in the tensor register file. By means of the embodiments of the present disclosure, more efficient MMA computation is realized with low cost, low power consumption and a smaller footprint.

The invention provides a communication method of a TPM (Trusted Platform Module), the TPM, a single board and equipment, and is applied to the technical field of computers, the TPM comprises a TPM logic module, a receiving buffer, a TPM register and a processor, and the TPM register is a storage space divided from a memory of the TPM. The TPM logic module receives a TPM register write command sent by the host and stores the effective load of the write command to the receiving buffer, and the effective load of the TPM register write command is part of or all of the content forming TPM command data; when the data in the receiving buffer reaches a first data volume threshold value, the processor transfers and stores the data in the receiving buffer into a TPM (Trusted Platform Module) register; when all contents of the TPM command data are stored in the TPM register, the processor executes the TPM command data. The problem that TPM hardware cost is high due to the fact that a pure hardware scheme is adopted in TPM communication in the related technology can be solved.

The embodiment of the invention provides a data processing method and device, a storage medium and electronic equipment, and relates to the technical field of computers, and the device comprises a data filling module which is used for carrying out data filling on received first data to obtain second data; splitting the second data to obtain at least one block message; the message word extension module is used for performing message word extension on each block message to obtain a message word for compression calculation; the compression function module is used for performing compression calculation on the message word to obtain a calculation result; the compression function module adopts an assembly line calculation framework formed based on a compressor and a working variable register, calculation variables required by compression calculation are stored in the compression function module, and the calculation variables change along with the change of the round number. In this way, the problem that in the prior art, a cryptographic chip is low in large-scale data safety calculation efficiency is solved through a pipeline calculation architecture, and the data calculation efficiency is improved in combination with the pre-stored calculation variables.

A method for processing a tensor is described including obtaining a first register for a number of items in the tensor. One or more second registers for a number of items in a first and a second axis of the tensor are obtained. A stride in the first and the second axis is obtained A next item in the tensor is obtained using the stride in the first axis and a first offset register, when the first register indicates the tensor has additional items to process and the second registers indicate the next item resides in the first axis. A next item in the tensor is obtained using the stride in the first axis and the second axis, the first offset register, and a second offset register. The first register and a second register is modified. The first and the second offset registers are modified.

The invention discloses a register control method, a processor, a system on chip and computing equipment. The method comprises the steps that in the process that a first process accesses a target register, in response to a processor, the first process is switched into a second process, the first state of the target register is obtained, and the target register is allowed to be accessed by a plurality of processes; under the condition that the first state meets a first preset state, storing the value of the target register into a target storage space; in response to the processor, switching the second process back to the first process, and obtaining a second state of the target register; and under the condition that the second state meets a second preset state, recovering the target register based on the data stored in the target storage space. According to the method and the device, the technical problems that the processing overhead of the processor is relatively high when the corresponding register needs to be updated during process switching of the processor in the related technology, and the process which needs to be realized by a processor hardware manufacturer in advance is relatively complex, time-consuming and relatively high in cost are solved.

A method is described herein. The method generally includes receiving stream parameters that defines an array, wherein the stream parameters include a first null element count and a second null element count. The method generally includes forming a stream of vectors for the multidimensional array responsive to the stream parameters. The stream of vectors generally includes a vector of null elements at a beginning of the stream of vectors based on the first null element count. The stream of vectors generally includes a null element at a beginning of each vector of the stream of vectors based on the second null element count. The stream of vectors generally includes a set of data distributed across a subset of the stream of vectors. The method generally includes providing the stream of vectors.