500results about "Handling data according to predetermined rules" patented technology

The invention discloses a matrix transposition method of a DDR3 read-write controller based on an AXI4 bus. The matrix transposition method solves the problems that an existing transposition method is low in data access efficiency, serious in storage resource waste and poor in system portability. The method comprises the following steps: dividing an original echo matrix into a plurality of sub-matrix blocks, mapping and storing the sub-matrix blocks into a Bank of DDR3 to obtain a three-dimensional mapping result; reading data in each sub-matrix block in the three-dimensional mapping result by utilizing a DDR3 read control module, and writing the read data into an RAM (Random Access Memory) of an FPGA (Field Programmable Gate Array) to obtain a transposed matrix; writing the transposed matrix into the original Bank of the DDR3 by using a DDR3 write control module to obtain the DDR3 in which the data is written; according to the invention, low on-chip storage resource occupation independent of matrix scale is realized, and high-efficiency processing requirements of large-scale echo data in satellite-borne SAR real-time imaging processing are better met.

According to one aspect of the present disclosure, a decoder is provided. The decoder may include a cache module. The cache module may be configured to cache soft data related to a codeword to be decoded. The decoder may include a flip-indication module. The flip-indication module may be configured to obtain the soft data from the cache module. The flip-indication module may be configured to, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration and with assistance of the soft data, a number of parity checks not satisfied by bits in the codeword to be decoded.

According to the asynchronous CIOS modular multiplication algorithm and the asynchronous modular multiplication architecture, three small cycles of j in the CIOS modular multiplication algorithm are combined, data temporary storage of the first two small cycles of j is omitted, calculation of the third small cycle of j is fused in a second-stage pipeline after calculation of the second small cycle of j, and two stages of pipelines are formed; after the first round of calculation is executed on the first small cycle of the j, the first round of calculation is started on the second small cycle of the j, assignment on the third small cycle of the j is completed, meanwhile, the second round of calculation is started on the first small cycle of the j, and so on; and in the CIOS modular multiplication algorithm, parallel computing is completed on an assembly line for large loop internal computing of i through an asynchronous circuit. The asynchronous micro-pipeline comprises three basic structures, namely, an FIFO (First In First Out) structure, a Fork structure and a Merge structure. According to the method, loops of the CIOS modular multiplication algorithm are combined, pipeline parallel computing of large loop internal computing is achieved through an asynchronous circuit, the computing area is reduced, and meanwhile the computing speed is increased.

The invention provides a shared cache control system for a high-performance switch. The shared cache control system comprises a plurality of port modules, a plurality of memory allocation modules, a plurality of memory recovery modules, a dynamic channel allocation module and an SRAM (Static Random Access Memory) array, the dynamic channel distribution module is used for cross communication among the port module, the memory distribution module, the memory recovery module and the SRAM array; the port module is used for receiving and transmitting data packets, scheduling other modules to work and performing read-write operation on addresses in the SRAM array; the memory allocation module is used for allocating a memory space address for the data packet and recording an idle state or an occupied state of an SRAM address space by adopting a vector mapping mechanism; and the recovery module is used for requesting the destination port to read the data packet and recovering the memory address space corresponding to the read data packet. The method has the beneficial effect that the switching rate of the shared cache type switch is improved.

The invention provides a complex operation lightweight architecture and method based on an FPGA, the architecture comprises a main scheduling module, a calculation module and a floating point operator module, the calculation module comprises a storage unit and a calculation unit, the storage unit obtains and caches input data of a target algorithm, and the main scheduling module carries out the calculation of the target algorithm according to the operation sequence of the target algorithm. The target algorithm is divided into a plurality of calculation steps, and corresponding operation enable signals are generated and transmitted to the calculation unit; the calculation unit obtains target parameters required by calculation steps from the storage unit according to the operation enable signal, obtains floating point operator units required by the calculation steps from the floating point operator module, and executes the calculation steps to determine an operation intermediate result; and storing the operation intermediate result in a storage unit, generating an operation completion signal and transmitting the operation completion signal to a main scheduling module to control the next calculation step until a final operation result is obtained. Therefore, the FPGA architecture with low power consumption and miniaturization is realized.

The invention discloses a data quantification method and system, computer equipment, a medium and a product, and relates to the technical field of large models.The data quantification method comprises the steps that a to-be-quantized numerical value matrix is obtained, and the to-be-quantized numerical value matrix is divided into parallel processing data sets; normalizing each parallel processing data group based on each preset parallel processing unit to obtain each intermediate to-be-quantized value; and determining a quantization scaling factor based on the maximum value in the intermediate to-be-quantized values, and scaling the intermediate to-be-quantized values based on the quantization scaling factor to obtain quantized values, the maximum value being the maximum value of the absolute values in the intermediate to-be-quantized values. According to the technical scheme, the technical problem of how to improve the reasoning speed of the large language model is solved.

The invention relates to the technical field of integrated circuit chips, and discloses a hardware accelerator for realizing attention weighted summation, which comprises a control module, a dynamic random access memory, a ping-pong static random access memory, a data buffer, an input first-in first-out queue module, an output first-in first-out queue module, a processing unit array, an exp module, an adder tree module and a log2 module, according to the hardware accelerator, by designing a special circuit structure, efficient parallel computing can be achieved, memory access delay is reduced, and therefore the computing speed of attention weighted summation is increased.

The present disclosure provides a character recognition model training method and apparatus, a character recognition method and apparatus, a device and a medium, relating to the technical field of artificial intelligence, and specifically to the technical fields of deep learning, image processing and computer vision, which can be applied to scenarios such as character detection and recognition technology. The specific implementing solution is: partitioning an untagged training sample into at least two sub-sample images; dividing the at least two sub-sample images into a first training set and a second training set; where the first training set includes a first sub-sample image with a visible attribute, and the second training set includes a second sub-sample image with an invisible attribute; performing self-supervised training on a to-be-trained encoder by taking the second training set as a tag of the first training set, to obtain a target encoder.

Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

A processing-in-memory (PIM) device may include a plurality of memory banks configured to provide plural groups of weight data, a global buffer configured to provide plural sets of vector data, and a plurality of multiplication / accumulation (MAC) operators configured to perform MAC operations of the plural groups of weigh data and the plural sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

Aspects of the disclosure provide for methods, systems, and apparatuses, including computer-readable storage media, for sparse matrix multiplication. A system for matrix multiplication includes an array of sparse shards. Each sparse shard can be configured to receive an input sub-matrix and an input sub-vector, where the input sub-matrix has a number of non-zero values equal to or less than a predetermined maximum non-zero threshold. The sparse shard can, by a plurality of multiplier circuits, compute one or more products of vector values multiplied with respective non-zero values of the input sub-matrix. The sparse shard can generate, as output to the sparse shard and using the one or more products, a shard output vector that is the product of applying the shard input vector to the shard input matrix.

The invention discloses a data sorting device and method, a chip, electronic equipment and a storage medium, and the device comprises a controller which is used for obtaining a plurality of first data groups; a parity sorting network for sorting the first data set into a second data set; the data selector is used for acquiring a target data group; the controller is used for comparing the target data set with the ith second data set at an interval of N bits to obtain an (i-1) th third data set; when the TopN is sorted, the double-adjustment merging network is used for sorting the (i-1) th third data group into the (i-1) th fourth data group; when i is equal to the number of the plurality of first data groups, taking the (i-1) th fourth data group as a TopN sorting result; and during full sorting, the double-adjustment merging network is used for carrying out iterative merging on the sorted fourth data group to obtain a full sorting result. The method can be compatible with TopN and a dual-tone full-sorting algorithm, and saves computing resources.

The invention discloses a multi-scalar multiplication acceleration method based on resource estimation and a pre-calculation strategy, and provides a systematic solution for the problems of insufficient resource estimation, pre-calculation factor stiffness and low sorting efficiency of a Pippenger algorithm in zero-knowledge proof. A multi-resolution point multiplication table is dynamically generated through a hierarchical displacement pre-calculation strategy, and global memory access delay is remarkably reduced by combining memory layout optimization and asynchronous flow task scheduling of window inner barrel continuous storage. A dynamic resource adaptation mechanism is designed, thread block topology, grid division and sorting algorithm selection are adjusted in real time based on GPU hardware features, and load balancing and cache utilization rate maximization are achieved. Iterative reduction and double temporary bucket strategies are introduced, and data scale is compressed and boundary processing is optimized through multi-round reduction. In the large-scale MSM operation in the block chain and privacy computing field, the computing efficiency and the resource utilization rate can be remarkably improved, and the method is suitable for an elliptic curve cryptography acceleration task.

The present invention relates to a processor designed to optimize memory bandwidth utilization for tensor transpositions in machine learning. An example processor includes an input tensor shift buffer, a staging buffer, and an output tensor shift buffer. The input tensor shift buffer reads an input tensor from input memory and performs multiple cycles of input tensor shifting. The shifted tensor data is then written into the staging buffer. The output tensor shift buffer reads the shifted tensor data from the staging buffer and performs multiple cycles of output tensor shifting. Finally, the result is written to the output memory. This configuration facilitates efficient handling and transformation of tensor data, optimizing the computational processes required in machine learning tasks.

The embodiment of the invention provides a method and a device for determining processing parameters for a rounding multiplication circuit and a modulo multiplication circuit. The method for determining the processing parameters of the rounding multiplication circuit comprises the steps that a low-order transformation matrix used for modular multiplication is obtained, the target modulus of the modular multiplication is k-th power of r, when the low-order transformation matrix is used for applying combined operation to multiplier segments of two multipliers, the operation result shows a low-order partial segment of a product, and the lower-order partial segment of the product is k-th power of r; wherein the multiplier segment is determined by dividing a multiplier into k segments with a cardinal number of r. Secondly, target transformation is conducted on the low-order transformation matrix through a mapping matrix in an inverse diagonal form, a high-order transformation matrix used for rounding multiplication is obtained, rounding multiplication is conducted on a target modulus, and when the high-order transformation matrix is used for applying the combined operation to a multiplier segment, an operation result shows a high-order part segment of a product; the high-order transformation matrix is used as a processing parameter of the rounding multiplication circuit.

Techniques are disclosed involving operand management using a fusion buffer. A processor includes operand management circuitry, where the operand management circuitry includes a fusion buffer, and execution circuitry. In one embodiment, the operand management circuitry is configured to detect a first storage instruction operation that is executable to store operand values usable by one or more consumer instruction operations and store the first storage instruction operation in the fusion buffer. In response to detecting a drop condition associated with the first storage instruction operation, the operand management circuitry is configured to remove the first storage instruction operation from the fusion buffer without forwarding the first storage instruction operation for execution. In response to detecting a buffer vacate condition and not detecting the drop condition the operand management circuitry is configured to forward the first storage instruction operation for execution by the execution circuitry.

A cryptographic operation is protected. The protecting includes performing a matrix transformation operation on a matrix having n rows and n columns, each row forming a respective vector of a first set of ordered vectors. A second set of ordered vectors is generated by shifting values of vectors of the first set of ordered vectors in a first direction, wherein a pitch of a shift applied to a vector of the first set of ordered vectors is based on an order number of the vector of the first set of ordered vectors. A working vector is generated by logically combining vectors of the second set of ordered vectors. A third set of ordered vectors is generated based on the second set of ordered vectors. A fourth set of ordered vectors is generated based on the third set of ordered vectors and the working vector.

The invention relates to the technical field of data processing, and discloses a salt cavern gas storage brine discharging pipeline operation data processing method and system, and the method comprises the steps: periodically receiving a link detection data packet which is transmitted by a collection device and is provided with a transmission timestamp, and recording the arrival time of the link detection data packet; according to the sending timestamp and the arrival time, transmission characteristics of the link detection data packet are analyzed, and the transmission characteristics comprise transmission delay, jitter dispersion and out-of-order conditions; adaptively predicting a time offset pattern based on the transmission characteristics; generating a real-time calibration parameter according to the time migration mode; and receiving an actual data packet, and adjusting the timestamp of the actual data packet by using the real-time calibration parameter. According to the method, the limitation of traditional fixed compensation parameters is overcome, the time alignment precision of pressure and flow data flow is remarkably improved, leakage misinformation caused by time deviation is avoided, and the reliability and the operation and maintenance efficiency of a salt cavern gas storage brine discharging pipeline operation monitoring system are improved.

Methods, systems, and computer program products are provided for encoding feature interactions based on tabular data. An exemplary method includes receiving a dataset in a tabular format including a plurality of rows and a plurality of columns. Each column is indexed to generate a position embedding matrix. Each column is grouped based on at least one tree model to generate a domain embedding matrix. An input vector is generated based on the dataset, the position embedding matrix, and the domain embedding matrix. The input vector is inputted into a first multilayer perceptron (MLP) model to generate a first output vector, which is transposed to generate a transposed vector. The transposed vector is inputted into a second MLP model to generate a second output vector, which is inputted into at least one classifier model to generate at least one prediction.

Embodiments detailed herein relate to matrix operations. In particular, support for a matrix transpose instruction is detailed. In some embodiments, decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to transpose each row of elements of the identified source matrix operand into a corresponding column of the identified destination matrix operand are detailed.

A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.

The invention discloses an optical fiber sensing high-speed data collecting and processing method based on an FPGA. The method comprises the steps that a user side server initializes configuration register information; the ADC module samples the optical fiber sensing signal according to the register information to obtain first signal data; the data processing module performs data processing on the first signal data according to the register information to obtain second signal data; the data caching module caches the second signal data; the client server reads the cache data information through the data state register and reads the second signal data through the PCIE; when the working mode needs to be switched or collection is stopped, the user side server closes working enabling through PCIE, and a cache clearing register is configured to clear cache data. According to the technical scheme provided by the embodiment of the invention, the inside of the FPGA can be automatically switched to the working mode required by the user according to the configuration register and starts to work, so that the flexible switching of the working mode is realized.

A processing system and method related to encryption are provided. The processing system includes multiple computing circuits. A memory stores data. The computing circuit performs a number theoretic transform (NTT) calculation on a polynomial. A matrix multiplication calculation is performed on the polynomial through the NTT calculation. Therefore, the computing efficiency of encryption or decryption can be improved.

The invention discloses a data processing method and device, electronic equipment and a nonvolatile storage medium. The method comprises the following steps: dividing a data matrix to be calculated into a plurality of data blocks with target sizes; data corresponding to the data blocks are allocated to a plurality of stream processors for data reading operation, the data reading operation is used for loading the data from a global memory of the edge computing device to a shared memory, and the data reading and writing efficiency of the shared memory is higher than that of the global memory; and loading the data in the memory block with the preset vector length in the shared memory into a register by taking the preset vector length as a unit, and operating the data loaded into the register by adopting a stream processor to obtain an operation result. The technical problem that the computing efficiency is not high due to the fact that the related technology is limited by the particularity of the memory access and computing rule of the correction operator and the hardware performance of the edge computing equipment cannot be fully exerted is solved.

The invention provides a computing device, system and method, a chip, equipment and a medium. The computing device comprises a reading circuit, a computing circuit, a storage circuit, a control circuit and a plurality of first registers. The at least one first register is configured with task configuration information of the tasks, and the control circuit reads register information corresponding to the tasks one by one according to a preset mode; enabling a first register identified by a currently read register information to output first configuration information to a reading circuit, output second configuration information to a computing circuit, output third configuration information to a storage circuit, and controlling the reading circuit to perform time-sharing data reading according to the first configuration information of each task, and controlling the calculation circuit to perform data operation in a time-sharing manner according to the second configuration information of each task, and controlling the storage circuit to perform data storage in a time-sharing manner according to the third configuration information of each task, so that the resource utilization rate and the calculation efficiency of the calculation device can be improved.

The embodiment of the invention provides a data processing method and device, a processor and computing equipment, and the method achieves the purpose of shuffling any bit of to-be-shuffled data in cooperation with a TBL instruction in a mode of generating a target index sequence for the TBL instruction. Specifically, the shuffling operation of the to-be-shuffled data with different lengths can be realized according to the adjustment of the number of index values in the target index element without being limited by the length of the to-be-shuffled operation, for example, when 8-bit indexes exist in the target index element, the shuffling operation of 64 (8 * 8)-bit to-be-shuffled data can be realized in cooperation with a TBL instruction, and the shuffling efficiency of the to-be-shuffled data is improved. And when 4-bit indexes exist in the target index element, the shuffling operation of 32 (4 * 8)-bit data to be shuffled can be realized in cooperation with the TBL instruction, and the purposes of improving the applicability of the data processing method and meeting the multi-scene data shuffling requirement are achieved.

A method performed by a processor for permuting dimensions of a multi-dimensional tensor is described. The multi-dimensional tensor contains an array of tensor values in three or more dimensions that are stored in a first storage unit. The array of tensor values is transferred from the first storage unit to a second storage unit by reading tensor values from the first storage that are arrayed along a first dimension of the multi-dimensional tensor and writing the corresponding tensor values to the second storage in locations corresponding to a second dimension of the multi-dimensional tensor. The dimensions of the multi-dimensional tensor may be further permuted by a programmable engine within the processor.

The invention provides a floating point data parallel computing method and device based on a vector processor and the vector processor, and the method comprises the steps: carrying out vectorization and parallel absolute value calculation on a plurality of pieces of input floating point data, and dividing each piece of data into different computing intervals according to the calculated absolute value; for data located in different calculation intervals, calculating branches in different intervals are combined, branch differences are uniformly represented through symbol transformation variables, and fitting intermediate variables corresponding to all the data are obtained through uniform vector operation instruction parallel calculation; and performing parallel calculation on the basis of the intermediate variable for fitting to obtain a preliminary result corresponding to each data, and correcting the preliminary result according to a symbol of original input data to output a final calculation result in a vector form. According to the method, the problems of low hardware resource utilization rate and poor calculation efficiency of high-precision floating point function calculation realized by adopting a scalar serial processing mode in the prior art are solved.