20 results about "Bit field" patented technology

The application provides an in-situ purity data automatic detection method and system of a radiopharmaceutical separation device, and relates to the technical field of data processing.The method comprises the following steps: dividing in-situ purity data into multiple folded segments, identifying the anchoring offset relationship between each node relative to the front anchor point and the rear anchor point to construct an anchoring sequence, calculating the response difference and time compression amount of adjacent nodes in each anchoring sequence, identifying the structural offset degree of local signals in the folded segment to obtain a bit segment displacement amount, proportionally reflecting and adjusting each node in the anchoring sequence to construct a reflection node sequence, extracting the end reflection node and the start reflection node of adjacent folded segments, identifying the evolution trend of overall purity change to obtain a purity latent displacement amount, and detecting the in-situ purity data to obtain in-situ purity detection data.The application can realize timely and accurate purity monitoring in the separation device.

The application relates to the solid state disk storage technical field and discloses an NVM solid state disk garbage collection method based on block effective segment bitmap and accelerated retrieval, which comprises the following steps: when a covering write request is received, locating a BS block and a segment to which an old physical page belongs and accumulating segment invalidation counts, and setting a segment level bitmap corresponding bit when the counts reach a threshold value; after garbage collection is triggered, a candidate block set is screened through hardware acceleration logic by traversing the segment level bitmap; comparing a candidate block version stamp with a global submission version, performing full volume verification and migration on corresponding segment physical pages when the versions are consistent, performing sample verification when the versions are inconsistent, and determining whether to migrate according to the result. The application realizes rapid screening and directional verification of garbage collection candidate blocks, reduces the number of mapping table access times, reduces the invalid migration probability, improves the solid state disk garbage collection efficiency, and simultaneously optimizes the overall read-write performance and running stability of the solid state disk in the small block random write and hotspot address covering write scene.

This invention relates to a bus-based data transmission method, apparatus, device, and storage medium. The bus-based data transmission method includes: when a signal edge is detected before the start of a synchronization segment of the next bit time on the bus, acquiring a sampling sequence obtained from multiple samplings, the sampling sequence being used to characterize the quality of the signal edge; determining a target bit synchronization strategy from among several preset bit synchronization strategies based on the sampling sequence, different bit synchronization strategies defining different bit segment adjustment methods; and adjusting a target phase buffer segment of the current bit time for data transmission based on the target bit synchronization strategy, the target phase buffer segment being the interval preceding the synchronization segment. This application evaluates signal quality through the sampling sequence and adopts a corresponding synchronization strategy based on the evaluation result, realizing dynamic adjustment of bit synchronization, effectively reducing synchronization errors caused by noise, and further improving the stability and reliability of data transmission.

The application provides a template-based IPv6 address data processing method and system, and related equipment, the method comprising: obtaining an IPv6 address to be processed and a multi-level identification template, the multi-level identification template comprising a parent level analysis rule, a child level analysis rule, and a prefix association mapping relationship between the parent level analysis rule and the child level analysis rule; determining parent level bit segment data of the IPv6 address based on the parent level analysis rule, and performing query comparison in the prefix association mapping relationship to determine a target prefix association identification; determining a target child level analysis rule from the child level analysis rule according to the target prefix association identification, and then determining child level bit segment data of the IPv6 address and performing mapping query to obtain a target child level identification; and obtaining a structured analysis result of the IPv6 address according to the target child level identification and the target prefix association identification and outputting the result. The application can improve the search, positioning, and troubleshooting efficiency for IPv6 addresses, and reduce the error rate.

Techniques for structuring IP version 6 (IPv6) addresses into bit fields to embed language localization and services information (e.g., and / or other attributes / information) are disclosed. In some embodiments, a system / process / computer program product for structuring IPv6 addresses into bit fields to embed language localization and services information includes allocating a configurable portion of an IP version 6 (IPv6) address for a subnet, wherein the subnet includes information that is associated with a geographical location (geolocation); and determining an attribute for a new session based on the subnet.

Provided is a method for indicating validity of a reference signal transmission occasion, and a user equipment. The method includes: receiving a paging early indication (PEI) of a current paging cycle sent by a network side device. The PEI includes a first bit field and a second bit field. In response to the first bit field being configured to indicate a need to wake up, the second bit field is configured to indicate whether a first reference signal transmission occasion is valid or invalid; or in response to the first bit field being configured to indicate no need to wake up, the second bit field is configured to indicate whether a second reference signal transmission occasion is valid or invalid.

This invention relates to an adaptive optimization method for a state-aware hierarchical storage index structure, belonging to the field of computer storage and data indexing. It consists of a base-layer metadata index table and a hot-layer accelerated index table, both sharing the same contiguous shared data area. An in-band hotness encoding area is constructed using reusable bit fields of existing metadata fields in the base-layer buckets, embedding access hotness information into redundant bit fields of the bucket metadata for in-band encoding. On the query path, a probability sampling method is used to trigger base-layer hotness state updates, reducing the number of atomic writes to shared cache lines in high-frequency access scenarios. A state vector is constructed, and the sampling probability and hot-layer admission threshold are dynamically adjusted accordingly to achieve hot object identification, index promotion, and hierarchical accelerated access. This invention improves the access efficiency and stability of dense hash tables under complex load conditions without requiring the construction of an external counting structure that grows linearly with the bucket size.

The application discloses a vehicle data query method, device and equipment, and relates to the technical field of vehicle data storage and processing. The method comprises the following steps: extracting target sub-information based on time information of vehicle data; the target sub-information comprises date sub-information, time period sub-information, accurate time sub-information and time zone sub-information; storing the encoding of each target sub-information into a corresponding bit segment according to a preset bit segment structure to obtain encoding data of the time information; determining a target mask according to the time dimension of a data query request, reading a target bit segment in the encoding data by using the target mask, and performing data aggregation based on the target bit segment and the data query request. The target mask is used to read the data of the required bit segment, so that the processor overhead can be reduced by avoiding calling a date analysis function; by simultaneously storing the time period, the accurate time and the time zone, the local time dimension / cross-time-zone data aggregation statistics can be simultaneously supported.

Provided are a communication method, a terminal device, and a network device. One example communication method includes: receiving, by a terminal device, a synchronization signal block / physical broadcast channel block (SSB) from a network device, wherein the SSB comprises a first bit field, and the first bit field indicates that the SSB is a non-cell-defined synchronization signal block / physical broadcast channel block (NCD SSB).

This disclosure provides a method, apparatus, and computer device for generating register transfer level (RTL) codes. The method includes: parsing a target document according to a target document format to locate a register mapping table for one or more registers in the target document; traversing the contents of each cell in the register mapping table to parse out the names of one or more registers and one or more addresses associated with each register; for each register, searching at a specified location in the target document based on the register name to locate the register bit field description table corresponding to the register, obtaining the register bit field information by traversing the register bit field description table, and associating the bit field information with the register name; forming a register configuration dictionary based on the register name and the addresses and bit field information associated with each register name; and generating a register configuration file and the corresponding RTL code based on the register configuration dictionary.

The embodiment of the application provides a DCI code stream detection processing method, the current scheduling parameter of the DCI code stream is obtained by carrying out bit field analysis on the DCI code stream;The false detection probability of the DCI code stream is obtained according to the historical scheduling parameter and the current scheduling parameter of the terminal;The DCI code stream with the false detection probability greater than the preset probability threshold is subjected to special scheduling processing, the problem that the terminal service stability and authenticity are poor due to the high false detection rate of the DCI code stream in the related art is solved, and the effect of reducing the false detection rate of the DCI code stream and improving the terminal service stability and authenticity is achieved.

Disclosed are an encoding / decoding method and device, relating to the field of multimedia. The method comprise: dividing 11B7T into three groups, i.e., 5B3T, 3B2T, and 3B2T; using a data pattern of 5 bits to set a feature combination in a specific bit field among 7 symbols to which 11 bits are mapped; using the feature combination of the specific bit field as an identifier to indicate an encoding mode; and at a decoding end, mapping 7 symbols into 11 bits on the basis of the encoding mode indicated by the feature combination of the specific bit field. Thus, a long sequence is divided into a plurality of short sequences, PAM3 encoding / decoding is performed on the plurality of short sequences, and an encoding mode is indicated on the basis of a feature combination of a specific bit field, reducing the complexity of PAM3 encoding / decoding for the long sequence, thereby reducing the circuit implementation complexity of PAM3 encoding / decoding of the long sequence and improving the PAM3 encoding / decoding performance.

Methods and apparatuses for providing an indication of a PUCCH repetition factor within DCI. The apparatus allocates a downlink resource for at least one UE. The downlink resource includes an indication of a PUCCH repetition factor within DCI. The apparatus transmits the downlink resource to the at least one UE. The indication of the PUCCH repetition factor can include a dynamic indication or an implicit indication of the PUCCH repetition factor. The dynamic indication of the PUCCH repetition factor can be indicated in a separate bit field within the DCI. The implicit indication of the PUCCH repetition factor can be based on a time domain resource allocation of an associated PDSCH.

The present disclosure provides a register transfer level encoding generation method, device and computer equipment. The method comprises: parsing a target document according to a target document format to locate a register mapping table of one or more registers in the target document; traversing the content in each unit in the register mapping table to parse to obtain the name of the one or more registers and one or more addresses respectively associated with each register; for each register, searching at a specified position of the target document based on the name of the register to locate a register bit field description table corresponding to the register, obtaining the bit field information of the register by traversing the register bit field description table, and associating the bit field information with the name of the register; forming a register configuration dictionary based on the name of the register and the addresses and bit field information respectively associated with the name of each register; and generating a register configuration file and a corresponding register transfer level encoding based on the register configuration dictionary.

The application discloses an Risc-V architecture trace compression method based on an improved banyan structure and relates to the technical field of computers. The method comprises the following steps: analyzing the trace message type under the RISC-V architecture, disassembling all the trace messages according to internal fields, assembling each field after the disassembly into a byte-level data structure according to the MSEO protocol, each byte containing 6-bit field information and 2-bit MSEO identification; integrating the byte-level data after the disassembly and assembly into a 16-byte standard data structure according to the size of the data volume of different trace messages and the correlation of the transmission sequence, splitting the message exceeding 16 bytes into multi-cycle transmission, and sequentially splicing and filling the message less than 16 bytes; and processing the 16-byte standard data structure by using the improved banyan structure, and simultaneously realizing the aggregation and shift operation of effective data. Through the cooperation of each step, the application realizes the optimization of 25% of the hardware area of the trace module, guarantees that the timing performance of all operation processes meets the standard, and effectively adapts to the application requirements of the RISC-V architecture in the high-performance and low-power consumption scene.

This invention relates to the field of Windows kernel driver technology, specifically to a kernel hardware access driver system based on a signature verification script virtual machine. It includes a driver framework module, a bytecode integrity verification module, a script virtual machine module, and a hardware access primitive module. The bytecode integrity verification module performs a byte-by-byte constant-duration comparison of the message authentication code signature of the loaded bytecode to resist timing side-channeling. The hardware access primitive module, during compilation for the ARM64 architecture, stores a first stub array and a second stub array generated by compiling constant expression functions in a read-only executable section, and directly uses the instruction word bit field as the array subscript index for access. This invention supports hot-swapping of driver functions and dynamic access to any ARM64 system register under the constraints of non-writable and executable memory protection.

This application discloses a data compression method, apparatus, electronic device, and storage medium based on battery inter-charging. The method includes: acquiring raw data from a battery inter-charging scenario; wherein the raw data includes a status flag and a channel flag; determining the status type and status data based on the status flag; encoding the status data into a first target bit of a preset status bit field based on the status type to obtain status bit field data; assigning a value to a second target bit of a preset channel bit field based on the channel flag to obtain channel bit field data; and integrating the status bit field data and the channel bit field data to obtain compressed data. This invention records status information and channel information in bit field format, enabling efficient and lossless compression of various types of data during battery inter-charging, and can be widely applied in the field of data compression technology.

Disclosed are an encoding / decoding method and apparatus, relating to the field of multimedia. The method comprises: dividing 11B7T into four groups, i.e., 3B2T, 3B2T, 3B2T and 2B1T; using data patterns of 2 bits to set a feature combination in specific bit fields of 7 symbols to which 11 bits are mapped, and using the feature combination in the specific bit fields as an identifier to indicate an encoding mode; and at a decoding end, mapping 7 symbols to 11 bits on the basis of the encoding mode indicated by the feature combination in the specific bit fields. Therefore, a long sequence is divided into a plurality of short sequences, PAM3 encoding / decoding is performed on the plurality of short sequences, and an encoding mode is indicated on the basis of a feature combination in specific bit fields, reducing the complexity of PAM3 encoding / decoding of the long sequence, thereby reducing the implementation complexity of circuits for PAM3 encoding / decoding of the long sequence and improving the performance of PAM3 encoding / decoding.