131 results about "Bit field" patented technology

The invention discloses an intelligent article tracking and identification method and system based on an RFID technology, and the method comprises the steps: collecting an environment noise intensity value, and carrying out the statistics of the number of tags in an effective identification range through a tag response signal; inputting the environmental noise intensity value and the tag number into a power regulation and control model, outputting reader-writer transmitting power, and generating a reader-writer transmitting power instruction; counting a collision time slot number, a successful time slot number and an idle time slot number of the label response signal in a preset time window; dynamically adjusting a frame time slot number Q value according to a proportional relation among the collision time slot number, the success time slot number and the free time slot number; and extracting the EPC code of the successfully identified tag, and deleting the predefined fixed bit field data in the EPC code. According to the method, an environment-data-communication three-in-one optimization system is constructed, the dynamic adaptability, the data transmission efficiency and the data reliability are improved, and the recognition success rate in a high-noise scene is improved.

The invention relates to the technical field of data compression, in particular to a ZSTD compression algorithm optimization method based on joint coding and ternary decomposition, and the method comprises the following steps: S1, building a joint frequency table based on the joint distribution of the literal length and the matching length of a previous section, setting a frequency deviation criterion, and dynamically adjusting a low-frequency combination proportion; s2, decomposing the offset value structure into a leading segment, a trailing segment and a middle segment, performing bit width-entropy ratio analysis on the middle segment, and selecting a symbol index or bit stream coding; and S3, entropy discriminant coding is performed on the joint symbol and the offset symbol respectively, and a structure position is mapped synchronously to generate a structured compressed output stream. According to the method, collaborative optimization of frequency self-adaption, redundancy minimization and structured mapping is realized through joint symbol dynamic modeling and offset ternary structure entropy discriminant coding, so that the ZSTD compression efficiency and the coding stability are remarkably improved.

The invention relates to the technical field of communication security, in particular to a satellite signal tamper-proofing method and system.The satellite signal tamper-proofing method comprises the following steps that a current communication data frame is obtained through a satellite orbit number, a real-time position vector and a timestamp, the data frame is input into a Hadamard integral segment algorithm to execute non-equal-length segment block cutting, a segment block index table is generated, and the segment block index table is stored in a database; recording an initial address bit, a segment block length value and an initial weight bit value; according to the method, non-equal-length cutting is carried out on a data frame through a Hadamard integral segment algorithm, a segment block index table is generated, a weight bit value is recorded, sub-keys and XOR parameters are extracted based on a main key group to execute logic rotation, a dynamic jump path is constructed, the association degree of a shielding area is calculated by combining satellite coordinates and timestamps, risk coefficients are quantified, and risk segment blocks are positioned. A dynamic key is called to generate a re-encryption key through dual linear perturbation, local protection is enhanced through byte-by-byte XOR and complement mapping, and a dynamic cutting, path generation, risk perception and key updating closed-loop mechanism is formed.

The embodiment of the invention provides a color setting method, a graphic processing unit and a system on chip. The method applied to GPU user mode driving comprises the steps that under the condition that a rendering preparation instruction is received, a first bit field of a sampling descriptor is set as a first identifier, the first identifier is used for pointing to a preset table located in a memory, and the table is used for storing boundary colors with the color format exceeding the bit number of the sampling descriptor; writing a target color carried in the rendering preparation instruction into the preset table; acquiring a second identifier of the target color in the preset table; and writing a second identifier of the target color in the preset table into a second bit field of the sampling descriptor, and sending the sampling descriptor to GPU hardware, so that the GPU hardware realizes texture boundary color setting according to the sampling descriptor. According to the embodiment of the invention, the storage format and precision of the target color can be expanded, so that the setting of the texture boundary color can be improved, and the user experience is improved.

The embodiment of the invention provides an embedded operation method and system based on preemptive multi-task scheduling, and belongs to the technical field of multi-task scheduling. The method comprises the following steps: initializing a global task priority group, a start-stop bit field group and an execution quality feedback table, and configuring parameters of a time base interrupt source; loading task parameters, and generating a task configuration table; driving each task cycle counter to accumulate through the time base interrupt source, and when the current accumulated value of the cycle counter is matched with the cycle parameter in the task configuration table and the start-stop bit field group is started, generating a ready mark graph; updating the global task priority group, determining a to-be-executed task, and completing task scheduling; and executing the to-be-executed task, calculating a task priority compensation value, and adjusting the priority value of the corresponding task in the global task priority group in the next period based on the task priority compensation value. According to the method, the defect of static scheduling accumulative errors is overcome through a dynamic priority compensation mechanism.

The invention relates to a hardware routing table look-up method based on segmented unified storage. The method comprises the following steps: firstly, acquiring an IPv4 / IPv6 routing prefix, dividing the IPv4 / IPv6 routing prefix into 1-4 address fields according to 32 bits, allocating a unique forward and backward segment identifier for each field, constructing table entries containing the segment identifiers, 32-bit segment data and a next hop, and uniformly storing the table entries into the same TCAM. During table lookup, segmenting an address to be looked up according to the same rule, querying the TCAM from a first segment by taking segment data as a key, and recording a backward segment identifier and a next hop after hit; and if the backward segment identifier is invalid, directly returning to the corresponding next hop, and if the backward segment identifier is valid, continuing query by taking the identifier and the next segment of data as a joint key. And when the table item is not hit or the identification verification fails, selecting the table item with the longest prefix and the valid next hop in the matched section, and returning to the next hop. According to the invention, IPv4 / IPv6 routing table entries can be uniformly stored, the TCAM space utilization rate is improved, and meanwhile, the hardware table look-up efficiency is guaranteed.

The invention discloses a fault processing method and device and a storage medium, and relates to the technical field of digital information transmission, and the method comprises the steps: when a communication link between a first EtherCAT slave station and a previous EtherCAT station is detected to be interrupted, when a message frame in a preset format is received, sending the message frame to a first EtherCAT slave station; judging whether a message index corresponding to the message frame is written into a message initial index register of the first EtherCAT slave station or not; if yes, modifying a circular flag bit field in the message frame from 0 to 1 to obtain a modified circular flag bit field; and the modified message frame is sent to a second EtherCAT slave station, so that the second EtherCAT slave station carries out discarding operation on the message frame based on the modified circular flag bit field, and the second EtherCAT slave station is an EtherCAT slave station which is located at the downstream of the first EtherCAT slave station and has the smallest distance from the first EtherCAT slave station. The technical problem that when link interruption occurs between slave stations in an EtherCAT protocol scene, the message continuously oscillates in a disconnected loop is solved, so that continuous oscillation of the message is prevented, and the stability and reliability of a system are improved.

A technique for transmitting and receiving a configuration message for a phase tracking reference signal, PT-RS, on a radio channel between a radio access node and a radio device is described. The radio channel comprises a plurality of subcarriers in a physical resource block, PRB. A subset of the subcarriers in the PRB is allocated to a demodulation reference signal, DM-RS. As to a method aspect of the technique, the configuration message is transmitted to the radio device. The configuration message comprises a bit field that is indicative of at least one subcarrier allocated to the PT-RS among the subset of subcarriers allocated to the DM-RS.

Techniques for structuring IP version 6 (IPv6) addresses into bit fields to embed language localization and services information (e.g., and / or other attributes / information) are disclosed. In some embodiments, a system / process / computer program product for structuring IPv6 addresses into bit fields to embed language localization and services information includes allocating a configurable portion of an IP version 6 (IPv6) address for a subnet, wherein the subnet includes information that is associated with a geographical location (geolocation); and determining an attribute for a new session based on the subnet.

The invention provides an automatic detection method and system for in-situ purity data of a radiopharmaceutical separation device, and relates to the technical field of data processing.The method comprises the steps that in-situ purity data is divided into a plurality of turning fragments, the anchoring offset relation of all nodes relative to a front anchor point and a rear anchor point is identified, and an anchoring sequence is constructed; calculating a response difference value and a time compression amount of adjacent nodes in each anchoring sequence, identifying a structure offset degree of a local signal in a turning segment, obtaining a bit segment extrusion amount, carrying out proportional reflection trimming on each node in the anchoring sequence, constructing a reflection node sequence, extracting a tail end reflection node and a starting reflection node of the adjacent turning segment, and obtaining a reflection node sequence; and identifying the evolution trend of the overall purity change to obtain the purity migration amount, and detecting the in-situ purity data to obtain in-situ purity detection data. According to the invention, timely and accurate purity monitoring can be realized in the separation device.

A technique for transmitting and receiving a configuration message for a phase tracking reference signal, PT-RS, on a radio channel between a radio access node and a radio device is described. The radio channel comprises a plurality of subcarriers in a physical resource block, PRB. A subset of the subcarriers in the PRB is allocated to a demodulation reference signal, DM-RS. As to a method aspect of the technique, the configuration message is transmitted to the radio device. The configuration message comprises a bit field that is indicative of at least one subcarrier allocated to the PT-RS among the subset of subcarriers allocated to the DM-RS.

Apparatuses, systems, and techniques that implement a unidirectional counter with one-time-programmable memory that prevents the counter from reversing direction. In at least one embodiment, a unidirectional counter is implemented with a base value represented as a binary number and an offset represented as a bit field where each bit represents an equal amount.

Methods, apparatuses, and systems provide MAC CE formats for LTM measurement reporting. In the context of a method, the method includes receiving control information indicative of reference signals, within one or more candidate cells, to monitor for one or more events associated with LTM reporting; providing for one or more measurements of the reference signals in accordance with the control information; identifying an occurrence of at least an event of the one or more events for at least a first candidate cell of the one or more candidate cells; and transmitting a MAC CE comprising an LTM report based on the occurrence of the event, wherein one or more first bit fields of the MAC CE indicate first candidate cell information for the first candidate cell, and wherein a second bit field of the MAC CE indicates second candidate cell information for at least one candidate cell.

The invention relates to the technical field of image processing, and discloses a reversible grayscale method and system based on bit field multichannel fusion coding, a computer readable storage medium and a computer program product. The method comprises the following steps: normalizing an input original RGB (Red, Green and Blue) image to obtain a normalized RGB image; converting the normalized RGB image into a corresponding HSV image, and normalizing an H channel of the HSV image; according to the three-channel data of the HSV image, calculating through a predetermined coding rule to obtain a reversible grayscale image; decoding the reversible grayscale image through a predetermined decoding rule, and restoring the three-channel data of the HSV image; and according to the restored three-channel data of the HSV image, a final RGB image is obtained through conversion. The zero-parameter storage lightweight design is adopted, the computing speed is increased, meanwhile, memory occupation is effectively reduced, high-resolution image processing can be achieved on an embedded platform, and cross-platform transplantation is more flexible.

A bit plane converter and associated methods. In an embodiment, the bit plane converter is configured to receive a first bit plane comprising low-order bits for an array of pixels, and a second bit plane comprising higher-order bits for the pixels. The bit plane converter is configured to perform an interleave process on the pixels to generate bit fields for the pixels by processing low nibbles of a low-order word and the low nibbles of a higher-order word using a lookup table to generate a bitwise interleaved low nibble vector, processing high nibbles of the low-order word and the high nibbles of the higher-order word using the lookup table to generate a bitwise interleaved high nibble vector, and interleaving bytes of the bitwise interleaved low nibble vector with bytes of the bitwise interleaved high nibble vector to generate a bitwise interleaved vector.

The invention discloses a memory access request processing method, a system on chip, a storage medium and a program product, when at least two continuous memory access requests are received, an enable signal of a continuous transmission mode is acquired, and if the enable signal is in a trigger state, bit field fields of physical addresses corresponding to all the memory access requests are acquired; remapping the memory controller identifier in the bit field to a target position; wherein the target position points to the same target memory controller; and routing all the memory access requests to the target memory controller according to the address information of the target position. By adopting the embodiment of the invention, the continuous memory access requests are aggregated to the same memory controller to be processed, so that the switching of the memory controller is reduced, the bandwidth utilization rate is improved, and the control overhead is reduced.

The present application relates to the field of computer network security technology. The present application provides a network packet classification method based on field distribution entropy and coverage difference, including: obtaining a rule set for a network data packet; dividing the rule set into multiple levels, selecting a rule set with a high optimization level as a candidate rule set; traversing multiple bit segments in the candidate rule set and performing a comprehensive score; selecting the best partitioned bit segment based on the comprehensive score and constructing a tuple hash bucket; establishing a hash table based on the actual value length of the best partitioned bit segment, and distributing the rules to the corresponding tuple hash bucket; traversing each tuple hash bucket for judgment and recursive processing; when the rules of all tuple hash buckets are effectively divided, the tuple hash subtree of the current node is constructed, and the process of rolling back to the previous level or completing the construction of the entire tree is completed. The present application addresses the deficiencies of packet classification technology in terms of search efficiency, structural balance, space utilization, and rule update support.

The present invention discloses a sequence encryption method for complex reconstructed keys: a chaotic computing structure is constructed using a set of composite logics to achieve chaotic bit-stream sequence encryption. The present invention schedules computing logic units such as bit extraction logic, bit metabolism logic, and bit reconstruction logic through the chaotic computing structure, and pseudo-randomly reconstructs the source of construction and the source of control segment by segment to construct a regenerated key bit segment sequence of "pseudo-randomly misaligned extraction of the key bit segment source bits that have not been metabolized or re-extraction of the key bit segment source bits that have been metabolized". The core of the present invention is to construct a chaotic computing structure, metabolize the working pool segment by segment during the encryption process, and then use the bit bits in the control source to control the bit extraction logic to extract the bit bits in the construction source for the control source and the construction source carried by the working pool, and pseudo-randomly reconstruct and re-construct the key bit segments. The beneficial effects of the present invention are: adapting to the breakthrough improvement of computing power and providing a set of secure encryption methods with high efficiency, high density, and wide application space.

Methods, systems, and devices for wireless communications are described that provide for a UE to send a request to a network entity that requests transmission of a beam report from the UE, along with an event that triggered the request. To indicate the event that triggered the request, a bit field may be provided with the request in which multiple codepoints are defined for different events, and the UE may select one of the codepoints based on conditions at the UE. Additionally, or alternatively, different beam reporting formats may be defined for different events. In cases where two or more triggering events occur contemporaneously at the UE, the multiple events may be reported together.

The invention relates to the technical field of embedded systems and automatic software generation, in particular to a heterogeneous single-chip microcomputer drive code automatic system and method based on an RISC-V instruction set, and the method comprises the following steps: receiving and analyzing an IP-XACT or JSON format peripheral description file provided by a hardware team; the method comprises the following steps: respectively calling a special parser to process different file formats, accurately extracting register address mapping, bit field definition, clock domain configuration, interrupt number and DMA channel information, constructing a tree-shaped peripheral data model of a cross-heterogeneous SoC, accurately mapping a physical address of a register to an RISC-V virtual address space, defining an interrupt trigger type and a DMA transmission direction, and establishing a tree-shaped peripheral data model of the cross-heterogeneous SoC; a unique hardware identifier is distributed to each peripheral; according to the method, the drive generation intelligence level of the heterogeneous RISC-V single-chip microcomputer can be comprehensively improved, and the key technical bottlenecks that multi-format peripheral description analysis is difficult, high-frequency data transmission is interrupted and lost, DMA configuration is complex and the like are solved.

The present application belongs to the field of data incremental backup and restoration, and particularly relates to a data incremental backup and restoration method based on bit operation. The method comprises the following steps: 1. New backup: allocating a bit value to a new backup task, and matching the bit value with the existing data in the backup library, and using the bit of the repeated data in the matching result and the bit of the new differential data of the backup task; 2. Restoring backup: querying the backup data with the set bit in the backup library according to the bit value of the backup task to restore; 3. Deleting backup: removing the position of the backup data record with the set bit value of the backup task until 0, and then physically deleting. The present application uses a bit field as a carrier for storing the differential version of the backup task, and uses bit operation to process the data storage and extraction task of the backup and restoration process, thereby saving the rapid increase of the storage space occupied by the repeated data in the full backup, and effectively simplifying the logical design cost and physical storage cost of the data backup and restoration.

The disclosure provides a method and a base station device for wireless communication. A RRC signaling having reference signal resource set(s) and second-type bit field(s) is transmitted, each of the second-type bit field(s) for indicating one power offset and corresponding to one of a plurality of indexes related to the reference signal resource set(s), the second-type bit field(s) including only one second-type bit field corresponding to a first index of the indexes. A PHY signaling having a first bit for determining a first reference signal resource set associated to the plurality of indexes is transmitted. Then a first radio signal at a first power value that is only related to power offsets indicated by all second-type bit fields among the second-type bit field(s) that correspond to the first index is received, the first radio signal being Quasi Co-located with one of the reference signal resource set(s).

Embodiments of the present application provide a kind of invalid instruction generation method, device, electronic equipment and storage medium, involve computer technical field, in the method, first instruction coding format is selected from the instruction coding format set corresponding to the preset instruction set architecture;First random code with the fixed bit section total length of first instruction coding format is equal in length;In the case where the first random code is inconsistent with each preset fixed code corresponding to the first instruction coding format, the invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code.The invalid instruction corresponding to the preset instruction architecture can be directly generated in a random manner, which does not comply with the instruction coding format, which helps to improve the efficiency of generating the invalid instruction of the preset instruction set architecture.

A data processing system is provided that includes a processor and a memory. The processor is configured to execute instructions to access a location pointed to by an address pointer. The memory is coupled to the processor and configured to have a plurality of memory portions. A first address pointer for accessing a first portion of the memory includes a type bit field, a tag bit field, and a first address bit field. A second address pointer for accessing a second portion of the memory is configured to have only the type bit field and a second address bit field without the tag bit field. The type bit field is set to a first value for the tagged pointer and a second value for the untagged pointer. In another embodiment, a method is provided for accessing a location in the data processing system.

The application provides an in-situ purity data automatic detection method and system of a radiopharmaceutical separation device, and relates to the technical field of data processing.The method comprises the following steps: dividing in-situ purity data into multiple folded segments, identifying the anchoring offset relationship between each node relative to the front anchor point and the rear anchor point to construct an anchoring sequence, calculating the response difference and time compression amount of adjacent nodes in each anchoring sequence, identifying the structural offset degree of local signals in the folded segment to obtain a bit segment displacement amount, proportionally reflecting and adjusting each node in the anchoring sequence to construct a reflection node sequence, extracting the end reflection node and the start reflection node of adjacent folded segments, identifying the evolution trend of overall purity change to obtain a purity latent displacement amount, and detecting the in-situ purity data to obtain in-situ purity detection data.The application can realize timely and accurate purity monitoring in the separation device.

Embodiments of the present application provide a resource processing method and device, electronic equipment and readable storage medium, in response to the target load sent resource processing request, obtain the target security attribute data corresponding to the to-be-processed resource indicated by the resource processing request; the target security attribute data includes a domain attribute field and a processing permission field; in the case of matching between the domain attribute field and the current execution mode corresponding to the target load, execute the resource processing request; in the case of not matching between the domain attribute field and the current execution mode corresponding to the target load, and the permission bit field in the control state register is the first value, if the processing permission field matches the resource processing operation corresponding to the resource processing request, execute the resource processing request. In this way, the flexible resource processing mode can improve the flexibility of resource processing request processing on the basis of maintaining resource security isolation, so that the system can better adapt to the operation requirements in different scenarios.

A cache-based data checking method, comprising: establishing, in the cache, second predetermined bytes of checking data for every first predetermined bytes of data; in response to data interaction with the cache, performing data checking according to the data involved in the data interaction and the corresponding checking data; through the cache-based data checking method, when data is stored in the cache, checking data is creatively established for data of a certain size, when data is input or output from the cache, data is checked according to the checking data, a checking bit field is added in the system bus, when data is transmitted to other terminals through the system bus, data is also checked according to the corresponding checking data, if data is abnormal, the way and reason of the abnormal data can be accurately located. In some cases, the abnormal data can be compensated through data reloading. The stability of system operation is improved.

The application relates to the solid state disk storage technical field and discloses an NVM solid state disk garbage collection method based on block effective segment bitmap and accelerated retrieval, which comprises the following steps: when a covering write request is received, locating a BS block and a segment to which an old physical page belongs and accumulating segment invalidation counts, and setting a segment level bitmap corresponding bit when the counts reach a threshold value; after garbage collection is triggered, a candidate block set is screened through hardware acceleration logic by traversing the segment level bitmap; comparing a candidate block version stamp with a global submission version, performing full volume verification and migration on corresponding segment physical pages when the versions are consistent, performing sample verification when the versions are inconsistent, and determining whether to migrate according to the result. The application realizes rapid screening and directional verification of garbage collection candidate blocks, reduces the number of mapping table access times, reduces the invalid migration probability, improves the solid state disk garbage collection efficiency, and simultaneously optimizes the overall read-write performance and running stability of the solid state disk in the small block random write and hotspot address covering write scene.

Methods, apparatuses, and systems provide medium access control (MAC) control element (CE) formats for lower-layer triggered mobility (LTM) measurement reporting. In the context of a method, the method includes receiving control information indicative of one or more reference signals, within one or more candidate cells, to monitor for one or more events associated with LTM reporting; providing for one or more measurements of the one or more reference signals in accordance with the control information; identifying, based at least in part on the one or more measurements, an occurrence of at least an event of the one or more events for at least a candidate cell of the one or more candidate cells; and transmitting a MAC CE comprising an LTM report based at least in part on the occurrence of the event, wherein a bit field of the MAC CE identifies at least the candidate cell.

The application discloses a configurable reduction circuit for integer operation in a post-quantum cryptographic algorithm and belongs to the technical field of hardware implementation of cryptographic algorithms. u The configurable reduction circuit receives an 8-bit integer index value, a 24-bit random integer, a 32-bit random integer, a 2-bit security level signal and a 1-bit mode selection signal, selects a corresponding 16-bit intermediate parameter n and an 18-bit intermediate parameter n according to the 2-bit security level signal, selects one of two reduction paths according to the 1-bit mode selection signal, and performs reduction on the 16-bit intermediate parameter n and the 18-bit intermediate parameter n to obtain a 16-bit modular reduction result. u The application can unify the reduction process, construct a shared wide-bit multiplier, and combine bit segment selection and control logic to multiplex the same multiplication calculation resource under different reduction modes, so that the hardware resource consumption and implementation complexity are effectively reduced while the functional correctness is ensured.