8 results about "ACCESS.bus" patented technology

The invention provides a method and a device for relieving voltage sag of an active power distribution network based on two-stage partition. The method comprises the following steps: determining node voltage and line impedance parameters of a bus based on network topology and element parameters of the active power distribution network; constructing an electrical connection matrix based on the line impedance parameters; determining a swing radius index based on the electrical connection matrix and the node voltage; constructing a sensitivity matrix, and combining the swing radius index to construct a lambda matrix; determining an M index according to the lambda matrix, and performing partitioning in combination with the feature boundary to obtain a first partitioning result; performing weighted smoothing on a lambda sequence in the lambda matrix through a kernel smoothing function, and performing partition boundary correction on the first partition result based on the smoothed lambda distribution to obtain a second partition result; and selecting a key node to configure a dynamic voltage restorer DVR according to a second partitioning result, so as to control the dynamic voltage restorer DVR to inject a compensation voltage to an access bus when a voltage sag event occurs, thereby realizing the alleviation of the voltage sag of the active power distribution network.

The invention relates to the technical field of computers, in particular to an SOC cache system and electronic equipment. To-be-processed data is stored in each master device of the SOC cache system; the data splitting module is in signal connection with each main device through each access bus module, and the data splitting module is used for splitting the to-be-processed data into a plurality of data units; the data behavior recognition module is in signal connection with the data splitting module, and the data behavior recognition module is used for performing behavior recognition on the data in each data unit to determine a corresponding data behavior; the cache control module is in signal connection with the data behavior identification module, the main memory and the cache memory, and prefetches corresponding data into the cache memory when the data behavior is read data; and writing the corresponding data into the main memory under the condition that the data behavior is write data. The invention provides the SOC cache system with higher efficiency.

This disclosure provides a data access method, system, device, storage medium, and program product. The data access method includes: receiving a current memory access request; associating the current memory access request with in-transit memory access requests in a preset storage area; in response to a first in-transit memory access request that has an association, establishing an association between the current memory access request and the first in-transit memory access request, and storing the current memory access request as an in-transit memory access request in a free storage space in the preset storage area; in response to receiving read data corresponding to a second in-transit memory access request, returning the read data as the target memory access data for the second in-transit memory access request; obtaining a third in-transit memory access request associated with the second in-transit memory access request based on the association, extracting the target memory access data corresponding to the third in-transit memory access request from the read data, and returning it. This disclosure can effectively reduce the number of memory accesses, improving the utilization rate of the memory access bus bandwidth while reducing system power consumption.

The invention provides an equipment access method and device, and the method comprises the steps: a broadcast end transmits a broadcast frame which carries bus access configuration information and is used for indicating a null event group of an access bus; the access end receives the broadcast frames, selects a null event group from the broadcast frames, and sends a bus access request frame for accessing a bus; and the broadcast end receives the bus access request frame and feeds back a bus access response frame for indicating whether the access end successfully accesses the bus or not. According to the method, rapid and concurrent access of multiple devices to the bus can be realized, and the access efficiency and the concurrent performance of the devices are improved. The application supports an IEEE protocol, such as an IEEE 802.11 be / Wi-Fi 7 / EHT protocol, an IEEE 802.11 bn / UHR / Wi-Fi 8 protocol, an IEEE Integrated mmWave / integrated millimeter wave / IMMW protocol, an IEEE 802.15 / UWB protocol, or an IEEE 802.11 bf / sensor / sensing protocol, and the application also supports an IEEE protocol. The method and the device can also support a star flash / spark link / nearlink / Bluetooth standard protocol.

The invention discloses an address lock structure, a multi-core processor system and electronic equipment, the address lock structure comprises a blocking control module and a centralized processing module, the centralized processing module is used for adding an address access record in an access suspension table according to an address access request; deleting the address access record in the access suspension table according to the access result response; the blocking control module is used for detecting whether conflict records are stored in other access suspension tables or not according to the newly added address access records added in the self access suspension table; if yes, adding an unlocking identifier in the newly-added address access request, and then temporarily storing the newly-added address access request to a self-access blocking area; when it is detected that the access result response hits the unlocking identification of the blocked address access request in the access blocking area, the blocked address access request is sent to the memory access bus, and according to the scheme, data consistency and correctness of the multi-core processor system under the shared memory programming model can be guaranteed, meanwhile, implementation expenses are effectively reduced, and the implementation efficiency is improved. The system performance is improved.

1. The name of the design product: programmable logic controller coupler. 2. The use of the design product: for expanding the capacity of CPU module of distributed PLC, accessing bus type DI / DI / AI / AO and other supporting expansion modules. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view 1.

The application discloses a storage body self-test system and method with extensible programming, which comprises the following steps: a CPU is connected to a configurable storage body test controller through a CPU configuration interface and a configuration bus for bidirectional transmission of configuration instructions and parameters; the configurable storage body test controller is connected to each group of SRAM and ROM through a storage body access bus; test results of the measured storage body are written into a state register through an internal bus, and the state register is connected to a CPU data reading port for output; a fault signal output end of the configurable storage body test controller is connected to an interrupt module, and the interrupt module sends an interrupt request to the CPU; and an ATE test multiplexing interface reserved in the configurable storage body test controller is directly connected to MBIST logic of chip factory test for multiplexing. The method is implemented based on the system. The application has the advantages of simple principle, lower cost, better responsiveness, stronger compatibility, wider application range and the like.

A dynamic power consumption shaping method for a memory controller chip includes: acquiring the channel enable signal vector of the current physical layer interface; extracting the corresponding equivalent admittance matrix based on the enable signal vector; calculating the instantaneous power density characteristic value of the silicon interposer in conjunction with the current operating voltage; statistically analyzing the arrival rate of memory read / write instructions according to a set long clock window and a short clock window respectively, obtaining a long-period moving average reference value and a short-period transient characteristic value, and calculating the statistical deviation; triggering a load burst interrupt signal when the statistical deviation exceeds the value of a hardware threshold register; and, in response to the load burst interrupt signal, forcibly splitting continuous memory access bus transactions exceeding a preset burst length threshold into several sub-transactions, and inserting a programmable number of clock idle cycles between the send enable signals of adjacent sub-transactions to shape continuous current pulses into discontinuous pulses. This method enables fine-grained power consumption shaping during load bursts.