77 results about "ACCESS.bus" patented technology

Route switch packet architecture processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The route switch packet architecture includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

Global access bus architecture includes a master request bus and a slave request bus separated from each other and pipelined. The global access bus architecture includes packet input global access bus software code for flow of data packet information from a flexible input data buffer to an analysis machine, packet data global access bus software code for flow of packet data between a flexible data input bus and a packet manipulator, statistics data global access bus software code for connection of an analysis machine to a packet manipulator, private data global access bus software code for connection of an analysis machine to an internal memory engine, lookup global access bus software code for connection of an analysis machine to an internal memory engine, results global access bus software code for providing flexible access to an external memory, and results global access bus software code for providing flexible access to an external memory.

The invention is applicable to the field of Internet, and provides a service management method and a service management system, and aims at solving the problems that in the prior art, services under a distributed architecture are not managed in a concentrated manner and not high in flexibility. The method comprises the steps of receiving service requests sent by a client via a unified access bus; performing a unified service governance process on the received service requests, and sending service calling requests to a background node according to service governance results; and receiving service responses sent by the background node, and encapsulating the service responses and returning the encapsulated service responses to the clients. According to the technical scheme of the method of the invention, concentrated processing and monitoring of the services are achieved by a service center, a unified interface is provided for the outside, and thus the all service requests interact with service providers of the background node after being processed by the service center in a concentrated manner, reuse and integration of the business are facilitated, and the flexibility of the distributed architecture is enhanced.

A multi-core processor system includes a number of cores, a memory system, and a common access bus. Each core includes a core processor; a dedicated core cache operatively connected to the core processor; and, a core processor rate limiter operatively connected to the dedicated core cache. The memory system includes physical memory; a memory controller connected to the physical memory; and, a dedicated memory cache connected to the memory controller. The common access bus interconnects the cores and the memory system. The core processor rate limiters are configured to constrain the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value.

A high speed access bus interface for a communications network. The interface allows uni-directional transfer of data packets at a fast path processing rate of about 10 gigabits per second. The interface uses a master port and a slave port in a chip to chip data transfer scheme. The master and slave ports may have one or more than one data channel for transferring data packets. The master port includes a clock signal for synchronizing the transfer from the master port to the slave port. The slave may send an asynchronous signal to the master port in order to initiate the master port to stop or stall the pipeline transfer of data packets until space is made available in the slave port buffer. In addition to the clock synchronization, the interface utilizes an enable signal, a start of packet signal, an end of packet signal, an error signal (if necessary), a last valid byte signal, and a parity bit signal to identify, address, each data packet in the data stream. If a processing error occurs, the master port error signal to the slave port also initiates the slave port to disregard the previous data packet. The operating frequency of 50 MHz allows the data packet transfer to exceed 10 gigabits per second.

A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus masters. If two or more of the bus masters issue access requests at the same time, the bus arbitration section preferentially gives access permission to a bus master which gained access permission a number of times less than a set value in the bus arbitration information within the given period, out of the two or more access bus masters.

A computer system includes first and second integrated circuits. The first integrated circuit provides a first input/output bus operating in accordance with a first protocol, such as ISA. The first input/output bus includes a plurality of address and data lines respectively providing address and data information. The second integrated circuit includes a plurality of second functional blocks at least some of which interface to legacy devices. The first integrated circuit includes a host controller circuit, coupled to the first input/output bus and for coupling to a register access bus which includes a register data out and a register data in signal line. The register access bus connects the first and second integrated circuits. The host controller circuit receives address and data information from the input/output bus and serially provides the address and data information to the data out line. A target controller circuit on the second integrated circuit is coupled to the register access bus. The target controller circuit receives the serially provided address and data information and provides the address and data information, over a second representation of the input/output bus, the second representation being at least a subset of the first protocol and including a plurality of internal address lines and a plurality of internal data lines coupled to the second functional blocks. Write operations take place to memory locations in the second integrated circuit from a write operation begun on the first integrated circuit and read operations take place from memory locations in the second integrated circuit for read operations begun on the first integrated circuit.

Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

An simulation device of bus arbitration is prepared as adding a bus arbitrator in simulation model of ARMulator to let operation of access bus on all bus master units including ARM Core pass arbitration of said bus arbitrator first, enabling to make access on bus slave unit and to obtain required return-back value only after bus is obtained.

A multi-services access platform is presented for supporting metallic test access in switching or multiplexing devices such as digital subscriber line access multiplexers (DSLAMs). The multi-services access platform includes a chassis within which a predetermined number of card slots are included. Each of the card slots includes a number of input/output ports. A backplane runs along the chassis and includes a metallic test access bus. The metallic test access bus is operable to selectively couple to one or more input/output ports within the line card slots of the chassis to establish one or more metallic test paths. A relay matrix may be used to provide the selective coupling for the metallic test access bus, and the flexibility provided by the configuration of the relay matrix supporting the metallic test access bus allows for a variety of different test access ports (TAPs) to be supported. Specific TAP configurations may be configured that support both a Safety Extra Low Voltage (SELV) rated stimulus and a Telecom Network Voltage (TNV) rated stimulus such that local loops that support a variety of different signaling protocols can be tested using the metallic test access bus either individually or concurrently.

The invention discloses a stepless rapid phase-control reactive power dynamic compensation device and a reactive dynamic compensation method. The device comprises a compensation transformer and a control circuit thereof, a capacitor or a capacitor bank; wherein, a secondary winding of the transformer is connected between an access bus and the capacitor in series; a primary winding of the transformer is connected to the output terminal of the control circuit; the control circuit comprises a phase-adjusting circuit adapted with a working power supply, a signal detection circuit connected between the access bus and the phase-adjusting circuit in series and a sampling circuit connected between the phase-adjusting circuit and the output side of the secondary winding of the transformer; the primary winding of the transformer is connected to the output terminal of the phase-adjusting circuit. The reactive compensation of the invention can be realized only by adjusting the output voltage phase of the phase-adjusting circuit, therefore, the invention can realize stepless compensation and has high adjusting accuracy, rapid response, high efficiency and good compensation effect. The compensation device and method of the invention are suitable for all the voltage grades of the existing power grids and various places such as substations, electrified railways and the like.

A process of programming or reprogramming a reprogrammable onboard memory (5) comprises programming or reprogramming the onboard memory of several modules (M0, M1) in parallel through a multiple access bus (6) to which the modules are connected. In the case of blank flash memories, a process downloads code through the multiple access bus (6) and executes the code, eliminating all external constraints (such as frequency, binary throughput). The process is more particularly intended to apply to onboard flash type memories.

The invention provides a random access memory access bus ECC (error checking and correcting) verification device, which comprises a main equipment module, a random access memory and a bus connector positioned between the main equipment module and the random access memory, wherein a bus ECC bridging module is arranged between the random access memory and the bus connector; the bus ECC bridging module comprises at least two gate control registers, at least two bus response gates, at least two bus transmission gates and an ECC bridge, wherein the first bus input end of each bus transmission gate and the coding input end of the ECC bridge are both connected to the bus connector; the first response input end of each bus response gate and the decoding input end of the ECC bridge are both connected to a random access memory end; a first switch is arranged between the coding input end of the ECC bridge and the bus connector; a second switch is arranged between the random access memory and the decoding input end of the ECC bridge. According to the random access memory access bus ECC verification device disclosed by the invention, whether each random access memory needs ECC verification or whether ECC verification is required in the random access memory is flexibly selected according to different application occasions, thereby being convenient for system expanding application, and improving the integral efficiency.

A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.

The invention discloses a network device and a console configuration method for the network device. Based on the network device and the console configuration method for the network device, through switching communication of a console of a main control panel, communication between the console of the main control panel and a CPU of a principle panel can be achieved through an intra-panel serial port bus so that the main control panel can use a console of the principle panel, and the console of the main control panel can also be communicated to an interface panel through an inter-panel access bus so that the interface panel can use the console of the main control panel. Thus, the interface panel in the network device can reuse the console of the main control panel so that the requirement of the interface panel for using the console can be met.

Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system includes an external access bus used when data is output from the CPU or data is input to the I/O unit or the internal memory unit; an internal access bus used when data is input to the CPU, data is output from the I/O unit or the internal memory unit, or data is input to or output from the peripheral circuitry; and an internal memory test bus used when data is output from the internal memory unit and input to the I/O unit.

The invention provides an intelligent remote power utilization monitoring modularization device and system. The device mainly comprises a monitoring module, a processing module, a micro control moduleand a communication module, wherein the monitoring module is connected with a power utilization access bus and used for collecting power utilization data; the processing module is connected with themonitoring module and used for analyzing the power utilization data according to a preset algorithm; the micro control module is connected with the processing module and used for receiving and executing a control instruction; and the communication module is connected with the micro control module and used for communicating with external equipment. The system mainly comprises the device, a background server and a client. The device provided by the invention adopts a modular design, and has the characteristics of simple structure, convenient installation, easy maintenance and the like. The system provided by the invention can provide detailed power utilization data of electrical appliances or electrical equipment and provide the information such as intelligent energy conservation suggestionsand measures, equipment health inspection or fault early warning through the algorithms such as big data analysis and a neural network.

The invention provides a multi-source multi-modal data processing system and a method using the system. The processing system comprises a multi-source multi-modal data storage module, a strategy control module, a risk measurement module, a data discovery engine module, a data desensitization engine module, a multi-modal sensitive data classification algorithm library module, a multi-modal data desensitization algorithm library module and a multi-source multi-modal data access bus module. The multi-source and multi-mode data access bus module provides an interface for accessing the multi-sourceand multi-mode data storage module for other modules, and multi-source and multi-mode data reading, analyzing and writing are achieved. According to the system method, the problems that sensitive information in multi-source and multi-mode data is missed or mistakenly recognized, and the sensitive information is not desensitized or insufficient in desensitization in the prior art are solved.