Random access memory access bus ECC (error checking and correcting) verification device

Abstract

The invention provides a random access memory access bus ECC (error checking and correcting) verification device, which comprises a main equipment module, a random access memory and a bus connector positioned between the main equipment module and the random access memory, wherein a bus ECC bridging module is arranged between the random access memory and the bus connector; the bus ECC bridging module comprises at least two gate control registers, at least two bus response gates, at least two bus transmission gates and an ECC bridge, wherein the first bus input end of each bus transmission gate and the coding input end of the ECC bridge are both connected to the bus connector; the first response input end of each bus response gate and the decoding input end of the ECC bridge are both connected to a random access memory end; a first switch is arranged between the coding input end of the ECC bridge and the bus connector; a second switch is arranged between the random access memory and the decoding input end of the ECC bridge. According to the random access memory access bus ECC verification device disclosed by the invention, whether each random access memory needs ECC verification or whether ECC verification is required in the random access memory is flexibly selected according to different application occasions, thereby being convenient for system expanding application, and improving the integral efficiency.

Description

technical field [0001] The invention relates to a random memory system, in particular to a random memory access bus ECC checking device. Background technique [0002] Affected by electromagnetic interference or process defects, random storage devices or bus transmissions have a certain probability of single-bit state flip errors. This cannot be allowed in systems with extremely high reliability requirements such as automotive electronics. Therefore, in embedded systems with high reliability requirements, ECC functions that support error correction and error detection are generally added at the bus level. Slaves mounted on the bus can share ECC logic, and the original IP can basically be protected by ECC on the basis of reuse. [0003] In the existing technology, the Slave mounted on the bus that requires ECC protection is implemented by adding an ECC module. The system designer needs to allocate the memory area that needs ECC protection at the initial stage of design, and ...

AI Technical Summary

Problems solved by technology

This method is relatively inflexible, and once the corresponding memory space is set as an area protected by ECC, even if the area does not need to be protected by ECC in different applications, the area cannot be reused, which not only has poor flexibility, but also can The portability is also low, which is not conducive to the improvement of system performance

Images