1262 results about "Control register" patented technology

A method for restricting access to an encryption key of an encrypted file system (EFS), whereby access is provided only when a computer system is booted in a trusted state. The EFS encrypts the files within a TPM chip according to TCPA specifications and simultaneously creates the encryption key, which is also stored in the TPM. The key is sealed to one or more platform control register (PCR) states (i.e., the TPM will export the key only when the PCRs are in a pre-defined state.). The original PCR states are modified during boot up of the computer system via a secure hashing algorithm, which extends a value of one PCR to a next PCR at each stage of the boot process and then hashes the value with the remaining content of the next PCR. When the system boot process is completed and before control passes to the user, the values within the PCRs are compared to values stored in a PCR table within the TPM, and the encryption key is exported to the OS kernel only when the PCR values match the table values. The control code of the TPM chip decrypts and exports the key only if the value of each and every PCR matches its corresponding table value. A complete match indicates that the computer system has completed a trusted boot sequence.

A memory system comprises a flash memory, a processing unit, and a flash controller including address and control registers, the address and control registers being configured to receive information from the processing unit, wherein the flash controller is configured to control a copy-back program operation of the flash memory in hardware based on information stored in the address and control registers.

A microprocessor includes a first processing core, a first cryptographic coprocessor and an integer multiplier unit that is coupled to the first processing core and the first cryptographic co-processor. The first processing core includes an instruction decode unit, an instruction execution unit, a load/store unit. The first cryptographic coprocessor is located on a first die with the first processing core. The first cryptographic co-processor includes a cryptographic control register, a direct memory access engine that is coupled to the load/store unit in the first processing core and a cryptographic memory.

An Electronically-Controlled Register vent (ECRV) that can be easily installed by a homeowner or general handyman is disclosed. The ECRV can be used to convert a non-zoned HVAC system into a zoned system. The ECRV can also be used in connection with a conventional zoned HVAC system to provide additional control and additional zones not provided by the conventional zoned HVAC system. In one embodiment, the ECRV is configured have a size and form-factor that conforms to a standard manually-controlled register vent. In one embodiment, a zone thermostat is configured to provide thermostat information to the ECRV. In one embodiment, the zone thermostat communicates with a central monitoring system that coordinates operation of the heating and cooling zones.

Aspects of the invention for managing power in a single chip device may comprise, an internal finite state machine that, while in a communicating state, determines from within the single chip device whether a power management status is set and/or whether a first power management event is received. If the power management status is set, the finite state machine may transition from the communicating state to a power management event sent state. If the first power management event is received, the finite state machine may transition from the communicating state to a non-communicating state. The first power management event may be a turn off power management event. Furthermore, in instances where the power management status is set, it may be cleared, thereby causing the finite state machine to transition back to the communicating state. One or more power management control registers may be utilized for indicating power management status.

A zone thermostat for use in connection with an Electronically-Controlled Register vent (ECRV) that can be easily installed by a homeowner or general handyman is disclosed. The ECRV can be used to convert a non-zoned HVAC system into a zoned system. The ECRV can also be used in connection with a conventional zoned HVAC system to provide additional control and additional zones not provided by the conventional zoned HVAC system. In one embodiment, the ECRV is configured have a size and form-factor that conforms to a standard manually-controlled register vent. In one embodiment, the zone thermostat is configured to provide thermostat information to the ECRV. In one embodiment, the zone thermostat communicates with a central monitoring system that coordinates operation of the heating and cooling zones.

A method of controlling access to a control register of a microprocessor. The method of controlling access to a control register of a processor having a normal execution mode and a secure execution mode may include storing state and mode information in the control register, allowing a software invoked write access to modify the state and mode information within the control register during the normal execution mode and selectively inhibiting the software invoked write access during the secure execution mode.

A modular Electronically-Controlled Register Vent (ECRV) that can be easily installed by a homeowner or general handyman is disclosed. The ECRV can be used to convert a non-zoned HVAC system into a zoned system. The ECRV can also be used in connection with a conventional zoned HVAC system to provide additional control and additional zones not provided by the conventional zoned HVAC system. In one embodiment, the modular ECRV can be configured to various sizes and form-factors that conform to a standard manually-controlled register vent. In one embodiment, a zone thermostat is configured to provide thermostat information to the ECRV. In one embodiment, the zone thermostat communicates with a central monitoring system that coordinates operation of the heating and cooling zones. In one embodiment, the zone thermostat communicates with a central monitoring system that coordinates operation of the heating and cooling zones and provides heating and cooling to the various zones according to a cost budget.

An Electronically-Controlled Register vent (ECRV) that can be easily installed by a homeowner or general handyman is disclosed. The ECRV can be used to convert a non-zoned HVAC system into a zoned system. The ECRV can also be used in connection with a conventional zoned HVAC system to provide additional control and additional zones not provided by the conventional zoned HVAC system. In one embodiment, the ECRV is configured have a size and form-factor that conforms to a standard manually-controlled register vent. In one embodiment, a zone thermostat is configured to provide thermostat information to the ECRV. In one embodiment, the zone thermostat communicates with a central monitoring system that coordinates operation of the heating and cooling zones.

An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be independently powered. The power control manager includes a set of control registers storing individual control bits, a power switch for each power domain and a programmable microprocessor. The programmable microprocessor controls the digital state of individual bits within the control registers thereby controlling the ON and OFF state of the corresponding power domain.

The present invention provides an apparatus, system and method for providing a generalized queue pair for use with host channel adapters of a system area network. With the apparatus, system and method, the hypervisor of a host channel adapter maintains a P_Key table for each logical port of the host channel adapter. When a request is received to allocate a queue pair from a requestor application associated with a logical port, a P_Key mode is set in a control register associated with the queue pair based on the type of requestor application that sent the request. Based on this P_Key mode, one or more P_Keys from a P_Key table associated with the logical port from which the request was received are written to one or more P_Key registers allocated to the queue pair. These P_Keys are then used to perform P_Key checks of incoming data packets. In addition, these P_Keys are inserted into headers of outgoing data packets. In a preferred embodiment, the P_Key modes may be a single P_Key check mode, a multiple P_Key check mode, and a P_Key check disabled mode.

In one embodiment, an input/output memory management unit (IOMMU) comprises a control register configured to store a base address of a set of translation tables and control logic coupled to the control register. The control logic is configured to respond to an input/output (I/O) device-initiated request having an address within an address range of an address space corresponding to a peripheral interconnect. One or more operations other than a memory operation are associated with the address range, and the control logic is configured to translate the address to a second address outside of the address range if the translation tables specify a translation from the address to the second address, whereby a memory operation is performed in response to the request instead of the one or more operations associated with the address range.

The present invention offers a daisy chain serial bus system. For bus construction, the slave device has a first data transmission port to transfer serial data with its upward connected device and a second data transmission port to transfer serial data with its downward connected device. The most upward slave device is connected to a master device. In each slave device, the input data from a first data transmission port is transferred to a data input gate in a second data transmission port. There is a control register in each slave device to control the data input gate of the second data transmission port. After the bus system has been started, only the slave device connected to the master device can receive the data from the master device, so that the master device can assign the first device address to the slave device connected to it, then, the master device can assign the second device address to the slave device next connected to the first slave device on the bus. By this way, the master device can assign the device address to each slave device on the bus one by one.

The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data.

The embodiment of the invention discloses an overcurrent protection circuit, and the circuit comprises a level converter and a substrate array line drive (GOA) circuit in electrical connection with the level converter. The circuit also comprises a current detection circuit, a current-voltage converter, a voltage comparator, a timer control register, and a logic gate circuit. The GOA circuit is connected with the current detection circuit, and the current detection circuit is connected with the current-voltage converter. The current-voltage converter is connected with the in-phase input end of the voltage comparator, and the inverted-phase input end of the voltage comparator is connected with a reference voltage. The output end of the voltage comparator is connected with the input end of the timer control register and the first input end of the logic gate circuit. The output end of the timer control register is connected with the second input end of the logic gate circuit. The output end of the logic gate circuit is connected with the level converter. According to the embodiment of the invention, the circuit can prevent the wrong triggering of an overcurrent protection operation. The invention also provides a liquid crystal display comprising the circuit.

A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

A method and system for routing fibre channel frames using a fibre channel switch element is provided. The switch element includes logic for comparing a credit counter value with a first threshold value to enable a credit limiting feature; and a first counter that receives a signal after a frame has departed from a transmit segment and maintains a maximum value for a certain duration that is based on the first threshold value. The method includes enabling a credit limiting feature, wherein frame transmission from a certain source is delayed when the credit limiting feature is enabled. The first counter is incremented every time a frame departs and holds its maximum value based on the threshold value. When the first counter is at the maximum value, a credit-limiting signal is used to enable the credit limiting feature by setting a control bit in a control register.

A zone thermostat for use in connection with an Electronically-Controlled Register vent (ECRV) that can be easily installed by a homeowner or general handyman is disclosed. The ECRV can be used to convert a non-zoned HVAC system into a zoned system. The ECRV can also be used in connection with a conventional zoned HVAC system to provide additional control and additional zones not provided by the conventional zoned HVAC system. In one embodiment, the ECRV is configured have a size and form-factor that conforms to a standard manually-controlled register vent. In one embodiment, the zone thermostat is configured to provide thermostat information to the ECRV. In one embodiment, the zone thermostat communicates with a central monitoring system that coordinates operation of the heating and cooling zones. In one embodiment, the zone thermostat communicates with a central monitoring system that coordinates operation of the heating and cooling zones and provides heating and cooling to the various zones according to a cost budget.

The invention discloses a NAND flash controller, including a command and address data transmission channel adapted to connect the bus timing interface with the channel selector and transmit command and address data, a data buffer region adapted to receive message data from the bus timing interface through system bus, a control register adapted to receive an operation parameter configured through system bus via the bus timing interface, a logic controller adapted to write the data information into or read the data information from the data buffer region according to the operation parameter, a channel selector adapted to connect the DMA data transmission channel or the command and address data transmission channel according to the operation parameter for transmitting data. The invention also discloses a date exchange method between NAND flash controller and NAND flash memory. The invention improves the data transmission efficiency and is compatible with various NAND flash memories.