420 results about "Control register" patented technology

Provided is a direct memory access architecture, including: a direct memory access control component, a read data moving component, a write data moving component and a data storage component; wherein the direct memory access control component includes a control register, a read descriptor storage component, a write descriptor storage component, a read command transfer component and a write command transfer component; the control register is configured to obtain descriptor address information; the read descriptor storage component is configured to store a read descriptor obtained by using the control register; the write descriptor storage component is configured to store a write descriptor obtained by using the control register; the read command transfer component is configured to send, to the read data moving component, a read command; the write command transfer component is configured to send, to the write data moving component, a write command.

The invention provides an equipment state detection method and device, equipment and a medium, and is applied to the technical field of equipment state detection.The equipment state detection method comprises the steps that a target event counter corresponding to a target event is enabled based on configuration information of a control register, and an event statistical period corresponding to the target event counter is determined, the target event is an event selected from various events obtained based on equipment state classification; counting the occurrence frequency of the target event in the event counting period based on a target event counter; and writing the occurrence frequency into a result register, so that a host acquires the occurrence frequency in the result register, and realizes equipment state detection based on comparison between the occurrence frequency and an expected value corresponding to the target event. Therefore, equipment state detection can be flexibly carried out, possible faults of the equipment can be found in advance, and timely problem finding is guaranteed. Moreover, by enabling the target event counters corresponding to various events, comprehensive detection of the equipment state can be realized.

Systems, apparatus, articles of manufacture, and methods are disclosed for a machine learning model decompression accelerator. An example apparatus includes a processor core including at least one matrix multiplication engine, a memory storing a plurality of tiles of compressed data of a machine learning model to be processed by the at least one matrix multiplication engine; and a decompression accelerator including one or more control registers in communication with the processor core, a processing engine in communication with the memory and configured by the one or more control registers to decompress the plurality of tiles of the compressed data, and an output register to store decompressed data, wherein the processor core is to read the decompressed data from the output register and cause the at least one matrix multiplication engine to perform matrix multiplication with the decompressed data for execution of the machine learning model.

The invention discloses an ARMv8-based virtual machine interrupt through routing method, which comprises the following steps that: a Hypervisor directly routes a physical interrupt to an EL1 through configuration, sets a top page table address of a vCPU (Virtual Central Processing Unit) and a Hypervisor control register at the same time, and sets a vcpudid flag bit for indicating whether the vCPU adopts a virtual interrupt injection mechanism or a physical interrupt through routing mechanism; and judging whether an interrupt through routing condition is met or not so as to determine whether an interrupt through routing mechanism or a virtual interrupt injection mechanism is adopted, periodically judging whether a switching condition is met or not when the interrupt through routing mechanism is adopted, and switching from the interrupt through routing mechanism to the virtual interrupt injection mechanism if the switching condition is met. The method is compatible with two interrupt controller specifications of GICv2 and GICv3, supports the virtual machine and the hypervisor to respectively and independently respond to respective corresponding interrupt requests, and meanwhile, the method has the capability of dynamically switching an interrupt routing mechanism during the system operation period, so that the flexibility of interrupt processing and the expandability of the system are improved.

The invention provides a data transmission method and system, a chip, electronic equipment and a storage medium, the method is applied to a processing module of the data transmission system, and the method comprises the following steps: under the condition that an interrupt request is received, obtaining a data transmission instruction, and performing data analysis on the data transmission instruction to obtain an interrupt request; obtaining a data operation type, an interface type and a data transmission parameter; acquiring register configuration data corresponding to the interface type, and performing configuration corresponding to the register configuration data and the data transmission parameters on the configuration register through the internal bus; under the condition that configuration of the configuration register is completed, data to be transmitted are obtained through a transmission interface corresponding to the register configuration data, and data transmission corresponding to the data operation type and the data transmission parameter is conducted on the data to be transmitted based on the control register and the encryption and decryption unit. The transmission interface is one of a bus master interface, a bus slave interface and a private interface.

The invention relates to a data transmission processing system, method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps of: transmitting received storage data from a host to a rear end through a storage data forwarding module in an FPGA (Field Programmable Gate Array) chip; the method comprises the following steps: controlling a stored data forwarding module to be initialized through an SOC chip under the condition that transmission of stored data is detected to be abnormal; controlling the register module to obtain queue pointer information of the host; the obtained queue pointer information is stored in the initialized storage data forwarding module; sending a retransmission instruction to the initialized storage data forwarding module; and further executing a data retransmission operation of the stored data according to the received retransmission instruction through the initialized stored data forwarding module so as to transmit the stored data to a rear end in a lossless manner. By adopting the method, lossless data transmission can be realized, and the stability and robustness of the system are improved.

The invention provides an EtherCAT slave station port identification and topology diagnosis system and method. Comprising a master station access interface module which is used for being in butt joint with an EtherCAT master station protocol stack and establishing a read-write channel for a data link layer register of a slave station controller; the port state acquisition module is used for analyzing to obtain a physical connection indication, a loop opening and closing state and a communication state of each port, and generating a port state record; the state analysis and control module is used for writing a port opening instruction into a data link layer control register when physical connection exists and a loop is closed, and selecting a preset recovery port of the system to execute register writing when all ports of the target slave station are detected to be in a closed state, so as to obtain a port judgment result; and the topology and diagnosis output module is used for establishing a connection relationship between slave stations based on the port judgment result to generate network topology data. According to the application, unified collection and analysis of registers, automatic judgment and recovery of ports, topology reconstruction and standardized diagnosis output can be realized.

A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced power consumption and latency. When the link transitions from an active functional state in which the link has a first configuration of N active lanes to a power-saving state, the number of active lanes is collapsed such that M of the N lanes are maintained in an active power-saving state and P of the N lanes are maintained in an electrically idle state, where M, N and P are positive integers and N>P>M. The reduction in lane width reduces power consumption. Bit values specifying the current link configuration can be saved in a control register and read and compared to bit values contained in a link control register before transitioning back to the active functional state. If the bit values match, the active functional state is resumed directly from the recovery state, thereby reducing latency.

The invention belongs to PCIe equipment, and relates to an NVMe controller and an initialization and data read-write method thereof, and the NVMe controller comprises a PCIe module with a DMA unit, an address translation unit ATU module, an SRAM and an equipment CPU. According to the invention, an SRAM (Static Random Access Memory) replaces an NVMe hardware control register, the space content of the SRAM is polled to obtain the change information of the register and send the change information to different modules for processing, and after the controller is polled and the register senses the change, the operations of initialization, resetting and the like are carried out; and after the polling doorbell register senses the change, a host storage command is obtained through the DMA unit, command analysis is performed, and the command is sent to other modules for processing. According to the method, special hardware design and verification are not needed, the development cost and time are reduced, the possibility of hardware fault points and hardware errors is reduced, the complexity of the system is simplified, and the NVMe controller is easy to modify and low in maintenance and updating cost; the method does not need to develop a host end drive program, and the development workload is small.

The invention discloses a loop control method and system based on RISC-V expansion. The loop control method comprises the following steps: customizing a loop control instruction in a main operation code and an instruction coding space reserved by RISC-V; an instruction fetching module, a decoding module, a state control register and a hardware loop control module are designed, loop information is written into the state control register by the decoding module, the loop information is read from the state control register by the hardware loop control module, arbitration is carried out by combining a control signal and an instruction address of the decoding module, and when a current address does not reach a loop end, the hardware loop control module is started. Sending an enable signal to enable the instruction fetching module to fetch instructions in sequence, and sending a cycle start address to the instruction fetching module to enable the instruction fetching module to circulate continuously when the current address reaches the last instruction of the cycle section and the cycle times are not reset to zero, so that a condition jump instruction of existing cycle judgment is omitted; and an assembly instruction part for loop control is replaced by an expanded loop control instruction, so that the performance loss caused by a loop program can be effectively reduced.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention relates to the technical field of industrial robots and intelligent control, and discloses an explosion-proof robot MOS tube optimization driving control method and system based on an intelligent algorithm. The method comprises the following steps: acquiring multi-point temperature monitoring data of a power device to construct a virtual thermal gradient model; according to the virtual thermal gradient model, operation boundary parameter optimization calculation is carried out, and a dynamic safety threshold value is determined; acquiring real-time output state data of the driving system and generating a preliminary steady-state control strategy by combining the real-time output state data with the dynamic safety threshold; monitoring load efficiency feedback data, and triggering multi-target optimization of driving parameters by taking the dynamic safety threshold as a boundary constraint when an efficiency decline feature is identified, so as to obtain a to-be-verified driving parameter set; performing online prediction verification on the to-be-verified driving parameter set to generate a verification result identifier; and according to the verification result identifier, performing configuration updating or configuration keeping processing on a control register of the driving system during operation. The method effectively improves the system stability.

The invention provides an EEPROM (Electrically Erasable Programmable Read-Only Memory) data read-write method and device based on a real-time industrial Ethernet and a medium. The method comprises the following steps: setting an initial offset and an access length of EEPROM access on a target slave station according to EEPROM capacity parameters, and establishing a paging transaction; when the paging transaction is of a reading type, sequentially triggering EEPROM control registers of the target slave station, reading EEPROM data to a buffer area of the master station according to pages from the initial offset, and executing cyclic redundancy check on each page of read data; when the paging transaction is of a write-in type, reading a to-be-written data file into a buffer area of the master station, writing the to-be-written data file into an EEPROM (Electrically Erasable Programmable Read-Only Memory) of a target slave station according to a page sequence from initial offset, and after writing of each page is completed, reading back data of the page and executing cyclic redundancy check; and when all page data of the paging transaction of the reading type or the writing type passes cyclic redundancy check, outputting a transaction completion state to the soft programmable logic controller. According to the method and the device, the technical effects of safely, efficiently and accurately reading and writing the EEPROM on line in batches and ensuring the data consistency can be achieved.

The invention discloses a redundancy-based hardware failure time division multiplexing detection circuit and method, and the method comprises the steps: enabling the counting of an input selection counter to be connected with a first input completion mark outputted by an upstream circuit, and enabling the counting of an output selection counter to be connected with a second input completion mark outputted by a downstream circuit; the output end of the input selection counter is connected with the enabling end of the input selector muxin, and the output end of the output selection counter is connected with the enabling end of the output selector muxout; the input end of the input selector muxin is connected with the output of the upstream circuit, the output end of the input selector muxin is connected with the input end of the redundant circuit, the input end of the output selector muxout is connected with the output of the hardware circuit, and the output end of the output selector muxout is connected with one input end of the comparator; the input end of the redundant circuit is connected with the output end of the input selector muxin, the output end of the redundant circuit is connected with the other input end of the comparator, and the output end of the comparator is connected with the control register.

The invention discloses an FIR filter circuit structure, and the structure comprises a path control unit which generates a first control signal and a second control signal according to the number and order of filters which are customized by a user; the routing unit correspondingly transmits the filtering data received by the filtering data channel unit to the multiply-add unit array based on the first control signal; the multiply-add unit array comprises N multiply-add units, and the multiply-add units are connected through data selectors; the path control register unit is connected with a selection port of the data selector, and the path control register unit controls a data path of the multiply-add unit array through the data selector based on a second control signal; and the filtering result operation unit adds the multiplication and addition results of the corresponding multiplication and addition unit to obtain the filtering result of the corresponding filter. According to the invention, the multiplication and addition unit structure of the filter circuit can be customized according to user requirements, and the FIR filter circuit with low circuit resource ratio and high operation speed is configured.

The invention relates to the technical field of semiconductor design and manufacturing, in particular to an operation method and a design method of a multi-core chip and the multi-core chip. According to the technical scheme, circuit logics which can accept manufacturing defects are divided into the first logic group, and circuit logics which cannot accept manufacturing defects are divided into the second logic group; by reading the defect state of at least one computing core on the multi-core chip, the availability of a first logic group capable of accepting manufacturing defects in the computing core can be determined; and when the defect state indicates that the first logic group is unavailable, configuring a control register in the computing core to close the first logic group, and keeping a second logic group which is not accepted to manufacture defects in the computing core in a running state without influencing the functional circuit logic of the computing core. According to the technical scheme, the circuit logic, capable of accepting manufacturing defects, of the multi-core chip still has usability when the manufacturing defects occur, and the overall yield of manufacturing of the multi-core chip is improved in a disguised mode.

The invention discloses a crossbar switch control method based on cache information exchange, which relates to the technical field of integrated circuits and high-speed interconnection, and comprises an outlet flow control waterline register, an outlet congestion waterline register and a dequeue strategy optimization control register of an inlet receiving module in initialization configuration center control; the cache occupation amount of each outlet is monitored in real time, when the outlet cache is in an early warning state, an inlet dequeue strategy is controlled, and outlet data messages in a non-early warning state are scheduled preferentially; the cache occupation and release information is interacted in real time, and the early warning state is updated through the change of an occupation amount register; and dynamically optimizing an entrance dequeue sequence based on an exit cache early warning state, and performing decentralized flow cooperative control. The problem of performance loss of a traditional Crossbar switching chip caused by outlet bottleneck is effectively solved, and a high-performance and high-reliability switching chip technical scheme is provided for the fields of data center lossless interconnection, 5G core network packet switching and the like.

The invention belongs to the field of switch chips, and relates to a hardware and software combined PCIE address translation and networking design device and method, the hardware and software combined PCIE address translation and networking design device comprises an address translation unit, a built-in CPU and firmware and a TLP transceiving unit, the address translation unit comprises a control register and an address or BDF translation module for implementing TLP address or BDF translation; the firmware is used for completing the simulation of the iEP, and the simulation method is that software is used for completing the response to a received configuration request TLP, so that a DSP and an EP are simulated; and the TLP receiving and transmitting unit connects the built-in CPU to a switching network, so that the built-in CPU receives and transmits a TLP data packet. According to the PCIe switching chip, a tree topology structure of a traditional PCIe switching chip can be broken through, and any needed network topology structure can be flexibly connected through software configuration; a plurality of hosts and devices can be connected at any port as required; the required iEP is realized by using internal firmware, the function of the iEP can be realized by more flexible programming, and the design cost is reduced compared with the method for realizing the iEP by using hardware.

An apparatus and method for securely reserving resources for trusted execution. For example, one embodiment of a processor comprises: a plurality of cores, each core of the plurality of cores to provide at least one logical processor of a plurality of logical processors; a first plurality of registers, each register of the first plurality of registers to associate a class of service (CLOS) value with a corresponding logical processor of the plurality of logical processors; a second plurality of registers, each register of the second plurality of registers to indicate a portion of a shared resource to be allocated to a corresponding CLOS value; a first control register of a first logical processor of the plurality of logical processors to be configured with a reserved CLOS value associated with a trusted control structure; resource reservation circuitry configurable by secure firmware or software to indicate a reserved portion of the shared resource associated with the reserved CLOS value; and enforcement circuitry to limit access to the reserved portion of the shared resource to threads or logical processors associated with the reserved CLOS value.

Certain examples described herein relate to a co-processor that allows a processing unit to efficiently perform a cryptographic operation. The co-processor has an arithmetic unit that is configured to perform discrete binary arithmetic using bit sequences loaded from a memory. The co-processor may be configured for fast, low-power computation of certain functions that comprise low-level building blocks for the cryptographic operation. These functions may include Boolean logic and integer arithmetic. The co-processor has a set of control registers that are writable by the processing unit to control the co-processor. Addresses for one or more sources and destinations may be computed by the co-processor to allow for flexible operation. The co-processor may allow many advanced cryptographic operations to be rapidly computed, including those that are “post-quantum” secure.

This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

The invention discloses a task processing method and system based on configuration queue data, and the method comprises the steps: storing register configuration parameters of a plurality of tasks in an internal storage space in advance; hardware reads back configuration queue data through an internal storage space to analyze an issued task before processing the task, and after configuration updating of an internal control register is completed and a current task is processed according to the updated configuration, a new task is executed, so that a new task can be executed under the condition that the control register is not added. According to the method, the occurrence condition of task gaps caused by untimely interrupt response of the processor can be reduced, so that the performance loss of the processor caused by null etc. is reduced, the resource utilization rate of arithmetic logic is improved, and the performance of the processor is improved; and under the condition that hardware resources are not increased, the execution unit of the data processor can reach the upper limit of hardware performance, and cost is saved while the performance utilization rate of the execution unit is improved.

The invention provides an SoC system control method and device, electronic equipment and a readable storage medium, and the method comprises the steps: controlling a CPU large core to generate a control instruction, and writing the control instruction into a register; the control register analyzes the control instruction, determines at least one target function module associated with the control instruction, generates a corresponding enable signal and sends the enable signal to a control circuit corresponding to each target function module; and aiming at the control circuit of each target function module, controlling the control circuit to receive and analyze the corresponding enable signal, generating control information and sending the control information to the corresponding target function module, so that each target function module is configured according to the control information and executes the control instruction. Therefore, the configuration time of the CPU for configuring the functional modules one by one through the on-chip internet can be reduced, and the control efficiency of the SoC system is further improved.

Aggregated subordinate control over a serial bus is described in the present disclosure. Herein, a serial bus circuit includes multiple subordinate circuits each configured to operate based on a respective one or more control bits programmed into a respective control register(s). Understandably, if the control register(s) in each of the subordinate circuits is programmed individually through multiple bus telegrams, then much of the already limited bandwidth of the serial bus will be wasted. In this regard, in embodiments disclosed herein, a single bus telegram can be configured to carry an aggregated control word that can simultaneously program the control register(s) in multiple subordinate circuits. As a result, it is possible to reduce bus telegrams for programming the subordinate circuits, thus helping to conserve bandwidth of the serial bus.

The invention discloses a DDR5 dynamic ODT regulation and control method, device and equipment based on multi-working-condition perception and a medium, and relates to the field of computer memories, and the method comprises the steps: obtaining a power supply ripple value and a DRAM chip temperature value of a system; querying a preset ripple-temperature-ODT value corresponding table by taking the power supply ripple value and the DRAM chip temperature value as a joint index to obtain a corresponding target ODT value; and writing the target ODT value into an ODT control register of the DDR5 chip through a mode register setting command. Multi-working-condition sensing is achieved by synchronously monitoring power supply ripples and chip temperature, the optimal ODT value is directly obtained based on a joint index query preset optimization mapping table, and finally configuration is written through a standard MRS command. Comprehensive state monitoring, pre-stored expert knowledge and a standard hardware interface are combined, microsecond-level fast decision making and reliable regulation and control are achieved, on the premise that an existing DDR5 standard is completely compatible, signal integrity is effectively guaranteed, system power consumption is optimized, and the overall performance and energy efficiency of a memory subsystem are improved.

The invention relates to a memory recovery method and device, electronic equipment and a medium, and the method comprises the steps: obtaining a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent to a memory recovery device after the target processor is powered on; in the power-on recovery processing process of the target processor, determining whether a target memory needing to be controlled by the target processor is in a power-down sleep state or not; when the target memory is in the power-down sleep state, performing control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal to realize memory recovery processing; wherein in the memory recovery process, only one target processor is needed to carry out self power-on processing, and the power consumption of memory recovery is low; and the self-power-on processing and the memory recovery processing of the target processor can be performed in parallel, so that the memory recovery time is shortened, and the memory recovery efficiency is improved.

A security agent configured to initiate a security agent component as a hypervisor for a computing device is described herein. The security agent component may then determine pages of the memory which include identified memory locations and set privilege attributes of those pages to prevent specific types of access to the memory locations, such as executing code stored at a memory location. Also, the security agent component may refrain from setting intercepts for pages including a whitelisted memory location. Further, the security agent component may set intercepts for debug registers, note read operations from the operating system for those registers, and respond with operating-system-permitted values. Additionally, the security agent component may set intercepts for instructions for performing write operations on control registers.

Provided is a direct memory access architecture, including: a direct memory access control component, a read data moving component, a write data moving component and a data storage component; wherein the direct memory access control component includes a control register, a read descriptor storage component, a write descriptor storage component, a read command transfer component and a write command transfer component; the control register is configured to obtain descriptor address information; the read descriptor storage component is configured to store a read descriptor obtained by using the control register; the write descriptor storage component is configured to store a write descriptor obtained by using the control register; the read command transfer component is configured to send, to the read data moving component, a read command; the write command transfer component is configured to send, to the write data moving component, a write command.

The invention provides a DMA (direct memory access) engine device and a data transmission method in a PCIE (peripheral component interface express)-to-RapidIO circuit, a DMA engine comprises a sending engine and a receiving engine which are used for processing data processing and protocol conversion of data packets sent and received in a DMA transmission process; the cache FIFO is used for caching the data read by the DMA engine; and the DMA channel control module and the state control register are used for controlling the DMA engine to update the operation state. A descriptor is configured in a PCIe memory through a host to define detailed parameters of DMA operation; the DMA engine can support DMA data transmission and protocol conversion between the PCIe core and the RapidIO core, and high-speed and low-delay data transmission in the PCIe-to-RapidIO circuit is achieved.

The invention provides an error frame injection device, method and system, and the device comprises a control register module, an error frame memory module and a medium access control module which are respectively constructed in a field programmable gate array. The control register module is used for receiving an Ethernet data frame and an error frame injection strategy, generating an Ethernet error frame, and generating an injection control signal of the Ethernet error frame according to an error injection frequency if an injection trigger condition is monitored to be established; the error frame memory module is used for receiving and storing Ethernet error frames; and the medium access control module is used for responding to the injection control signal, reading the Ethernet error frame from the error frame memory module, and injecting the Ethernet error frame into the equipment to be tested for testing. By integrating the control register module, the error frame memory module and the medium access control module in the field programmable gate array, Ethernet error frame injection is realized, and an efficient, comprehensive and economical test means is provided for high-speed Ethernet equipment.