37 results about "Control register" patented technology

A computing system is disclosed, comprising a host computer and multiple CGRPs (coarse-grained reconfigurable architecture processors) connected to the host computer through external communication links. Each CGRP includes an internal network, external interface circuits, memory interface circuits, arrays of configurable units, hang detection circuits, force-quit controllers, and a network recovery circuit with control registers. The host computer is programmed to configure and execute applications across the arrays of configurable units in both CGRPs. In case of a hang detection in one CGRP, the network recovery circuit initiates a force quit process and notifies the host computer. Additionally, the network recovery circuit compares application IDs and halts execution in the other CGRP if necessary. This system provides efficient failure tolerance and recovery mechanisms for parallel processing applications.

An apparatus comprises processing circuitry configured to perform data processing in response to instructions executed in one of a plurality of exception levels; system registers configured to store s

A compute array employs localized redundant columns within each compute row to replace defective columns through software-controlled multiplexers. The multiplexers, located in inter-row regions, enable substitution of redundant columns in the same compute row under control of a redundancy management system implemented in software, firmware, or hardware. A general-purpose controller configures the multiplexers by writing to control registers based on defect-map information obtained from test routines. This distributed but software-orchestrated redundancy system maintains timing consistency, simplifies layout, and provides high-yield fault tolerance with minimal additional hardware.

This application provides a clock peak shifting control device, control method, and chip. The device includes a first selection module, a first delay module, a second selection module, and a first latch module. The first delay module generates a target delay clock signal. The first selection module selects between a test clock signal and the target delay clock signal. The second selection module switches between different operating modes of the chip to obtain a drive clock signal. The latch module controls the timing of different groups of registers. The drive clock signal provides a clock signal for each register in each register group, ensuring that registers in each group do not flip at the same time. This reasonable peak shifting control of register flipping time effectively reduces the peak power consumption during the shift process.

A method of temporal freedom from interference (FFI) for safe tasks is described. The method includes writing an incoming safe task to a safe task field of a control register. The method also includes determining a safe partition and a non-safe partition of processing elements (PEs). The method further includes determining priorities of currently executed safe tasks in the safe partition and non-safe tasks in a non-safe partition of the PEs. The method also includes preempting a currently executed safe task if a priority of the currently executed safe task is less than a priority of the incoming safe task.

This provides a new power cutoff technology for semiconductor integrated circuit devices. [Solution] The present invention is a semiconductor integrated circuit device comprising a bus, a processor circuit module, and a circuit module to be power-off. The bus comprises a bus core including data signal lines and a predetermined bus interface circuit for connecting the circuit module to the bus core. The predetermined bus interface circuit comprises a transaction control circuit for controlling transactions related to data transmission via the bus core, and a power control circuit including a power control register, which controls the power supply to the circuit module according to the register value held by the power control register. The power control circuit, under the control of the processor circuit module, controls the power supply to the circuit module to be cut off in accordance with a power-off instruction from the transaction control circuit.

A disclosed computer-implemented method may include loading a pair of input vectors of into a respective pair of registers included in a processor, each input vector associated with a different shared scale term. The method may also include storing a shared scale term corresponding to at least one of the pair of input vectors within at least one control register of the processor. The method may also include performing a vector operation that utilizes the pair of input vectors by accessing the at least one control register to retrieve the shared scale term as part of the vector operation Various other methods, systems, and computer-readable media are also disclosed.

Isolation circuitry to implement testing in a semiconductor device is described. In certain examples, a computing system includes a device circuit to generate a resultant and store the resultant in a resultant register; a power supply; a controller circuit to, in response to a power reset indication for the power supply, send a read command to cause the device circuit to return the resultant from the resultant register to the controller circuit; and an isolation circuit comprising a control register that when set to a first value allows the device circuit to receive the read command, and when set to a second value allows the device circuit to receive a test command to cause the device circuit to perform a test operation and ignore the read command.

Embodiments relate to atomic memory operations with floating point values. An example processor comprises: a control register to store rounding mode and denormal mode control bits to indicate a rounding mode and denormal value processing mode; fetch circuitry to fetch a remote atomic operation (RAO) floating point (FP) instruction comprising a memory location to store at least one FP result value; decode circuitry to decode the instruction and scheduling circuitry to offload the instruction to an execution engine external to the logical processor or to schedule the decoded instruction for local execution, wherein an indication of the rounding mode and denormal value processing mode is communicated to the execution engine, the indication to be communicated by a transfer of one or more of the rounding mode control bits and denormal mode control bits to a storage coupled to the execution engine, or to be communicated in the message.

This invention provides an improved method, system, and computer program for performing matrix multiplication computer instructions. [Solution] The method is a processor having a control register and a vector register whose length is indicated in the control register, in which a matrix operation A × B = C is performed, where A is an M × K matrix with elements of a first bit width, B is a K × N matrix with elements of a second bit width, and C is an M × N matrix with elements of a third bit width. The instruction has three parameters that encode the type of multiplication to be performed and indicate which vector register to sequentially store the elements of each matrix in. The method also obtains the length from the control register, decodes the instruction to obtain the multiplication type, determines the first and second bit widths according to the multiplication type, determines the values ​​of M, N, and K according to the length and the first and second bit widths, and performs matrix multiplication considering the three parameters, the first and second bit widths, and the values ​​of M, N, and K.

The application discloses a processor load preheating and exiting method, device, equipment and storage medium, and is applied to the field of processor control, and comprises the following steps: setting a load preheating / exiting control register in a global register of a processor, and configuring a field of the load preheating / exiting control register based on a task load; when reading that the load preheating field is in an activated state, controlling a calculation unit of the processor to execute an invalid calculation task with an increased task amount; and when reading that the load exiting field is in the activated state, controlling the calculation unit of the processor to execute an invalid calculation task with a decreased task amount. According to the method, meaningless calculation tasks are executed by the processor before and after starting or stopping heavy work loads, the load is gradually and slowly increased or decreased, the transition to a normal working state is smoothed, a complex power management strategy is not needed, and the starting stability and reliability of the system can be obviously improved.

A display control circuit and a display control method are provided. The display control circuit includes a storage unit, a control register, a local dimming control register, and a microcontroller unit. The storage unit is configured to store a plurality of predefined LDC setting data. The control register is configured to store a first mode setting value. The local dimming control register is configured to store a LDC setting data that is to be applied in synchronization with a frame synchronization signal. The microcontroller unit is coupled to the control register and the local dimming control register. The microcontroller unit is configured to read a first predefined LDC setting data of the plurality of predefined LDC setting data stored in the storage unit according to the first mode setting value and write the first predefined LDC setting data into the local dimming control register.

The application provides a virtual information processing method, device and storage medium. The method comprises the following steps: a host system creates a virtual device instance, allocs hardware resources and a continuous memory area for the virtual device instance, generates and stores first configuration information corresponding to a physical hardware control register area and second configuration information indicating the memory area, and transmits a real physical base address of the memory area to the virtual device instance; after a virtual machine binds the virtual device instance, the virtual machine completes zero-copy data processing according to the real physical base address, the first configuration information and the second configuration information. Through virtual device instantiation, independent memory allocation and direct transmission of a physical base address, the virtual machine can directly initiate a hardware DMA operation, the data copying overhead is saved, a single physical hardware can be safely shared by multiple virtual machines, and the I / O performance of a virtualization environment and the hardware utilization rate are improved.

Techniques for implementing instructions for a trust domain implemented by a processor are described. In certain examples, a hardware processor core, that implements a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory, includes a debug register; a control register; decoder circuitry to decode a first single instruction into a first decoded instruction, the first single instruction having a field to indicate a data structure to store a control state of a trust domain and a debug state of the trust domain, and an opcode to indicate execution circuitry is to load the control state of the trust domain from the data structure into the control register and load the debug state of the trust domain from the data structure into the debug register; and the execution circuitry to execute the first decoded instruction according to the opcode.

The embodiment of the application provides a data operation bit width expansion method and device, relates to the computer technical field, and comprises the following steps: reading variable vector information in a vector width control register, determining a maximum data operation bit width after expansion based on the variable vector information.If the width of to-be-processed data is greater than an original data operation bit width and less than or equal to the maximum data operation bit width, then based on the width of the to-be-processed data and the bit width of a single operation unit, the target number of operation units used for processing the to-be-processed data is determined.The target number of operation units is written into an operation unit control register after being reduced by one, so as to control the start of the target number of operation units, and the to-be-processed data is processed.Two control registers are newly defined to realize variable vector expansion without changing the original mode, and the data operation bit width is expanded from the original data operation bit width to a larger data operation bit width, so that the parallelization capability of data processing is improved without the need of instruction set expansion and code rewriting.

The objective is to achieve efficient control processing. [Solution] The frame-side control CPU executes a counting notification transmission process which consists of at least the following: a ninth frame-side control load instruction that loads a counting subtraction counter into the first frame-side control register; a tenth frame-side control load instruction that saves the counting subtraction counter to the address of the frame-side control transmit buffer with 3 added to it; a third frame-side control call instruction that calls and executes an SC transmit process that transmits the contents of the frame-side control transmit buffer to the card unit via the first frame-side control serial port; a fifteenth frame-side control load instruction that sets information indicating the completion of counting into the second frame-side control pair register; and a sixth frame-side control call instruction that calls and executes a main transmit process that transmits the contents of the second frame-side control pair register to the game control board via the second frame-side control serial port.

The application relates to the technical field of motor control and serial communication, and provides a low-voltage small motor rotating speed monitoring method based on UART communication. The method comprises the following steps: sending a communication handshake data frame to a motor control board through a serial port to establish a stable serial port communication connection; generating a motor rotating speed setting instruction according to the equipment operation requirement and sending the motor rotating speed setting instruction to the motor control board through the serial port; receiving the data frame by the motor control board, obtaining an instruction code and a target rotating speed parameter through analysis and writing the instruction code and the target rotating speed parameter into a control register; according to the target rotating speed value, executing three proportional integral closed loop control algorithms of constant rotating speed, current limiting and power limiting, adopting a magnetic field oriented control mode to accurately control phase current and rotor angle of the motor, adjusting motor driving signals to realize the target rotating speed; encapsulating running data into feedback data frames by the motor control board, analyzing the feedback data, displaying the motor running state, sending new control instructions according to the feedback information, and realizing real-time control and monitoring.

This invention discloses a hardware circuit supporting SM3 encryption, relating to the field of information security cryptography. It includes a register configuration component, an initialization and update component, and an SM3 hash calculation component integrated at the top layer of the chip and interconnected in pairs. The register configuration component includes a message register, an IV value setting register, a status register, a hash result register, and an SM3 control register. The register configuration component is connected to the CPU via a CPU_IF interface, through which the CPU performs read and write operations on each register. The initialization and update component receives the message data to be encrypted from the message register and the IV value from the IV value setting register, packages the received IV value as the initial IV value and the message data to be encrypted, and forwards it to the SM3 hash calculation component. The SM3 hash calculation component calculates the hash value based on the message data and the IV value, performs endianness conversion, and sends the hash result back to the hash result register. This invention enhances the overall security and computational speed of the chip system.

This application relates to the field of motor control and serial communication technology, and provides a method for monitoring the speed of a low-voltage small motor based on UART communication. The method includes: sending communication handshake data frames to the motor control board via a serial port to establish a stable serial communication connection; generating a motor speed setting command based on the device's operating requirements and sending it to the motor control board via the serial port; the motor control board receiving the data frames via the serial port, parsing the command code and target speed parameters, and writing them into the control register; executing three proportional-integral closed-loop control algorithms—constant speed, current limiting, and power limiting—based on the target speed value, using a field-oriented control method to precisely control the phase current and rotor angle of the motor, and adjusting the motor drive signal to achieve the target speed; the motor control board encapsulating the operating data into feedback data frames, parsing the feedback data and displaying the motor's operating status, and sending new control commands based on the feedback information to achieve real-time control and monitoring.

The objective is to achieve efficient control processing. [Solution] The frame-side control CPU executes a launch control process comprising at least the following: a third frame-side control load instruction that sets first information indicating permission to feed game balls in a fourth frame-side control register; a first frame-side control determination instruction that determines whether or not information indicating that balls are being removed is set in the communication system flag; a sixth frame-side control load instruction that sets the value of the fourth frame-side control register in the first frame-side control register when the determination result of the first frame-side control determination instruction is that information indicating that balls are being removed is set in the communication system flag; and a first frame-side control input / output instruction that writes the value of the first frame-side control register to the frame-side control output port.

The present invention provides a semiconductor integrated circuit device which includes a bus, a processor circuit module, and a circuit module targeted for power cutoff. The bus includes a bus core including a data signal line, and a predetermined bus interface circuit configured to connect the circuit module to the bus core. The predetermined bus interface circuit includes a transaction control circuit configured to control transactions for data transmission via the bus core, and a power supply control circuit including a power supply control register and configured to perform power supply control for the circuit module in accordance with a register value stored in the power supply control register. The power supply control circuit performs control to cut off power supply to the circuit module in response to a power cutoff instruction from the transaction control circuit under control of the processor circuit module.

Methods, systems, and apparatus for conditionally clean ancilla qubits in quantum circuits. In one aspect a quantum computing device performs, conditioned on a control register of qubits being on, a target operation on a target register of qubits. For at least two repetitions a first CNOT operation is performed, where a first dirty ancilla qubit is the target and a first subset of control register qubits acts as a control. A second CNOT operation is performed, where a second dirty ancilla qubit is a target, and the first dirty ancilla qubit and a second subset of control register qubits acts as a control. The target operation is applied, conditioned on the second dirty ancilla qubit being on, and a third CNOT operation is performed, where the second dirty ancilla qubit is a target, and the first dirty ancilla qubit and second subset of control register qubits acts as a control.

This application discloses a ZYNQ multi-core testing system based on a probe station, relating to the field of electrical performance testing technology. The method includes: shared memory; a first processing unit, used to receive instructions from a host computer via the LWIP protocol, and set the task registers of pending tasks according to the instruction frame header, while simultaneously polling the return control registers of each task; a second processing unit, used to poll the control registers of all tasks except the return control registers, and the working status of a third processing unit, setting the status flag of pending tasks to a pending state according to the polling results, and sending a soft interrupt to the third processing unit whose working state is idle; at least one third processing unit, used to execute a service task in response to the soft interrupt. This system schedules tasks through multi-core collaborative work logic and centrally and periodically monitors and manages the status, achieving automated and parallel testing of the chip.

This invention discloses a data operation structure and method. A request translation unit associates the processor with the cache and memory. This unit uses setting logic to convert complex request signals initiated by the processor into simple read / write signals, allowing the cache and memory to process only these simple signals, thus simplifying the design complexity of the cache and memory structure. Furthermore, by clearing the cache enable bit in the cache control register, the cache can be set to bypass mode. The bypassed cache does not respond to any operations, thus adapting to the low-power requirements of some applications. Simultaneously, the cache hit feedback signal directly controls the enable pin of the memory cell, blocking memory access. A cache hit disables the memory cell's enable, eliminating the need to initiate a memory access cancellation operation, further reducing the complexity of the memory control logic.

The application discloses a kind of based on shared memory mechanism and realizes FPGA and CPU data frame bidirectional transceiving method and device, the method is divided out in CPU and set size RAM space as shared memory, shared memory includes FPGA / CPU control register and corresponding read-write address space;FPGA is connected with CPU by SBD bus, after both sides power-on initialization is completed, according to control register state, read-write data in corresponding address space.The application improves bidirectional transmission speed without increasing cost and power consumption, solves the problems such as low transmission rate, unable to meet real-time and performance requirements when low-speed interface such as UART, SPI is used between existing low-end FPGA and CPU.

Embodiments of the present disclosure relate to a test architecture for electronic circuits, corresponding apparatus and methods. Test stimulus signals for application to at least one circuit under test are generated in a test stimulus generator set in accordance with test stimulus information loaded in a test stimulus register. The loading of test stimulus information in the test stimulus register is controlled in accordance with test programming information loaded in corresponding control registers of a control register set via a programming interface. Test stimulus generators are activated in accordance with the test programming information loaded in the control registers. Test result signals received from the at least one circuit under test are used to generate signature comparison signals which are compared with corresponding programmable signature reference signals stored in an input signature register set, the signature comparison signals being generated in response to a mismatch between the signature comparison signals generated from the test result signals and the corresponding reference signals.

Methods of performing matrix multiplication instruction in a processor having control register and vector registers whose length is indicated in the control register, the matrix multiplication being A×B=C, wherein A is an M×K matrix of elements with bitwidth-1, B is a K×N matrix of components with bitwidth-2, and C is an M×N matrix of items with bitwidth-3. The instruction codifies a multiplication type to be performed and has parameter-1, parameter-2 and parameter-3 indicating in which vector registers the elements, components and items are sequentially stored, respectively. Such methods comprise performing, in runtime, following steps: obtaining length from control register; decoding instruction to obtain multiplication type; determining bitwidth-1 and bitwidth-2 depending on multiplication type; determining value of M, N and K depending on the length and bitwidth-1 and bitwidth-2; and performing the matrix multiplication taking into account parameter-1, parameter-2 and parameter-3, bitwidth-1 and bitwidth-2, and value of M, N and K.

The application discloses a microcontroller unit (MCU) firmware grey box fuzzing test method. The method first establishes a high-fidelity peripheral simulator in a simulation execution environment, the peripheral simulator including peripheral registers, internal states and state machines, and determines the interrupt line enable state by jointly monitoring the global interrupt controller register and the peripheral interrupt control register to realize the controlled triggering of the peripheral interrupt. Secondly, the time when the firmware or DMA reads the peripheral data register is determined as an input consumption point during firmware execution, an incremental snapshot containing the processor register state, the peripheral state and the memory dirty page information is saved at the input consumption point, and only the input data that has not been read is mutated after the snapshot is restored. Finally, the test input is divided into multiple input streams corresponding to different peripherals or data registers, a probability distribution is constructed according to the access frequency of each input stream, and the input stream to be mutated is selected, so that the path exploration efficiency and the vulnerability discovery capability of the fuzzing test are improved.

The application provides a digital frequency jitter system, a chip and an electronic device, and relates to the technical field of wireless charging. The system comprises a frequency jitter control register module for storing frequency jitter configuration parameters; a low-frequency frequency jitter control module and a high-frequency frequency jitter control module for determining target low-frequency triangular wave frequency jitter values and target high-frequency frequency jitter values from low-frequency triangular wave frequency jitter values and high-frequency frequency jitter values according to actual carrier cycle numbers; a carrier control module for superimposing the target low-frequency triangular wave frequency jitter values and the target high-frequency frequency jitter values on carrier cycle configuration values, adjusting carrier edge point configuration information based on the obtained actual carrier cycle; and an output control module for outputting a target carrier signal based on the adjusted edge point information and the actual carrier cycle. The system aligns the low-frequency triangular wave frequency jitter values with the half-bit data bit cycle specified in the wireless charging protocol and synchronously aligns the high-frequency frequency jitter values with the low-frequency triangular wave frequency jitter values, thereby ensuring the synchronization of the frequency jitter operation and the FSK data bit cycle and reducing the bit error rate.

The present disclosure provides a display method for a picture, a timing control register, and an electronic device. The method includes: in a case of receiving a command for displaying a first picture reducing, by a timing control register, an original resolution to a preset resolution, and the first picture is a picture needing to be displayed at the same time as an original picture of a screen; sending the preset resolution to a display card, so that the display card outputs a picture with the preset resolution to obtain a second picture, and sends the second picture to the timing control register; and receiving the first picture and the second picture, and splicing first picture with the second picture into a picture with the original resolution to obtain a target picture, and sending the target picture to the screen for displaying.