186 results about "Control register" patented technology

The invention discloses an ARMv8-based virtual machine interrupt through routing method, which comprises the following steps that: a Hypervisor directly routes a physical interrupt to an EL1 through configuration, sets a top page table address of a vCPU (Virtual Central Processing Unit) and a Hypervisor control register at the same time, and sets a vcpudid flag bit for indicating whether the vCPU adopts a virtual interrupt injection mechanism or a physical interrupt through routing mechanism; and judging whether an interrupt through routing condition is met or not so as to determine whether an interrupt through routing mechanism or a virtual interrupt injection mechanism is adopted, periodically judging whether a switching condition is met or not when the interrupt through routing mechanism is adopted, and switching from the interrupt through routing mechanism to the virtual interrupt injection mechanism if the switching condition is met. The method is compatible with two interrupt controller specifications of GICv2 and GICv3, supports the virtual machine and the hypervisor to respectively and independently respond to respective corresponding interrupt requests, and meanwhile, the method has the capability of dynamically switching an interrupt routing mechanism during the system operation period, so that the flexibility of interrupt processing and the expandability of the system are improved.

The invention provides an EtherCAT slave station port identification and topology diagnosis system and method. Comprising a master station access interface module which is used for being in butt joint with an EtherCAT master station protocol stack and establishing a read-write channel for a data link layer register of a slave station controller; the port state acquisition module is used for analyzing to obtain a physical connection indication, a loop opening and closing state and a communication state of each port, and generating a port state record; the state analysis and control module is used for writing a port opening instruction into a data link layer control register when physical connection exists and a loop is closed, and selecting a preset recovery port of the system to execute register writing when all ports of the target slave station are detected to be in a closed state, so as to obtain a port judgment result; and the topology and diagnosis output module is used for establishing a connection relationship between slave stations based on the port judgment result to generate network topology data. According to the application, unified collection and analysis of registers, automatic judgment and recovery of ports, topology reconstruction and standardized diagnosis output can be realized.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention relates to the technical field of industrial robots and intelligent control, and discloses an explosion-proof robot MOS tube optimization driving control method and system based on an intelligent algorithm. The method comprises the following steps: acquiring multi-point temperature monitoring data of a power device to construct a virtual thermal gradient model; according to the virtual thermal gradient model, operation boundary parameter optimization calculation is carried out, and a dynamic safety threshold value is determined; acquiring real-time output state data of the driving system and generating a preliminary steady-state control strategy by combining the real-time output state data with the dynamic safety threshold; monitoring load efficiency feedback data, and triggering multi-target optimization of driving parameters by taking the dynamic safety threshold as a boundary constraint when an efficiency decline feature is identified, so as to obtain a to-be-verified driving parameter set; performing online prediction verification on the to-be-verified driving parameter set to generate a verification result identifier; and according to the verification result identifier, performing configuration updating or configuration keeping processing on a control register of the driving system during operation. The method effectively improves the system stability.

The invention discloses an FIR filter circuit structure, and the structure comprises a path control unit which generates a first control signal and a second control signal according to the number and order of filters which are customized by a user; the routing unit correspondingly transmits the filtering data received by the filtering data channel unit to the multiply-add unit array based on the first control signal; the multiply-add unit array comprises N multiply-add units, and the multiply-add units are connected through data selectors; the path control register unit is connected with a selection port of the data selector, and the path control register unit controls a data path of the multiply-add unit array through the data selector based on a second control signal; and the filtering result operation unit adds the multiplication and addition results of the corresponding multiplication and addition unit to obtain the filtering result of the corresponding filter. According to the invention, the multiplication and addition unit structure of the filter circuit can be customized according to user requirements, and the FIR filter circuit with low circuit resource ratio and high operation speed is configured.

The invention relates to the technical field of semiconductor design and manufacturing, in particular to an operation method and a design method of a multi-core chip and the multi-core chip. According to the technical scheme, circuit logics which can accept manufacturing defects are divided into the first logic group, and circuit logics which cannot accept manufacturing defects are divided into the second logic group; by reading the defect state of at least one computing core on the multi-core chip, the availability of a first logic group capable of accepting manufacturing defects in the computing core can be determined; and when the defect state indicates that the first logic group is unavailable, configuring a control register in the computing core to close the first logic group, and keeping a second logic group which is not accepted to manufacture defects in the computing core in a running state without influencing the functional circuit logic of the computing core. According to the technical scheme, the circuit logic, capable of accepting manufacturing defects, of the multi-core chip still has usability when the manufacturing defects occur, and the overall yield of manufacturing of the multi-core chip is improved in a disguised mode.

The invention discloses a crossbar switch control method based on cache information exchange, which relates to the technical field of integrated circuits and high-speed interconnection, and comprises an outlet flow control waterline register, an outlet congestion waterline register and a dequeue strategy optimization control register of an inlet receiving module in initialization configuration center control; the cache occupation amount of each outlet is monitored in real time, when the outlet cache is in an early warning state, an inlet dequeue strategy is controlled, and outlet data messages in a non-early warning state are scheduled preferentially; the cache occupation and release information is interacted in real time, and the early warning state is updated through the change of an occupation amount register; and dynamically optimizing an entrance dequeue sequence based on an exit cache early warning state, and performing decentralized flow cooperative control. The problem of performance loss of a traditional Crossbar switching chip caused by outlet bottleneck is effectively solved, and a high-performance and high-reliability switching chip technical scheme is provided for the fields of data center lossless interconnection, 5G core network packet switching and the like.

The invention belongs to the field of switch chips, and relates to a hardware and software combined PCIE address translation and networking design device and method, the hardware and software combined PCIE address translation and networking design device comprises an address translation unit, a built-in CPU and firmware and a TLP transceiving unit, the address translation unit comprises a control register and an address or BDF translation module for implementing TLP address or BDF translation; the firmware is used for completing the simulation of the iEP, and the simulation method is that software is used for completing the response to a received configuration request TLP, so that a DSP and an EP are simulated; and the TLP receiving and transmitting unit connects the built-in CPU to a switching network, so that the built-in CPU receives and transmits a TLP data packet. According to the PCIe switching chip, a tree topology structure of a traditional PCIe switching chip can be broken through, and any needed network topology structure can be flexibly connected through software configuration; a plurality of hosts and devices can be connected at any port as required; the required iEP is realized by using internal firmware, the function of the iEP can be realized by more flexible programming, and the design cost is reduced compared with the method for realizing the iEP by using hardware.

The invention provides an SoC system control method and device, electronic equipment and a readable storage medium, and the method comprises the steps: controlling a CPU large core to generate a control instruction, and writing the control instruction into a register; the control register analyzes the control instruction, determines at least one target function module associated with the control instruction, generates a corresponding enable signal and sends the enable signal to a control circuit corresponding to each target function module; and aiming at the control circuit of each target function module, controlling the control circuit to receive and analyze the corresponding enable signal, generating control information and sending the control information to the corresponding target function module, so that each target function module is configured according to the control information and executes the control instruction. Therefore, the configuration time of the CPU for configuring the functional modules one by one through the on-chip internet can be reduced, and the control efficiency of the SoC system is further improved.

Aggregated subordinate control over a serial bus is described in the present disclosure. Herein, a serial bus circuit includes multiple subordinate circuits each configured to operate based on a respective one or more control bits programmed into a respective control register(s). Understandably, if the control register(s) in each of the subordinate circuits is programmed individually through multiple bus telegrams, then much of the already limited bandwidth of the serial bus will be wasted. In this regard, in embodiments disclosed herein, a single bus telegram can be configured to carry an aggregated control word that can simultaneously program the control register(s) in multiple subordinate circuits. As a result, it is possible to reduce bus telegrams for programming the subordinate circuits, thus helping to conserve bandwidth of the serial bus.

The invention discloses a DDR5 dynamic ODT regulation and control method, device and equipment based on multi-working-condition perception and a medium, and relates to the field of computer memories, and the method comprises the steps: obtaining a power supply ripple value and a DRAM chip temperature value of a system; querying a preset ripple-temperature-ODT value corresponding table by taking the power supply ripple value and the DRAM chip temperature value as a joint index to obtain a corresponding target ODT value; and writing the target ODT value into an ODT control register of the DDR5 chip through a mode register setting command. Multi-working-condition sensing is achieved by synchronously monitoring power supply ripples and chip temperature, the optimal ODT value is directly obtained based on a joint index query preset optimization mapping table, and finally configuration is written through a standard MRS command. Comprehensive state monitoring, pre-stored expert knowledge and a standard hardware interface are combined, microsecond-level fast decision making and reliable regulation and control are achieved, on the premise that an existing DDR5 standard is completely compatible, signal integrity is effectively guaranteed, system power consumption is optimized, and the overall performance and energy efficiency of a memory subsystem are improved.

The invention provides an error frame injection device, method and system, and the device comprises a control register module, an error frame memory module and a medium access control module which are respectively constructed in a field programmable gate array. The control register module is used for receiving an Ethernet data frame and an error frame injection strategy, generating an Ethernet error frame, and generating an injection control signal of the Ethernet error frame according to an error injection frequency if an injection trigger condition is monitored to be established; the error frame memory module is used for receiving and storing Ethernet error frames; and the medium access control module is used for responding to the injection control signal, reading the Ethernet error frame from the error frame memory module, and injecting the Ethernet error frame into the equipment to be tested for testing. By integrating the control register module, the error frame memory module and the medium access control module in the field programmable gate array, Ethernet error frame injection is realized, and an efficient, comprehensive and economical test means is provided for high-speed Ethernet equipment.

Aspects of the disclosure are directed to dynamic memory prefetching. In accordance with one aspect, the disclosure includes a main memory configured to store data; a memory hierarchy coupled to the main memory, the memory hierarchy configured to augment the main memory; and a trusted zone element coupled to the memory hierarchy, the trusted zone element configured to read a shared memory to determine a specific control register and one or more prefetch values based on a secure monitor call (SMC). In another aspect, the disclosure includes reading a shared memory to determine a specific control register and one or more prefetch values based on a secure monitor call (SMC); and writing the one or more prefetch values to an exception level register.

The invention relates to the technical field of network communication, and discloses an interrupt control method and device, equipment and a medium, and the method comprises the steps: if an interrupt event is monitored, determining a target register for controlling the interrupt event according to a preset mapping relation, and dividing the target register into a plurality of sub-registers; determining a target sub-register corresponding to the interrupt event based on the priority of the interrupt event; and timing based on the preset delay time of the target sub-register, and reporting the interrupt vector to a host based on the state of the interrupt vector after timing expires. According to the method, the interrupt control register is dynamically divided into a plurality of sub-registers capable of flexibly configuring the bit width, and the interrupt events are bound with the sub-registers according to the priorities of the interrupt events, so that the processing speed of the interrupt events with different priorities is adjusted on the premise that the hardware resource area is not changed, and the host performance is improved.

A computing system is disclosed, comprising a host computer and multiple CGRPs (coarse-grained reconfigurable architecture processors) connected to the host computer through external communication links. Each CGRP includes an internal network, external interface circuits, memory interface circuits, arrays of configurable units, hang detection circuits, force-quit controllers, and a network recovery circuit with control registers. The host computer is programmed to configure and execute applications across the arrays of configurable units in both CGRPs. In case of a hang detection in one CGRP, the network recovery circuit initiates a force quit process and notifies the host computer. Additionally, the network recovery circuit compares application IDs and halts execution in the other CGRP if necessary. This system provides efficient failure tolerance and recovery mechanisms for parallel processing applications.

The invention discloses an SSD low-power-consumption control method and device and a medium, and relates to the technical field of SSDs, and the method comprises the steps that a system-on-chip receives an effective power-off notification signal from a host through a preset universal input and output pin; in response to the effective power-off notification signal, the system-on-chip writes the data in the cache into a nonvolatile storage medium of the solid state disk; then, the system-on-chip sends a control instruction to the power management chip through the communication bus, and a power-off control register of the power management chip is configured to be in an enabled state; the power management chip responds to the power-off control register to be in the enabled state, all power output except the power input by the power management chip in the solid state disk is cut off, and the solid state disk enters a low-power-consumption state. The problem that the power consumption of a traditional partial power-off scheme is not reduced thoroughly is solved, meanwhile, the hardware cost and complexity caused by a scheme depending on a standby power capacitor are avoided, and extreme low-power-consumption control on the premise that data safety is guaranteed is achieved.

The application provides an optical module and a remote optical module loopback control method based on double MCUs. When a first master MCU of a near-end optical module modifies a value of a loopback message enable register to a first value on a sending end host computer, the first master MCU generates an update enable command. A loopback control register stores a loopback control value written by the sending end host computer and writes the loopback control value into a first slave MCU. The first slave MCU receives the update enable command from the first master MCU and generates a loopback control command according to the loopback control value. The loopback control command stored in the first slave MCU is loaded into a first optical signal. The abnormal positioning of a remote device in an optical link is completed at a local device end. The double MCU control function is adopted, the communication response function of the slave MCU is turned on and off, the slave MCU is not disturbed when sending and receiving messages by the host computer and the master MCU, and therefore the success rate of the loopback control command transmission is improved.

In a general aspect, a processor includes a plurality of control registers, an instruction processing pipeline operatively coupled to the plurality of control registers, and a pipeline flush control unit operatively coupled to the instruction processing pipeline. The pipeline flush control unit is configured to record an indication of a first instruction in response to completion of execution of the first instruction by the instruction processing pipeline. The first instruction is configured to write to a first control register of the control registers. The pipeline flush control unit is also configured to identify a second instruction in the instruction processing pipeline before completion of execution of the second instruction and determine whether the second instruction conflicts with the first instruction based on a predetermined set of criteria. If the second instruction is determined to conflict with the first instruction, the pipeline flush control unit initiates a flush of the instruction processing pipeline.

The embodiment of the present application provides a single bus communication component and a slave device, data communication channels adopting a SWI bus protocol and a 1-WIRE bus protocol are established by arranging a data converter, a SWI transceiver, a 1-WIRE transceiver, a SWI ROM state machine, a 1-WIRE ROM state machine, a receiving buffer and a sending buffer in the single bus communication component, and the slave device can flexibly select corresponding data communication channels according to the bus protocol adopted by a host by arranging control information in a control register of a microprocessor in the slave device, so that the versatility of the slave device is improved.

The invention provides a processor system and an interrupt response method. In the processor system, an interrupt controller is used for setting the state of a control register, receiving an interrupt request signal which is sent from the outside and is used for requesting to execute an interrupt service program, setting the state of the control register to be a first state value when the interrupt request signal is received, and executing the interrupt service program after the interrupt server program is executed. Setting the state of the control register as a second state value; the multiplexer is used for reading the state value of the control register, when the read state value of the control register is a first state value, the multiplexer is communicated with the shadow register group and the arithmetic unit, and when the read state value of the control register is a second state value, the multiplexer is communicated with the main register group and the arithmetic unit; the main register group is used for storing data when the main program is operated; and the shadow register group is used for storing data when the interrupt server program runs. The delay in the interrupt response process can be reduced, and the system performance is improved.

The embodiment of the invention discloses a chip, a PCIe link error processing method and a chip system, relates to the technical field of integrated circuits, and aims to facilitate accurate fault isolation and reduce the service interruption range. The chip comprises: a link error processing module configured to keep a PCIe port in a connection state in response to a detected downstream link error event of the PCIe port of the chip, and send an interrupt signal to an on-chip microcontroller through an internal bus of the chip; the interrupt signal carries an error source identifier for indicating a bus number, an equipment number and a function number of the fault equipment; the on-chip microcontroller is configured to search a device tree topology table corresponding to the PCIe port according to the error source identifier, and locate a target port to which a bus connected with the fault device belongs; and disconnecting the PCIe link between the fault device and the target port through the link control register of the target port. The PCIe bus error detection method and device are suitable for the scene of PCIe bus error detection.

An apparatus comprises processing circuitry configured to perform data processing in response to instructions executed in one of a plurality of exception levels; system registers configured to store s

The present invention provides a quantum system error detection device, the device comprising: a control register for receiving information representing a quantum state of a control qubit and outputting an operation result; an auxiliary register for receiving, on a one-to-one basis, information representing a quantum state of a target qubit; a CNOT gate connected to the control register and the auxiliary register; a first detector connected to the control register and configured to measure a quantum state of the control qubit to which the CNOT gate is applied; a second detector connected to the auxiliary register and configured to measure a quantum state of the auxiliary qubit to which the CNOT gate is applied; a probability calculation unit for calculating probabilities of quantum states of the control qubit and the target qubit from measurement results of the first detector and the second detector; and an error rate calculation unit for calculating error rates of quantum state initialization, the CNOT gate, and quantum measurement from the probabilities calculated by the probability calculation unit.

Systems or methods of the present disclosure may provide for analyzing or monitoring one or more frequencies of one or more clocks. For example, a clock analysis system includes a control register that stores a frequency indication for a first clock, and an edge counter and a window counter that count respective numbers of edges of the first clock and a second clock within a particular window. The clock analysis system also includes a status register that stores indications of the number of edges from the edge counter and the window counter. The clock analysis system further includes an application processor that determines a ratio between the number of edges of the first clock and the number of edges of the second clock, determines a frequency of the first clock based on the ratio, and transmits an indication of the frequency to a peripheral device for display.

The present disclosure provides a serialization and deserialization method of an FPGA-based IPU acceleration service grid. The serialization and deserialization method of the FPGA-based IPU acceleration service grid comprises: determining all message objects of remote procedure calls to be sent and received; allocating a sending descriptor ring and a receiving descriptor ring and configuring a control register through a memory-mapped I / O operation; defining a message format of a remote procedure call through a domain-specific language for serialization and deserialization; when in a transmission mode, creating a sending descriptor and filling it into the sending descriptor ring; the FPGA obtains the sending descriptor from the sending descriptor ring and sends encoded data to a system-on-chip; and the system-on-chip sends the encoded data through a network transmission protocol. The embodiments of the present disclosure solve the problems of performance bottleneck, high delay and high CPU resource occupation in the prior art.

A compute array employs localized redundant columns within each compute row to replace defective columns through software-controlled multiplexers. The multiplexers, located in inter-row regions, enable substitution of redundant columns in the same compute row under control of a redundancy management system implemented in software, firmware, or hardware. A general-purpose controller configures the multiplexers by writing to control registers based on defect-map information obtained from test routines. This distributed but software-orchestrated redundancy system maintains timing consistency, simplifies layout, and provides high-yield fault tolerance with minimal additional hardware.

A processor circuit that includes a plurality of register circuits and an event handler circuit is disclosed. The event handler circuit may detect a processing event that causes the processor circuit to halt execution of a current instruction and transfer control to a kernel. In response to a detection of the processing event, the event handler circuit may store a program counter value corresponding to the current instruction, information indicative of a cause of the processing event, and a size of the current instruction in corresponding register circuits of the plurality of register circuits.

This application provides a clock peak shifting control device, control method, and chip. The device includes a first selection module, a first delay module, a second selection module, and a first latch module. The first delay module generates a target delay clock signal. The first selection module selects between a test clock signal and the target delay clock signal. The second selection module switches between different operating modes of the chip to obtain a drive clock signal. The latch module controls the timing of different groups of registers. The drive clock signal provides a clock signal for each register in each register group, ensuring that registers in each group do not flip at the same time. This reasonable peak shifting control of register flipping time effectively reduces the peak power consumption during the shift process.

In an embodiment, a circuit includes a data path including at least a first lane of a first width and a second lane of a second, larger, width; an execution unit to execute a first instruction on data of the first width or less using the first lane, and to execute a second instruction on data greater than the first width and less than or equal to the second width using the second lane; and a control register that stores a value indicating which of the first and second lanes to be used in instruction execution by the execution unit. The circuit is configured to, based on the value stored in the control register, power off the first lane when the execution unit executes the second instruction but not the first instruction, and power off the second lane when the execution unit executes the first instruction but not the second instruction.

A method of temporal freedom from interference (FFI) for safe tasks is described. The method includes writing an incoming safe task to a safe task field of a control register. The method also includes determining a safe partition and a non-safe partition of processing elements (PEs). The method further includes determining priorities of currently executed safe tasks in the safe partition and non-safe tasks in a non-safe partition of the PEs. The method also includes preempting a currently executed safe task if a priority of the currently executed safe task is less than a priority of the incoming safe task.