93 results about "Control register" patented technology

The invention discloses a crossbar switch control method based on cache information exchange, which relates to the technical field of integrated circuits and high-speed interconnection, and comprises an outlet flow control waterline register, an outlet congestion waterline register and a dequeue strategy optimization control register of an inlet receiving module in initialization configuration center control; the cache occupation amount of each outlet is monitored in real time, when the outlet cache is in an early warning state, an inlet dequeue strategy is controlled, and outlet data messages in a non-early warning state are scheduled preferentially; the cache occupation and release information is interacted in real time, and the early warning state is updated through the change of an occupation amount register; and dynamically optimizing an entrance dequeue sequence based on an exit cache early warning state, and performing decentralized flow cooperative control. The problem of performance loss of a traditional Crossbar switching chip caused by outlet bottleneck is effectively solved, and a high-performance and high-reliability switching chip technical scheme is provided for the fields of data center lossless interconnection, 5G core network packet switching and the like.

The invention provides an SoC system control method and device, electronic equipment and a readable storage medium, and the method comprises the steps: controlling a CPU large core to generate a control instruction, and writing the control instruction into a register; the control register analyzes the control instruction, determines at least one target function module associated with the control instruction, generates a corresponding enable signal and sends the enable signal to a control circuit corresponding to each target function module; and aiming at the control circuit of each target function module, controlling the control circuit to receive and analyze the corresponding enable signal, generating control information and sending the control information to the corresponding target function module, so that each target function module is configured according to the control information and executes the control instruction. Therefore, the configuration time of the CPU for configuring the functional modules one by one through the on-chip internet can be reduced, and the control efficiency of the SoC system is further improved.

The invention discloses a DDR5 dynamic ODT regulation and control method, device and equipment based on multi-working-condition perception and a medium, and relates to the field of computer memories, and the method comprises the steps: obtaining a power supply ripple value and a DRAM chip temperature value of a system; querying a preset ripple-temperature-ODT value corresponding table by taking the power supply ripple value and the DRAM chip temperature value as a joint index to obtain a corresponding target ODT value; and writing the target ODT value into an ODT control register of the DDR5 chip through a mode register setting command. Multi-working-condition sensing is achieved by synchronously monitoring power supply ripples and chip temperature, the optimal ODT value is directly obtained based on a joint index query preset optimization mapping table, and finally configuration is written through a standard MRS command. Comprehensive state monitoring, pre-stored expert knowledge and a standard hardware interface are combined, microsecond-level fast decision making and reliable regulation and control are achieved, on the premise that an existing DDR5 standard is completely compatible, signal integrity is effectively guaranteed, system power consumption is optimized, and the overall performance and energy efficiency of a memory subsystem are improved.

The invention provides an error frame injection device, method and system, and the device comprises a control register module, an error frame memory module and a medium access control module which are respectively constructed in a field programmable gate array. The control register module is used for receiving an Ethernet data frame and an error frame injection strategy, generating an Ethernet error frame, and generating an injection control signal of the Ethernet error frame according to an error injection frequency if an injection trigger condition is monitored to be established; the error frame memory module is used for receiving and storing Ethernet error frames; and the medium access control module is used for responding to the injection control signal, reading the Ethernet error frame from the error frame memory module, and injecting the Ethernet error frame into the equipment to be tested for testing. By integrating the control register module, the error frame memory module and the medium access control module in the field programmable gate array, Ethernet error frame injection is realized, and an efficient, comprehensive and economical test means is provided for high-speed Ethernet equipment.

A computing system is disclosed, comprising a host computer and multiple CGRPs (coarse-grained reconfigurable architecture processors) connected to the host computer through external communication links. Each CGRP includes an internal network, external interface circuits, memory interface circuits, arrays of configurable units, hang detection circuits, force-quit controllers, and a network recovery circuit with control registers. The host computer is programmed to configure and execute applications across the arrays of configurable units in both CGRPs. In case of a hang detection in one CGRP, the network recovery circuit initiates a force quit process and notifies the host computer. Additionally, the network recovery circuit compares application IDs and halts execution in the other CGRP if necessary. This system provides efficient failure tolerance and recovery mechanisms for parallel processing applications.

The invention discloses an SSD low-power-consumption control method and device and a medium, and relates to the technical field of SSDs, and the method comprises the steps that a system-on-chip receives an effective power-off notification signal from a host through a preset universal input and output pin; in response to the effective power-off notification signal, the system-on-chip writes the data in the cache into a nonvolatile storage medium of the solid state disk; then, the system-on-chip sends a control instruction to the power management chip through the communication bus, and a power-off control register of the power management chip is configured to be in an enabled state; the power management chip responds to the power-off control register to be in the enabled state, all power output except the power input by the power management chip in the solid state disk is cut off, and the solid state disk enters a low-power-consumption state. The problem that the power consumption of a traditional partial power-off scheme is not reduced thoroughly is solved, meanwhile, the hardware cost and complexity caused by a scheme depending on a standby power capacitor are avoided, and extreme low-power-consumption control on the premise that data safety is guaranteed is achieved.

An apparatus comprises processing circuitry configured to perform data processing in response to instructions executed in one of a plurality of exception levels; system registers configured to store s

The present invention provides a quantum system error detection device, the device comprising: a control register for receiving information representing a quantum state of a control qubit and outputting an operation result; an auxiliary register for receiving, on a one-to-one basis, information representing a quantum state of a target qubit; a CNOT gate connected to the control register and the auxiliary register; a first detector connected to the control register and configured to measure a quantum state of the control qubit to which the CNOT gate is applied; a second detector connected to the auxiliary register and configured to measure a quantum state of the auxiliary qubit to which the CNOT gate is applied; a probability calculation unit for calculating probabilities of quantum states of the control qubit and the target qubit from measurement results of the first detector and the second detector; and an error rate calculation unit for calculating error rates of quantum state initialization, the CNOT gate, and quantum measurement from the probabilities calculated by the probability calculation unit.

The present disclosure provides a serialization and deserialization method of an FPGA-based IPU acceleration service grid. The serialization and deserialization method of the FPGA-based IPU acceleration service grid comprises: determining all message objects of remote procedure calls to be sent and received; allocating a sending descriptor ring and a receiving descriptor ring and configuring a control register through a memory-mapped I / O operation; defining a message format of a remote procedure call through a domain-specific language for serialization and deserialization; when in a transmission mode, creating a sending descriptor and filling it into the sending descriptor ring; the FPGA obtains the sending descriptor from the sending descriptor ring and sends encoded data to a system-on-chip; and the system-on-chip sends the encoded data through a network transmission protocol. The embodiments of the present disclosure solve the problems of performance bottleneck, high delay and high CPU resource occupation in the prior art.

A compute array employs localized redundant columns within each compute row to replace defective columns through software-controlled multiplexers. The multiplexers, located in inter-row regions, enable substitution of redundant columns in the same compute row under control of a redundancy management system implemented in software, firmware, or hardware. A general-purpose controller configures the multiplexers by writing to control registers based on defect-map information obtained from test routines. This distributed but software-orchestrated redundancy system maintains timing consistency, simplifies layout, and provides high-yield fault tolerance with minimal additional hardware.

This application provides a clock peak shifting control device, control method, and chip. The device includes a first selection module, a first delay module, a second selection module, and a first latch module. The first delay module generates a target delay clock signal. The first selection module selects between a test clock signal and the target delay clock signal. The second selection module switches between different operating modes of the chip to obtain a drive clock signal. The latch module controls the timing of different groups of registers. The drive clock signal provides a clock signal for each register in each register group, ensuring that registers in each group do not flip at the same time. This reasonable peak shifting control of register flipping time effectively reduces the peak power consumption during the shift process.

A method of temporal freedom from interference (FFI) for safe tasks is described. The method includes writing an incoming safe task to a safe task field of a control register. The method also includes determining a safe partition and a non-safe partition of processing elements (PEs). The method further includes determining priorities of currently executed safe tasks in the safe partition and non-safe tasks in a non-safe partition of the PEs. The method also includes preempting a currently executed safe task if a priority of the currently executed safe task is less than a priority of the incoming safe task.

This provides a new power cutoff technology for semiconductor integrated circuit devices. [Solution] The present invention is a semiconductor integrated circuit device comprising a bus, a processor circuit module, and a circuit module to be power-off. The bus comprises a bus core including data signal lines and a predetermined bus interface circuit for connecting the circuit module to the bus core. The predetermined bus interface circuit comprises a transaction control circuit for controlling transactions related to data transmission via the bus core, and a power control circuit including a power control register, which controls the power supply to the circuit module according to the register value held by the power control register. The power control circuit, under the control of the processor circuit module, controls the power supply to the circuit module to be cut off in accordance with a power-off instruction from the transaction control circuit.

A disclosed computer-implemented method may include loading a pair of input vectors of into a respective pair of registers included in a processor, each input vector associated with a different shared scale term. The method may also include storing a shared scale term corresponding to at least one of the pair of input vectors within at least one control register of the processor. The method may also include performing a vector operation that utilizes the pair of input vectors by accessing the at least one control register to retrieve the shared scale term as part of the vector operation Various other methods, systems, and computer-readable media are also disclosed.

A method for managing a failure condition at a host includes detecting an occurrence of a host critical failure event at the host, configuring at least one panic bit of a host panic control register of a device, based on the detecting of the occurrence of the host critical failure event, and issuing, to the device, at least one input / output (I / O) read / write command.

Isolation circuitry to implement testing in a semiconductor device is described. In certain examples, a computing system includes a device circuit to generate a resultant and store the resultant in a resultant register; a power supply; a controller circuit to, in response to a power reset indication for the power supply, send a read command to cause the device circuit to return the resultant from the resultant register to the controller circuit; and an isolation circuit comprising a control register that when set to a first value allows the device circuit to receive the read command, and when set to a second value allows the device circuit to receive a test command to cause the device circuit to perform a test operation and ignore the read command.

Embodiments relate to atomic memory operations with floating point values. An example processor comprises: a control register to store rounding mode and denormal mode control bits to indicate a rounding mode and denormal value processing mode; fetch circuitry to fetch a remote atomic operation (RAO) floating point (FP) instruction comprising a memory location to store at least one FP result value; decode circuitry to decode the instruction and scheduling circuitry to offload the instruction to an execution engine external to the logical processor or to schedule the decoded instruction for local execution, wherein an indication of the rounding mode and denormal value processing mode is communicated to the execution engine, the indication to be communicated by a transfer of one or more of the rounding mode control bits and denormal mode control bits to a storage coupled to the execution engine, or to be communicated in the message.

This invention discloses an embedded SoC-level real-time monitoring and analysis device, comprising a bus comparator, a system event counter, and a control register set. The bus comparator acquires access signals from the address bus, data bus, and instruction bus in real time and compares them with preset matching rules. Upon matching, it generates a trigger signal to drive the event status register to record, output interrupt signals, or debug signals, and serves as the input event for the system event counter. The system event counter monitors various events generated during operation, and generates a trigger signal when the monitoring result equals a preset reference value. The control register set configures the matching conditions of the bus comparator, sets the counting mode of the system event counter, and reads the comparison status, event counting results, and related monitoring information through the bus interface. This invention introduces a configurable event capture mechanism and multiple counting modes at the hardware level, reducing reliance on software debugging and improving the real-time performance of monitoring and analysis.

This invention provides an improved method, system, and computer program for performing matrix multiplication computer instructions. [Solution] The method is a processor having a control register and a vector register whose length is indicated in the control register, in which a matrix operation A × B = C is performed, where A is an M × K matrix with elements of a first bit width, B is a K × N matrix with elements of a second bit width, and C is an M × N matrix with elements of a third bit width. The instruction has three parameters that encode the type of multiplication to be performed and indicate which vector register to sequentially store the elements of each matrix in. The method also obtains the length from the control register, decodes the instruction to obtain the multiplication type, determines the first and second bit widths according to the multiplication type, determines the values ​​of M, N, and K according to the length and the first and second bit widths, and performs matrix multiplication considering the three parameters, the first and second bit widths, and the values ​​of M, N, and K.

The application discloses a processor load preheating and exiting method, device, equipment and storage medium, and is applied to the field of processor control, and comprises the following steps: setting a load preheating / exiting control register in a global register of a processor, and configuring a field of the load preheating / exiting control register based on a task load; when reading that the load preheating field is in an activated state, controlling a calculation unit of the processor to execute an invalid calculation task with an increased task amount; and when reading that the load exiting field is in the activated state, controlling the calculation unit of the processor to execute an invalid calculation task with a decreased task amount. According to the method, meaningless calculation tasks are executed by the processor before and after starting or stopping heavy work loads, the load is gradually and slowly increased or decreased, the transition to a normal working state is smoothed, a complex power management strategy is not needed, and the starting stability and reliability of the system can be obviously improved.

A display control circuit and a display control method are provided. The display control circuit includes a storage unit, a control register, a local dimming control register, and a microcontroller unit. The storage unit is configured to store a plurality of predefined LDC setting data. The control register is configured to store a first mode setting value. The local dimming control register is configured to store a LDC setting data that is to be applied in synchronization with a frame synchronization signal. The microcontroller unit is coupled to the control register and the local dimming control register. The microcontroller unit is configured to read a first predefined LDC setting data of the plurality of predefined LDC setting data stored in the storage unit according to the first mode setting value and write the first predefined LDC setting data into the local dimming control register.

The application provides a virtual information processing method, device and storage medium. The method comprises the following steps: a host system creates a virtual device instance, allocs hardware resources and a continuous memory area for the virtual device instance, generates and stores first configuration information corresponding to a physical hardware control register area and second configuration information indicating the memory area, and transmits a real physical base address of the memory area to the virtual device instance; after a virtual machine binds the virtual device instance, the virtual machine completes zero-copy data processing according to the real physical base address, the first configuration information and the second configuration information. Through virtual device instantiation, independent memory allocation and direct transmission of a physical base address, the virtual machine can directly initiate a hardware DMA operation, the data copying overhead is saved, a single physical hardware can be safely shared by multiple virtual machines, and the I / O performance of a virtualization environment and the hardware utilization rate are improved.

Techniques for implementing instructions for a trust domain implemented by a processor are described. In certain examples, a hardware processor core, that implements a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory, includes a debug register; a control register; decoder circuitry to decode a first single instruction into a first decoded instruction, the first single instruction having a field to indicate a data structure to store a control state of a trust domain and a debug state of the trust domain, and an opcode to indicate execution circuitry is to load the control state of the trust domain from the data structure into the control register and load the debug state of the trust domain from the data structure into the debug register; and the execution circuitry to execute the first decoded instruction according to the opcode.

The embodiment of the application provides a data operation bit width expansion method and device, relates to the computer technical field, and comprises the following steps: reading variable vector information in a vector width control register, determining a maximum data operation bit width after expansion based on the variable vector information.If the width of to-be-processed data is greater than an original data operation bit width and less than or equal to the maximum data operation bit width, then based on the width of the to-be-processed data and the bit width of a single operation unit, the target number of operation units used for processing the to-be-processed data is determined.The target number of operation units is written into an operation unit control register after being reduced by one, so as to control the start of the target number of operation units, and the to-be-processed data is processed.Two control registers are newly defined to realize variable vector expansion without changing the original mode, and the data operation bit width is expanded from the original data operation bit width to a larger data operation bit width, so that the parallelization capability of data processing is improved without the need of instruction set expansion and code rewriting.

The objective is to achieve efficient control processing. [Solution] The frame-side control CPU executes a counting notification transmission process which consists of at least the following: a ninth frame-side control load instruction that loads a counting subtraction counter into the first frame-side control register; a tenth frame-side control load instruction that saves the counting subtraction counter to the address of the frame-side control transmit buffer with 3 added to it; a third frame-side control call instruction that calls and executes an SC transmit process that transmits the contents of the frame-side control transmit buffer to the card unit via the first frame-side control serial port; a fifteenth frame-side control load instruction that sets information indicating the completion of counting into the second frame-side control pair register; and a sixth frame-side control call instruction that calls and executes a main transmit process that transmits the contents of the second frame-side control pair register to the game control board via the second frame-side control serial port.

A technique for controlling access to a set of memory-mapped control registers is described. An apparatus has processing circuitry for executing program code to perform data processing operations and a set of memory-mapped control registers for storing control information for controlling operation of the processing circuitry when executing the program code. In addition, a lock register is for storing a lock value. The processing circuitry is arranged to execute store instructions for performing write operations to a memory address space, the store instructions being of a plurality of types. However, on setting the lock value, the processing circuitry is arranged to prevent the write operations from being performed unless a write operation to change the control information in the memory-mapped control registers occurs as a result of executing a store instruction from a first subset of the plurality of types of store instruction. This significantly reduces the likelihood of an attacker seeking to exploit a software vulnerability to change the control information in the memory-mapped control registers.

The application relates to the technical field of motor control and serial communication, and provides a low-voltage small motor rotating speed monitoring method based on UART communication. The method comprises the following steps: sending a communication handshake data frame to a motor control board through a serial port to establish a stable serial port communication connection; generating a motor rotating speed setting instruction according to the equipment operation requirement and sending the motor rotating speed setting instruction to the motor control board through the serial port; receiving the data frame by the motor control board, obtaining an instruction code and a target rotating speed parameter through analysis and writing the instruction code and the target rotating speed parameter into a control register; according to the target rotating speed value, executing three proportional integral closed loop control algorithms of constant rotating speed, current limiting and power limiting, adopting a magnetic field oriented control mode to accurately control phase current and rotor angle of the motor, adjusting motor driving signals to realize the target rotating speed; encapsulating running data into feedback data frames by the motor control board, analyzing the feedback data, displaying the motor running state, sending new control instructions according to the feedback information, and realizing real-time control and monitoring.

The invention provides a 3D stacked memory drive test system, a drive test method and a storage medium, and the drive test system comprises a scanning register module which comprises a register and is used for controlling the register to receive a high-level starting pulse signal, switching an output signal of the register from a low level to a high level in response to the starting pulse signal to obtain a test signal; the driving module comprises a driver, the register is electrically connected with the driver, and the driving module is used for controlling the driver to receive a test signal transmitted by the register, obtaining an enabling control signal in response to the test signal, and controlling the driver to be in a conducting state based on the enabling control signal; and the current testing module is electrically connected with the driver, and the current testing module is used for detecting the current value of a circuit where the driver is located and determining the driving state of the driver based on the current value. According to the invention, accurate detection of the driving state of the driver can be realized in the intermediate detection stage, so that the product yield is improved, and the production cost is reduced.

The utility model discloses an in-memory computing accelerator and system, the in-memory computing accelerator comprises a four-dimensional in-memory computing processor and a configuration control register file, and the configuration control register file is connected with the four-dimensional in-memory computing processor; the four-dimensional in-memory computing processor comprises four in-memory computing units, and the four in-memory computing units form a dynamic parallel structure; the configuration control register file is used for acquiring target configuration corresponding to a target neural network and sending the target configuration to the four-dimensional in-memory calculation processor; and the four-dimensional in-memory computing processor is used for performing configuration according to the target configuration, so that the four in-memory computing units form a target parallel structure. The four-dimensional in-memory calculation unit in the accelerator can execute at least one neural network reasoning calculation process on the input data aiming at the input data of a certain neural network, so that the utilization rate of different operator calculation requirements is improved.

The application provides a kind of grey box fuzzing test method and system based on Intel-PT and Syzkaller, method includes: first fuzzing test engine starts test cycle, constantly test and synchronize test progress to manager;Manager sends the new use case found by second fuzzing test engine to first fuzzing test engine in response to the poll request of first fuzzing test engine, the effective queue of first fuzzing test engine is updated, start to generate new use case and test;First fuzzing test engine sends new use case to executor, executor prepares to execute test;Executor identifies kernel address range before executing test, collects static storage area of new use case, applies to start PT tracking function by super call;Intercept control register setting request, obtain the value of control register, and assign the value of control register to the parameter of super call, the value of control register is the page table base address of tracking system;Process super call to set the kernel address range of tracking, set page table base address, start PT tracking;Executor starts to parse and execute input use case, real-time call registered parsing function to complete parsing, fill in static storage area;After the execution of multiple rounds of system call of executor, updated coverage information is synchronized to first fuzzing test engine.The grey box fuzzing test method and system based on Intel-PT and Syzkaller provided by the application can be used for closed source version linux system binary grey box fuzzing test, to form effective feedback information closed loop.