494 results about "Cyclic redundancy check" patented technology

The invention relates to the technical field of data encryption, and discloses a data encryption protection system and method for intelligent controller hardware, and the method comprises the steps: generating a random confusion factor based on a real-time operation state through constructing a dynamic confusion algorithm, and carrying out the nonlinear transformation of original data; implementing a fragment encryption strategy, dividing fragments according to data sensitivity levels, and adopting a heterogeneous encryption algorithm; generating a dynamic binding key in combination with the environment parameters and the hardware unique identifier; hardware-level integrity check is executed, and data and hardware are verified through cyclic redundancy check codes and hardware fingerprints; establishing a self-adaptive key updating mechanism; performing multi-layer defense linkage; and implementing anti-side channel protection, and constructing a security audit log. According to the method, the hardware data security of the intelligent controller is comprehensively guaranteed, various security threats are effectively resisted, and the data confidentiality, integrity and availability are improved.

The invention discloses an adaptive modulation anti-multipath unmanned aerial vehicle swarm communication method and system based on MIMO-OFDM, and relates to the technical field of wireless communication, and the method comprises the steps: receiving a down-conversion baseband; synchronization and compensation are carried out; removing a cyclic prefix and carrying out fast Fourier transform; estimating a channel and noise on the training and pilot frequency, and correcting a common phase; performing frequency domain equalization and soft decision, forward error correction and cyclic redundancy check according to the estimation to obtain a control parameter, decoding a payload according to the control parameter, and performing statistics to form a link quality indication; modulating coding, bandwidth and spatial mode, configuring mapping, power and weight, and packaging physical layer protocol data; carrier sensing conflict avoiding sending, confirmation and retry are adopted to generate media access statistics; and the routing selects the next-hop multi-hop forwarding according to the transmission quality, and performs end-to-end statistics and recharge. Through cooperation of hierarchical synchronization and phase correction with cyclic prefix and FFT, crosstalk is suppressed, channel noise scale optimization soft decision is robust, data decoupling is controlled, and end-to-end availability is improved through multi-hop self-healing recharge.

The embodiment of the invention provides a data processing method and device, electronic equipment and a storage medium, is suitable for a processor comprising a first integrated circuit unit and a second integrated circuit unit, and comprises the following steps: acquiring to-be-transmitted data and providing the to-be-transmitted data to the first integrated circuit unit; the verification information of the data to be transmitted is generated, the verification information comprises state information of a forward error correction code, data information of the forward error correction code and state information of cyclic redundancy check, and the data information of the forward error correction code and error data in the data to be transmitted have a corresponding relation; and sending the verification information and the to-be-transmitted data to the second integrated circuit unit, so that the second integrated circuit unit sends the to-be-transmitted data to the second integrated circuit unit under the condition that the state information of the forward error correction code is error-free or correctable error and the state information of the cyclic redundancy check is error-free. And a correct cyclic redundancy check code is calculated based on the received data to be transmitted and the data information of the forward error correction code, so that efficient data transmission is realized.

The invention provides a vehicle-mounted data grading processing method, system, device and medium, the method is cooperatively realized by a cloud end and a terminal device, and the method specifically comprises the following steps: the cloud end generates a structured configuration file containing an acquisition signal, a data type, a transmission condition, a priority and a compression rule based on a service scene, a first processor of the terminal equipment analyzes a received structured configuration file to generate an acquisition white list, a second controller filters controller messages according to the white list, executes double verification of cyclic redundancy check and counter tamper-proofing, and transmits valid data passing the verification in a hierarchical manner according to priorities, and a cloud terminal performs hierarchical decompression analysis on the received data and sends the analyzed data to a server. A historical data supplement mechanism is triggered when the data is abnormal, and the terminal equipment responds to the request to upload data in a specified time period and performs compensation analysis; according to the method, the collection flexibility is realized through dynamic configuration, and the problems of high computing power pressure of terminal equipment, non-uniform network transmission distribution and low cloud computing power utilization rate are solved.

The invention discloses a high-speed camera data self-adaptive two-stage caching system and method and a storage medium, and relates to the technical field of machine vision high-speed imaging and high-speed data storage, a preprocessing unit is used for performing deserialization and parallel connection, ROI cutting and gain adjustment on collected item number data, and writing incremental FrameID and cyclic redundancy check codes into each frame; the DDR annular cache unit comprises a monitoring module, a decision module and an execution module; the decision module is used for calculating an instantaneous cache demand Cnew and a dynamic cache occupancy U; the execution module expands and shrinks an annular buffer space in a single shot through a DDR4 controller, and outputs a Hi / Lo mark in real time through an occupancy rate comparator to drive an NVMe queue manager. According to the invention, on the premise of zero extra burden in a normal working condition, millisecond-level automatic capacity expansion and high-speed flood discharge can be realized in a sudden working condition, and real-time frame-level integrity verification can be completed on a local FPGA (Field Programmable Gate Array) side. The patent is subsidized by national key research and development plans, and the project number is 2023YFF0719700.

The invention provides an FPGA program loading and updating method and system, and relates to the technical field of FPGA configuration management. The FPGA program loading and updating method comprises the following steps: S1, based on an RS422 physical layer protocol, adopting a self-adaptive block verification algorithm, acquiring a signal-to-noise ratio parameter in real time through a channel quality monitoring module, dynamically adjusting the size of a data packet, and implementing a double-buffer alternate receiving mechanism; and verifying each data block by using cyclic redundancy check and serial number continuity detection, discarding abnormal data packets with bit error rates exceeding the limit, and generating a data block set passing verification. Through combination of an adaptive block check algorithm and channel quality dynamic monitoring, real-time optimization and adjustment of the size of a data packet in a transmission process are realized, transmission requirements in different channel environments are effectively adapted, the data retransmission probability is reduced, and through cooperative application of a double-buffer alternate receiving mechanism, cyclic redundancy check and a serial number tracking technology, the transmission efficiency is improved. And continuity and integrity of data receiving are ensured.

The invention relates to the technical field of embedded data storage, and discloses a method and a system for prolonging the service life of a FLASH simulation EEPROM (Electrically Erasable Programmable Read-Only Memory) in a single chip microcomputer, and the method comprises the following steps: firstly, initializing the FLASH, dividing the FLASH into a main data area, a mapping table area, a backup area and a transaction log area, selecting a physical block through a dynamic wear leveling algorithm when data is written, and writing the data into a database; the method comprises the following steps of: starting a backup area or a transaction log area, safely updating a mapping table by using a transaction mechanism, performing cyclic redundancy check when reading data, if the cyclic redundancy check fails, starting cascade recovery from the backup area or the transaction log area, and finally, updating a transaction log to record operation so as to form a closed-loop management process. According to the invention, through a set of dynamic wear leveling and data classification management mechanism, global and uniform distribution of the write load in the storage array is realized, the physical block with the least erasing times is selected during writing, the access frequency of the data can be identified, and cold data which is not changed frequently can be actively migrated.

The invention discloses a communication data transmission method and system for an intelligent charging pile, and relates to the technical field of intelligent charging pile communication, and the method comprises the steps: constructing a reverse power line transmission channel model based on an equivalent channel response matrix, extracting channel frequency response, generating a channel equalization configuration parameter set through a joint optimization equalization algorithm, and transmitting the channel equalization configuration parameter set to a communication module. Subcarrier modulation orders are dynamically allocated according to the signal-to-noise ratio parameter, and a pre-balanced OFDM time domain signal is generated; on the basis of the channel equalization configuration parameter set and the pre-equalization OFDM time domain signal, dynamically monitoring power frequency harmonic noise of the cable, and inhibiting interference through a filtering algorithm to generate a clean power line carrier signal; and generating a verified V2G communication control instruction through a cyclic redundancy check method based on the clean power line carrier signal in combination with the main polarization direction feature vector. According to the method, an accurate channel model is constructed by combining an equivalent channel response matrix and cable characteristics, and dynamic subcarrier distribution is realized based on signal-to-noise ratio parameters.

A cyclic redundancy check bit determination method and system, the method including obtaining an information bit, determining, based on a first correspondence, that a check bit length is L, where L is a natural number, and where the first correspondence includes a correspondence among code length information of to-be-transmitted data including the information bit, length information of the information bit, and the check bit length, and determining a first check bit based on a first cyclic redundancy check (CRC) polynomial, where a length of the first check bit is the check bit length L, where a highest power of terms in the first CRC polynomial is Lmax, where Lmax is a positive integer, and where Lmax is greater than or equal to L.

The invention provides a cyclic redundancy check method and device and a logic chip, and relates to the technical field of electronics. The cyclic redundancy check method comprises the following steps: acquiring to-be-processed data; splitting the to-be-processed data based on a preset bit width to generate N sub-data; performing CRC operation on the N sub-data according to a CRC matrix corresponding to a preset bit width to generate M first CRC values; and for the M first CRC values, selecting a corresponding CRC sub-matrix from the N CRC sub-matrixes according to the position of the sub-data corresponding to the current first CRC value in the data packet from the first first CRC value to the last first CRC value, performing CRC operation on the current first CRC value and the previous first CRC value to obtain M second CRC values, and performing XOR operation on the M second CRC values to determine a target CRC value. Through the method, the time sequence requirement of logic chip design can be met.

The present application provides a data check method, device and system, which are applied to the field of communications. The method comprises: obtaining operation environment information, check information and data to be checked; on the basis of the operation environment information and the check information, matching a target check mode, wherein the target check mode is one of a first check mode, a second check mode and a third check mode, the first check mode completes cyclic redundancy check (CRC) calculation on the basis of vectorization calculation, the second check mode completes the CRC calculation on the basis of a hardware CRC, and the third check mode completes the CRC calculation on the basis of a look-up table; and checking said data on the basis of the target check mode. The present application can support various CRC algorithms, and adaptively provide an optimal check mode on the basis of system information, thereby increasing the calculation speed, and optimizing data check.

Apparatuses and methods for transmission and reception between a reader and an Internet of Things (IoT) device. A method includes receiving a physical reader-to-device channel (PRDCH) from the reader. The PRDCH includes a medium access control (MAC) header and a payload. The MAC header indicates (i) a type of reader-to-device (R2D) message and (ii) information related to determining a size of the payload. The MAC header and the payload are jointly attached with a single set of cyclic redundancy check (CRC) bits. The method further includes determining, based on reception of the PRDCH, a transmission of a physical device-to-reader channel (PDRCH) to the reader including determining a type of device-to-reader (D2R) message, a size of a payload of the D2R message, a length of the PDRCH transmission, and a transmission timing of the PDRCH. The method further includes transmitting the PDRCH to the reader.

The invention relates to the technical field of data processing, in particular to an FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit) cooperative network data processing system, which comprises a network interface module for receiving and forwarding an external data flow, and a protocol analysis module for distinguishing a service message and a protocol message based on a message header characteristic and a load mode; the service processing module executes protocol format conversion, security encryption and data extraction in the FPGA; the protocol stack interaction module transmits a protocol message to the CPU through the MAC layer communication interface; the protocol stack module activates necessary protocol services in the CPU and generates a resource allocation instruction; and the data integration module receives the service data flow and the protocol processing result, and dynamically adjusts the encryption rule. According to the invention, FPGA business data closed-loop processing and CPU protocol service physical isolation are realized, a double-processing-unit architecture supports financial signature and industrial filtering cascade operation, the MAC layer interface is additionally provided with cyclic redundancy check to guarantee transmission reliability, and equipment processing efficiency and anti-attack capability under a fusion scene are improved.

The invention discloses a large file concurrent uploading method and system based on a dynamic fragmentation strategy and resource optimization, and the method comprises the steps: a client generates a file fingerprint according to the file size of a large file and metadata, and dynamically calculates the fragmentation size of the large file; the client carries out fragment cutting on the large file according to the calculated fragment size, establishes a concurrent uploading queue and uploads a plurality of fragments to a server side in parallel; the server selects an optimal storage node to store each fragment based on a consistent hash ring and a multi-dimensional weight model; the client side and the server side track a fragment uploading state through a fragment serial number and a cyclic redundancy check (CRC) value, and after all fragments are uploaded, integrity check and logic recombination are carried out; and when network interruption or uploading failure is detected, the client side and the server side execute an intelligent retry strategy or a splitting rescheduling strategy of breakpoint resume and failure fragmentation.

Wireless communication is performed by: receiving downlink control information including by a user equipment in an inactive state, a cyclic redundancy check scrambled by a radio network with at least one base-station with paging-Radio Network Temporary Identifier at least one user equipment, user equipment monitors paging message in inactive state and uses paging-Radio Network Temporary Identifier to decode reception of paging message, wherein the user equipment receives more than one random-access channel resources from the network and the indication of Small Data transmission and user equipment selects the random-access channel resources.

The embodiment of the invention relates to the technical field of data transmission security detection, and provides a data transmission detection method and device, electronic equipment and a medium, and the method comprises the steps: receiving target data which is transmitted by a transmitting end and carries a first check code, and obtaining the character length of the first check code; when the character length of the first check code does not meet the integral multiple of the parallelism degree of a cyclic redundancy check algorithm, a preset method is adopted to verify the first check code, and the preset method is a method for carrying out data frame tail zero padding and then backspacing on the first check code; and carrying out transmission anomaly detection on the target data based on a verification result of the first check code. Therefore, processing delay is greatly reduced, resource occupation and power consumption are reduced, and cost is reduced.

A method of wireless communication comprises receiving downlink control information by a user equipment in an inactive state. The downlink control information comprises a cyclic redundancy check scrambled by a radio network with at least one base-station with paging-Radio Network Temporary Identifier. The user equipment monitors paging message in inactive state and uses paging-Radio Network Temporary Identifier to decode reception of paging message, wherein the user equipment receives indication of small data transmission and identifier from radio network with at least one base-station.

The invention discloses a distributed storage management method, an electronic device, a storage medium and a program product, and relates to the technical field of distributed storage. Cyclic redundancy check codes corresponding to data are written into metadata, the amount of metadata written into a distributed key value storage database is reduced, the performance of the distributed key value storage database is improved, and the reliability of the distributed key value storage database is improved. According to the method, the network transmission protocol is expanded, the metadata separation transmission mode is supported, the data logic block pointer and the independent metadata logic block pointer are supported when the distributed storage protocol access layer processes the read-write request, data copying of distributed storage is reduced through the metadata separation transmission mode, and the read-write performance is improved.

The invention discloses a multipath effect suppression method for 2.4 GHz radio frequency identification. The multipath effect suppression method comprises a transmitting end processing flow and a receiving end processing flow. A transmitting end carries out pulse code modulation on an analog signal to obtain a digital signal, blocks the digital signal after channel coding, and distributes the digital signal to subcarriers through quadrature amplitude modulation; and generating a time domain OFDM symbol through IFFT (Inverse Fast Fourier Transform), adding a cyclic prefix and a synchronization head, converting into an analog baseband signal, and performing up-conversion, filtering, amplification and radiation. The receiving end amplifies the signal, down-converts the signal to a baseband, filters the signal and converts the signal into a digital signal; the method comprises the following steps of: synchronizing header frame alignment, recovering a coding bit stream through FFT (Fast Fourier Transform) and QAM (Quadrature Amplitude Modulation) demodulation, carrying out CRC (Cyclic Redundancy Check) after decoding and merging, returning ACK (Acknowledgement Character) if According to the method, the multipath effect can be effectively inhibited, and the integrity of received data is improved.

This disclosure describes systems, methods, and devices related to enhanced duplex communication. A device may receive an indication for PRACH resources for subband non-overlapping full duplex (SBFD) operationin downlink control information with a Cyclic Redundancy Check (CRC). The device may determine a physical random access channel (PRACH) occasion based on the indication for PRACH resources for SBFD operation. The device may transmit a PRACH preamble on the determined PRACH occasion.

The invention provides an EEPROM (Electrically Erasable Programmable Read-Only Memory) data read-write method and device based on a real-time industrial Ethernet and a medium. The method comprises the following steps: setting an initial offset and an access length of EEPROM access on a target slave station according to EEPROM capacity parameters, and establishing a paging transaction; when the paging transaction is of a reading type, sequentially triggering EEPROM control registers of the target slave station, reading EEPROM data to a buffer area of the master station according to pages from the initial offset, and executing cyclic redundancy check on each page of read data; when the paging transaction is of a write-in type, reading a to-be-written data file into a buffer area of the master station, writing the to-be-written data file into an EEPROM (Electrically Erasable Programmable Read-Only Memory) of a target slave station according to a page sequence from initial offset, and after writing of each page is completed, reading back data of the page and executing cyclic redundancy check; and when all page data of the paging transaction of the reading type or the writing type passes cyclic redundancy check, outputting a transaction completion state to the soft programmable logic controller. According to the method and the device, the technical effects of safely, efficiently and accurately reading and writing the EEPROM on line in batches and ensuring the data consistency can be achieved.

The embodiment of the invention provides a cyclic redundancy check method and device, electronic equipment and a medium. The method comprises the following steps: determining a target pre-calculation result according to a target parameter; the target parameter comprises a target generator polynomial and a target data bit width; the target pre-calculation result comprises a cyclic redundancy check (CRC) input coefficient matrix and an input data coefficient matrix; determining a parallel CRC calculation logic according to the target pre-calculation result; the parallel CRC calculation logic is used for calculating a CRC check result of each check cycle in each check cycle; and updating the to-be-verified system according to the parallel CRC calculation logic, and when the to-be-verified system receives the to-be-verified data, controlling the to-be-verified system to execute the parallel CRC calculation logic to verify the to-be-verified data to obtain a verification result. The method is used for achieving the effect of efficiently determining the parallel CRC calculation logic applied to the to-be-verified system.

The invention discloses a remote upgrading method, relates to the technical field of remote upgrading, and solves the problems that multiple times of upgrading cannot be successful, and starting cannot be performed or repeated restarting cannot be performed after upgrading due to external conditions such as external condition network signal fluctuation and power supply interruption when a vehicle is subjected to remote upgrading. The remote upgrading method comprises the following steps: reading key parameters in a storage area, judging a version number, and selecting a server response; dividing the upgrade package into a plurality of to-be-deployed packages according to a preset subpackage mechanism, distributing an independent check code and a storage area for each to-be-deployed package, and continuously performing real-time check and rolling check; when the remote upgrading process is abnormal, the vehicle starts a triple storage protection mechanism and an intelligent reconnection strategy, and then transmission and verification of a to-be-deployed packet are completed to generate an upgrading flag bit; when the vehicle is started again, the to-be-deployed package is moved from different storage areas according to the upgrading mark, verification judgment of the overall cyclic redundancy check code is completed, and then remote upgrading of the vehicle is completed.

A method according to one embodiment of the present specification comprises the steps of: generating a signal on the basis of a cyclic redundancy check (CRC); and transmitting the signal. The plurality of chips related to the signal include i) chips related to the CRC and ii) one or more chips related to padding.

Wireless communication is performed by: receiving downlink control information including by a user equipment in an inactive state, a cyclic redundancy check scrambled by a radio network with at least one base-station with identifier that is specific to a group of UEs, the group of UEs including the UE, and a resource assignment for a data transmission from at least a base-station to the user equipment; and receiving, by the user equipment in the inactive state, the data transmission on a physical shared channel, wherein the user equipment receives indication from radio network with at least one base-station, whether the radio network with at least one base-station has one shot downlink data transmission or multiple shot data transmission.

The disclosure discloses a method for supporting segmented cyclic redundancy check, comprising: in response to correctness of a first cyclic redundancy check performed on an encoding block by using a generator polynomial corresponding to the encoding block belonging to a transport block, performing a second cyclic redundancy check operation on the encoding block by using a generator polynomial corresponding to the transport block, obtaining a first result; performing third cyclic redundancy check operation on parameters respectively related to the position of the coding block in the transmission block and the length of the coding block by using a generator polynomial corresponding to the transmission block to obtain a second result; performing a first operation on the first result and the second result, and performing a fourth cyclic redundancy check operation on the result of the first operation by using a generator polynomial corresponding to the transmission block to obtain a partial result of the coding block in the cyclic redundancy check code of the whole transmission block; and performing second operation on each part result to obtain a cyclic redundancy check code of the whole transmission block.

A memory device includes CRC (cyclic redundance check) circuitry to detect CRC errors in write transactions. The CRC circuitry computes CRC for a data block to compare with CRC bits that were computed and sent by the memory controller. The memory device records the pass / fail status of write transactions in an error status register readable by the memory controller. The memory device can trigger the ALERT_n signal in response to an error.

An apparatus may receive T copies of data that includes a cyclic redundancy check (CRC). T is an even number greater than or equal to 4. The apparatus may determine a first set of bit positions, at each of which T / 2 copies of the data have a same first bit value different from a same second bit value of the other T / 2 copies of the data, determine a second set of bit positions, at each of which more than T / 2 copies of the data have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the first set of bit positions and the second set of bit positions, an error contained in the first copy.

An apparatus may receive a first copy, a second copy and a third copy of data including a cyclic redundancy check (CRC) code, determine that a number of one or more bit positions, at each of which at least two of the first copy, the second copy or the third copy have bit values different from each other, is greater than a threshold value, divide the one or more bit positions into a first set of bit positions corresponding to the threshold value and remaining bit positions, determine, among the remaining bit positions, a second set of bit positions at each of which both the second copy and the third copy have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the second set of bit positions, an error in the first copy.

Embodiments of the present application provide a wireless communication method and a wireless communication device. The wireless communication method is executed by a reader / writer and comprises: sending information; and on the basis of a predefined rule, determining whether to add a cyclic redundancy check (CRC) code to the information. The information is first information, the first information comprises paging-like information and / or device selection information, and the paging-like information is used for selecting a device to be inventoried or classifying the device.