1342 results about "Data error" patented technology

Systems and methods for time series data error detection, correction, and transformation may detect gaps and anomalies in time series data, such as from a meter device, and may correct the gaps and adjust the anomalies prior to long-term record storage. Data forecasting may be used to correct the errors in the time series data. The error corrected data may be regarded as an actual set of time series data and become a base data set against which additional heuristic projections are generated. In addition, the time series data may be transformed into any number of physical and virtual device hierarchies that represent the underlying data source configurations, and may then be stored in an analytical database for further analysis. The hierarchies may be irregular and may change over time.

Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2^M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.

Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.

A method and apparatus of dynamically storing critical data of a gaming machine by allocating and deallocating memory space in a gaming machine is disclosed. One or more embodiments describe downloading or removing a new game to a gaming machine such that all existing critical data in NV-RAM memory is left intact. In one embodiment, the invention discloses a method and apparatus for dynamically allocating and deallocating memory space to accommodate either permanent or temporary storage in an NV-RAM. A method and apparatus is provided to monitor available memory space and dynamically resize the memory in NV-RAM. In one embodiment, a method is disclosed for performing an integrity check of the NV-RAM and determining whether a critical data error has occurred. In one or more embodiments, methods of compacting and shifting contents of an NV-RAM are described to consolidate available memory space or to prevent unauthorized access of NV-RAM memory.

In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage is adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

A computer system includes a dual basic input-output system (BIOS) read-only memory (ROM) system to initialize the computer. When the computer is first powered on or reset, the primary BIOS ROM is initially enabled. The computer analyzes the contents of the primary BIOS memory to detect data errors. If a data error is detected, a chip enable circuit disables the primary BIOS ROM and enables a secondary BIOS ROM containing essentially the same initialization instructions as the primary BIOS ROM. If no errors are detected in the secondary BIOS ROM, the initialization of the computer proceeds using the secondary BIOS ROM. As part of the initialization procedure, the contents of the secondary BIOS ROM are copied to a random access memory. The primary BIOS ROM can then be reprogrammed with the contents of the secondary BIOS ROM using the copy in random access memory, or from the secondary BIOS ROM itself.

A storage subsystem monitors one or more conditions related to the probability of a data error occurring. Based on the monitored condition or conditions, the storage subsystem adjusts an error correction setting, and thus the quantity of ECC data used to protect data received from a host system. To enable blocks of data to be properly checked when read from memory, the storage subsystem stores ECC metadata indicating the particular error correction setting used to store particular blocks of data. The storage subsystem may be in the form of a solid-state non-volatile memory card or drive that attaches to the host system.

A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubbing controller then detects any errors in the read error correcting codes, and generates corrected error correcting codes that are written to the DRAM. This scrubbing procedure, by reading error correcting codes from the DRAM, inherently refreshes memory cells in the DRAM. The error correcting codes are read at rate that may allow data errors to be generated, but these errors are corrected in the memory scrubbing procedure. However, the low rate at which the error correcting codes are read results in a substantial power saving compared to refreshing the memory cells at a higher rate needed to ensure that no data errors are generated.

Methods of operating nonvolatile memory devices include testing a plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings. An identity of the at least one weak string may be stored as weak column information. This weak column information may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on a first plurality of bits of data read from the plurality of strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits.

A new system and method for communicating between a host device and one or more slave devices are presented. The system provides data error checking and correcting, data encryption, and robust slave address sequencing using a portion of a session key. The data encryption uses a second portion of the session key, which changes for each power cycle.

In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.

A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or cleansing operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the cleansing logic initiates a cleansing routine in response to an event such as an operator instruction or a periodic schedule. By implementing the cleansing operation, the system does not rely on external READ commands to verify data integrity. Further, a monitoring device is coupled between the cleansing logic and a memory scheduler. The monitoring device provides a feed back mechanism from which to vary the frequency of certain memory requests such as the cleansing and scrubbing operations. The cleansing routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the cleansing routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.

In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

Flash memory devices and associated methods are described for controlling data errors in the devices through various forms of decoding, error correction, and wear concentration. To this end, a flash memory device may be partitioned into a plurality of sectors. Data may then be received from, for example, a host processor for storage within the flash memory device. Storage durations of the data are then estimated and the data is stored in the data sectors based on those estimated storage durations.

This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

As part of electronically handling a large amount of data (e.g., error messages) generated within, for example, a telephone service provider's billing network, a configuration utility software allows a user to electronically change or update various configuration parameters for another software application, e.g., a loader application, and also to access the performance data generated by the loader application so as to optimize the performance of the loader application in varying data transfer situations. The loader application, in turn, is a computer-based data transfer application that electronically loads a large volume of data, e.g., telecommunication billing data, from one computer into another computer. The loader application thus substantially reduces human involvement during transfers of large amount of data, and thereby also reduces errors typically associated with manual data entries by human data operators. After completion of data transfers, an error handler program facilitates electronic investigation and disposal of errors in the received data, thereby minimizing participation of human operators in the data error rectification process. The reduced reliance on manual identification and correction of data errors thus results in increased accuracy and efficiency in the overall network data management and customer billing operations.

A data scrubbing apparatus corrects disturb data errors occurring in an array of memory cells such as SMT MRAM cells. The data scrubbing apparatus receives an error indication that an error has occurred during a read operation of a grouping of memory cells within the array of memory cells. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data. Based on a scrub threshold value, the data scrubbing apparatus writes the corrected data back after a specific number of errors. The data scrubbing apparatus may further suspend writing back during a writing of data. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

A feedback link is provided in a directional communication system, such as a millimeter wave communication link, to allow a directional transmitter to optimize an antenna alignment and gain. A remote receiver in the directional link can receive a transmission over the directional link and determine a signal metric, such as received signal strength or data error rate, based on the received signal. The receiver can then couple the signal metric to a feedback transmitter that communicates the signal metric back to the originating directional transmitter using a feedback communication link that is distinct from the directional link. The feedback communication link can be a wireless communication link, such as an IEEE 802.11 wireless communication link. The directional transmitter can receive the signal metric using a receiver coupled to the feedback link. The directional transmitter can adjust a gain or alignment of the antenna based on the signal metric.

This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A likelihood calculation circuit calculates a likelihood value of data stored in a memory cell based on the soft-value. An error correction circuit executes data error correction for the data read from the memory cell based on the likelihood value. A refresh control circuit controls a timing of a refresh operation for the memory cell based on the soft-value or the likelihood value.

A remote asset control system for optimized asset performance under a variety of circumstances, such as network communication path failures, software maintenance, software faults, hardware faults, hardware maintenance, computer system maintenance, computer system failure, undetected data errors, configuration errors, human error, power outages, malicious network attacks, and the like, having a means to create, modify, and delete asset policies, an object oriented asset policy inheritance scheme that generates composite asset policies, an asset policy transference and caching scheme, condition driven asset policy enforcement, permission-based asset policy mechanism for throttling energy or water consumption, asset replacement simplification, query capability to enumerate actual asset deviance as compared to the currently enforced composite asset policy, real-time control asset policies, atomic activation and deactivation of asset policies, which are part of the policy inheritance hierarchy, ensuring composite policy integrity, and multi-tiered telemetry caching and transference.

A high speed, high sensitivity post amplifier as described herein includes a digitally-controlled DC offset cancellation feature. The amplifier circuit is configured to provide DC offset voltage levels in response to a digital control signal, where the digital control signal is generated based upon a data error metric such as bit error rate. The AC signal path and the DC offset adjustment signal path in the amplifier circuit are separated to facilitate operation with normal power supply voltages, and to achieve low power operation.

The invention provides a high-performance reliable solid-state disk realizing method. The method includes: (1), dividing all flash memory chips in a solid-state disk into groups and forming an RAID (redundant array of independent disks) 4-level flash array in each group by N successive flash chips; (2), receiving and storing data through a cache; (3), judging whether the cache is filled up or not, if yes, entering the step (4), and if not, returning to the step (2); (4), extracting N-1 data blocks from the cache and computing check values of the N-1 data blocks; making up the N-1 data blocks and the check values into filled stripe data and writing back the flash array; returning to the step (2). The flash chips in the solid-state disk are used for establishing the RAID4-level physical array to assure data reliability. Faults at different levels including page level, block level, or even chip level can be processed. Besides, writing-in performance is improved by writing of filled stripes and sequence, and spatial and performance loss resulted from data errors can be reduced to the utmost.

The invention discloses a behavior identification method based on a 3D convolution neural network, and relates to the fields of machine learning, feature matching, mode identification and video image processing. The behavior identification method is divided into two phases including the off-line training phase and the on-line identification phase. In the off-line training phase, sample videos of various behaviors are input, different outputs are obtained through calculation, each output corresponds to one type of behaviors, parameters in the calculation process are modified according to the error between an output vector and a label vector so that all output data errors can be reduced, and labels are added to the outputs according to behavior names of the sample videos corresponding to the outputs after the errors meet requirements. In the on-line identification phase, videos needing behavior identification are input, calculation is conducted on the videos through the same method as the training phase to obtain outputs, the outputs and a sample vector for adding the labels are matched, and the name of the sample label most matched with the sample vector is viewed as a behavior name of the corresponding input video. The behavior identification method has the advantages of being low in complexity, small in calculation amount, high in real-time performance and high in accuracy.

A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or verify operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the verify logic initiates verify routine in response to an event such as an operator instruction, hot-plug operation, or a periodic schedule. By implementing the verify operation, the system does not rely on external READ commands to verify data integrity. The verify routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the verify routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.

A method and an apparatus for error resilient, digital image scrambling are disclosed. Error resilience scrambling is produced by shuffling transform coefficients between arrays of coefficients arranged along an axis substantially orthogonal to the axis along which packetization of the coefficients proceeds. Scrambling transform coefficients requires a reasonable level of processing resources and has minimal impact on the efficiency of the compression process. Shuffling can be performed in a number of ways to provide good access security and a variety of security. Scrambling the image data in a direction substantially orthogonal to the direction of packetization of the transform coefficients distributes any transmission error in the image reducing the effects of data error or loss on the displayed image.

A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.

The invention discloses a road environment element sensing method based on a laser radar, and the method comprises the steps: 1, downsampling original point cloud data of the laser radar, obtaining aregion of interest, obtaining simplified point cloud data, segmenting ground data, and obtaining a result; 2, adopting a voxelization-based DBSCAN clustering algorithm to realize barrier segmentationof non-ground data, and carrying out obstacle classification and recognition based on multiple features; and 3, designing a road boundary extraction method suitable for vehicle-mounted laser radar data by utilizing data point elevation mutation, screening boundary points by using prior knowledge after extracting the road boundary points, fitting a road boundary line by adopting a least square method, and marking a barrier-free area by using the grids to realize detection of a passable area in a laser radar road scene. The method is simple in algorithm, small in data error, safe and reliable.

Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC, where the sample selected depends on the count of erase-program cycles that a block has experienced, where different count ranges can use different samples.

A method for detecting transfer errors in an address bus is provided. In this method, a first address parity is generated using a memory address. Next, at least two data error-correction-code (ECC) check bits are scrambled using the first address parity. Subsequently, the data ECC check bits are written to a memory and the data ECC check bits enable detection of transfer errors in the address bus. A system for detecting transfer errors in an address bus is also described.