129 results about "Bit-length" patented technology

Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reducer can receive a particular input and generate multiple reduced inputs from the input. The reduced inputs can include reduced input data elements and / or a reduced weights. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide multiple reduced inputs with second shorter bit-length to the array. The systolic array may perform multiply-accumulate operations on each unique combination of the multiple reduced input data elements and the reduced weights to generate multiple partial outputs. The systolic array may sum the partial outputs to generate the output.

The invention relates to the technical field of data processing, and discloses a logistics data transmission verification method and system based on hierarchical priority. The method comprises the steps of collecting logistics data, establishing a grading system according to business importance, and generating a weight matrix and a sensitivity matrix; calculating a data change difference value, and performing weighted operation with the matrix to output a deviation vector; extracting position, state and time information in the vector, and calculating correlation degree and consistency to generate a multi-dimensional check value; allocating coding bit length according to the check value, and performing dynamic Huffman coding to generate a data packet; and verifying the data packet, performing incremental decoding to recover information, and reconstructing a database state. The logistics data transmission verification method and device solve the problems that an existing logistics data transmission verification method is low in verification efficiency, cannot adapt to business differentiation requirements and is too large in verification overhead in a bandwidth limited environment, and the efficiency and pertinence of logistics data transmission verification are improved.

The invention discloses a coding and decoding method for LDPC codes under time and frequency selective channels in an NAVDAT system, and the method comprises the steps: determining a basis matrix and an expansion factor Z according to an information bit length and a target code length of an input bit sequence before coding, and the Z is a positive integer; obtaining a low density parity check (LDPC) matrix based on the basis matrix and the expansion factor Z; the method comprises the following steps: encoding an input bit sequence by using a low density parity check (LDPC) matrix under an NAVDAT system time and frequency selective channel, wherein the code rate is 3 / 4 or 1 / 2; wherein a basis matrix of the LDPC matrix comprises a sub-matrix A and a sub-matrix B, if the basis matrix is expressed as an m-row n-column matrix, the sub-matrix A is an m-row n-m-column matrix, the sub-matrix B is an m-row m-column matrix, and the sub-matrix B comprises a double-diagonal structure matrix B1, a single-diagonal structure matrix B2 and a column B3 with the weight of 4; and outputting the coded or decoded bit sequence. According to the invention, the coding requirements of information bit sequences with various lengths can be met.

The application discloses a short public parameter identity-based proxy re-encryption method based on an LWE problem, a trapdoor matrix, namely a short base on a lattice, is generated through a more simple and efficient trapdoor generation algorithm, the trapdoor matrix is taken as a master secret key MSK, an identity sequence with an l-bit length is divided into l' = l / β blocks through a block technology, the number of public parameter selection is reduced, the size of the master secret key and the public parameter is reduced, the public parameter calculation complexity is reduced, the calculation efficiency is improved, and the storage cost is reduced. The application satisfies adaptive IND-ID-CPA security under a standard model, has unidirectionality and limited multi-hop nature, and can resist collusion attacks.

A method for updating arbitrary length cryptographic keys having a bit length greater than 256 bits by a cryptographic key update system includes transmitting, by a sender, a first transmission to one or more controllers that are part of a vehicle and transmitting, by the sender, a second transmission to the one or more controllers, where the second transmission is a symmetric key encryption under a key encryption key of a concatenation of a plurality of parameters and a new cryptographic key. The sender derives the key encryption key by transforming an authentication key and a bit string of constant values based on an N-bit compression function. The method includes transmitting, by the sender, a third transmission to the one or more controllers that is an N-bit message authentication code under a first message authentication code (MAC) key of a concatenation of the first transmission and the second transmission.

The application discloses an intelligent decoding method for UART serial signals, which comprises the following steps: firstly, automatically recognizing unknown baud rate, data bit number, stop bit length and whether the UART protocol signal contains a parity check bit and other key parameters by using a large amount of data; and secondly, decoding and processing subsequent UART protocol signals according to cascaded decoding modules. Through the intelligent decoding of the UART protocol signal, the correct data information and baud rate can be accurately parsed without manually configuring or trying various decoding settings, so that the decoding process of the UART protocol signal can be greatly simplified, and the operation burden of the user can be reduced.

This invention discloses a multidimensional coupled chain code encoding method based on generalized integrated interleaving codes. It selects d-dimensional chain codes from s-dimensional chain codes for generalized integrated interleaving encoding, resulting in the l-th... i The code length of the wiry chain code is [value], and the information bit length is [value]. The remaining (s-d) wiry chain code is encoded, and the l′ [value] is [value]. i' Wirachain codes use linear block codes with a code length of and an information bit length of as the basic code, and the sequence c... (t) Initialize to an all-zero sequence; set the information sequence u Divide into sL groups. For the l-th dimensional zip code, divide into groups of length k. t,l -m t,l sequence u (t,l) With a length of m t,l sequence w (t,l) The data is fed into a multiplexer to obtain a length of k. t,l sequence a (t,l) The sequence is fed into a basic code encoder for encoding to obtain a codeword sequence. Simultaneously, the sequence is fed into a generalized integrated interleaved code encoder for encoding to obtain another codeword sequence. c (t,0) , c (t,1) ,…, c (t,s‑1) The encoded output sequence c at time t is obtained by feeding it into the multiplexer. (t) This invention has the advantages of simple coding, ease of implementation, and good performance.

Methods and devices are provided for rectifying a forward mapping coding bit length issue introduced by LMCS. In one method, a plurality of prediction samples, in a mapped domain, of luma component of a CU that is coded by a CIIP mode under LMCS framework is obtained, a plurality of residual samples, in the mapped domain, of the luma component of the CU is obtained, the plurality of prediction samples in the mapped domain is added to the plurality of residual samples in the mapped domain, resulting in a plurality of reconstructed samples, in the mapped domain, of the luma component, and the plurality of reconstructed samples of the luma component is converted from the mapped domain into an original domain based on a pre-defined plurality of inverse mapping scaling factors.

The invention provides a distributed processing method for a model weight, and belongs to the technical field of artificial intelligence, and the method comprises the steps: S1, carrying out the feature extraction of a model weight file, obtaining the feature information of a model weight tensor, and enabling the feature information to be the data information of a preset bit length of the model weight tensor; and S2, performing hash fragmentation processing on the feature information, determining a storage node corresponding to each fragment, and storing each fragment to the storage node corresponding to each fragment. The method has the beneficial effects that the model weights are fragmented and stored in a plurality of nodes, so that the capacity demand of single storage equipment is reduced, the hardware cost and the management difficulty are reduced, and the storage reliability and expandability are improved; the distributed storage model weight is adopted, weight data can be obtained from a plurality of storage nodes in parallel, the loading time is greatly shortened, the model loading efficiency is improved, and the method is suitable for application scenes with high real-time requirements.

The invention discloses an execution uncertainty-oriented air edge computing resource allocation method, device and equipment and a storage medium, and relates to the technical field of air edge computing, and the method comprises the steps: obtaining user number information, edge server task information, bit length information, time delay constraint information and energy constraint information; determining a target system resource allocation probability based on the user number information, the edge server task information, the bit length information, the time delay constraint information and the energy constraint information; and controlling a system to carry out resource allocation based on the target system resource allocation probability, and completing execution uncertainty-oriented air edge computing resource allocation. According to the method and the device, the uncertainty factors in the dynamic environment are quantified into probability constraints, calculation is performed through the optimal resource allocation strategies corresponding to different scenes, and the resource allocation probability of the target system is obtained, so that the system performs resource allocation in a self-adaptive manner, and the utilization efficiency of the system resources is maximized.

A method of determining a bit length of an IQ sample associated with a first data frame is provided. The method includes determining a first parameter associated with a payload length of the first data frame, and determining a second parameter indicative of a number of physical resource blocks in the first data frame. A presence of a compression header is detected based on the first parameter and the second parameter, and the bit length of the IQ sample is determined from one of the detected compression header and the first parameter and the second parameter. The bit length of the IQ sample may be determined automatically from information available in the data frame. This eliminates the need for manual entry of parameters into the packet analyzer and eliminates the likelihood of errors to due incorrect entry.

A processor obtains pieces of coded data, which are included in a bitstream and generated by coding tiles, and tile boundary independence information, which indicates whether each boundary between the tiles is a first or second boundary. Image data of a first tile is generated by decoding a first code string included in first coded data with reference to decoding information of a decoded tile when the tile boundary independence information indicates the first boundary, and by decoding the first code string without referring to the decoding information when the tile boundary independence information indicates the second boundary. A bit string is added after the first code string to make a bit length of first coded data a multiple of a predetermined N bits, with N being an integer greater than or equal to 2.

This invention discloses a hardware optimization method for shared NTT in a hybrid application scenario of quantum-resistant cryptography ML-KEM and ML-DSA. For the three core basic operators in the NTT module—modular addition, modular subtraction, and modular multiplication—this invention redesigns the corresponding hardware implementation structure. Based on the design of ML-KEM with a smaller modulus bit length, it supports large-bit-width NTT operations by time-division multiplexing small-width arithmetic units, effectively reducing the hardware overhead of the underlying operators. For ML-DSA NTT operations, this invention proposes a dedicated pipeline structure that matches the improved operators. This structure optimizes register overhead through reasonable design of data flow paths and multiplexing mechanisms, further reducing system resource costs. This invention achieves compatibility support for multiple NTT parameters, thereby enabling the simultaneous completion of NTT operation tasks under different algorithms or parameter sets on the same hardware platform.

The invention discloses a coding and decoding method for LDPC codes under a slight fading Gaussian channel in an NAVDAT system, and the method comprises the steps: determining a basis matrix and an expansion factor Z according to an information bit length and a target code length of an input bit sequence before coding, and the Z is a positive integer; obtaining a low density parity check (LDPC) matrix based on the basis matrix and the expansion factor Z; the method comprises the following steps: encoding an input bit sequence by using a low density parity check (LDPC) matrix under a slight fading Gaussian channel of an NAVDAT system, wherein the code rate is 3 / 4 or 1 / 2; wherein a basis matrix of the LDPC matrix comprises a sub-matrix A and a sub-matrix B, if the basis matrix is expressed as an m-row n-column matrix, the sub-matrix A is an m-row n-m-column matrix, the sub-matrix B is an m-row m-column matrix, and the sub-matrix B comprises a double-diagonal structure matrix B1, a single-diagonal structure matrix B2 and a column B3 with the weight of 4; and outputting the coded or decoded bit sequence. According to the invention, the coding requirements of information bit sequences with various lengths can be met.

The application discloses a code length adaptive parity check polar encoding construction method, which is based on a polarization channel, has a low front channel reliability, a high rear reliability and a serial decoding characteristic of a classical polarization decoding scheme SCL, and designs a polar encoding method based on channel reliability and inserting a specified parity check code number of the code length adaptively. The method comprises the following steps: firstly, a channel polarization weight value is obtained based on a Gaussian channel to measure the channel reliability, the polarization weight value is inverted and added to the maximum polarization weight value in the channel for conversion, and then the first insertion of PC code is performed at the position of half PC code number. Finally, the second insertion of PC code is performed based on the remaining PC code number, the information bit length of PC code check and the converted polarization weight value, so that the parity check code with the code length adaptivity and the front dense and rear sparse characteristics is constructed. When SCL decoding is performed at the decoding end, the effective distribution of the parity check code in the information bit is utilized to effectively improve the saving probability of the decoding correct branch and improve the decoding performance.

The invention discloses a cell bandwidth part (BWP) setting method and device. The cell BWP setting method comprises the following steps: receiving downlink control information (DCI) of a first cell; the DCI may include a first field for indicating a first BWP of a third cell, and a second field for indicating a second BWP of a second cell. The first BWP is different from the activated BWP of the third cell. And setting the BWP of the second cell as a second BWP according to the first bit length and / or the second bit length. Wherein the first bit length of the second field is different from the second bit length of the second field of the first BWP. According to the invention, under the condition that the DCI indicates that the BWP of the third cell is switched to the first BWP, the second BWP can be accurately set for the second cell according to different bit lengths of the second field under different BWPs, and the communication efficiency is improved.

The invention provides a channel coding method suitable for different modulation modes. The method comprises the following steps: S1, acquiring a channel grouping set, a variable node number, a check node number, a degree range, an information bit length and a code rate; s2, constructing a bit mapping matrix and an edge distribution matrix; wherein one element in the bit mapping matrix represents the proportion of the quantity of variable nodes which are distributed to a channel corresponding to a specified row and have a corresponding degree of a specified column in all variable nodes; one element in the edge distribution matrix represents the proportion of the number of edges between all check nodes with a specified column corresponding degree and all variable nodes allocated to a specified row corresponding channel in all edges; s3, traversing solution spaces of the bit mapping matrix and the edge distribution matrix to obtain a plurality of matrix combinations, and calculating a decoding threshold of each matrix combination by adopting a preset calculation strategy; and S4, adopting a preset construction strategy to construct the LDPC code of the matrix combination with the minimum decoding threshold.

Methods, systems, and devices for wireless communications are described. A transmitting device may generate cyclic redundancy check (CRC) bits associated with a set of information bits using a CRC generation function configured to generate a plurality of CRC bit lengths, wherein one or more baseline polynomials associated with generating one or more first CRC bit lengths of the plurality of CRC bit lengths are nested within a plurality of polynomials associated with generating one or more second CRC bit lengths of the plurality of CRC bit lengths. The transmitting device may transmit the set of information bits and the CRC bits in accordance with the generating.

Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and / or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.

One embodiment provides a computing device for performing machine learning operations, the computing device comprising: a fetch unit to fetch a single instruction having a plurality of input operands having unequal bit lengths, a first input having a first bit length, and a second input having a second bit length; a decode unit to decode the single instruction into a decoded instruction; an operand length unit to determine a smaller bit length of the first bit length and the second bit length; and a calculation unit to perform a matrix operation on the plurality of input operands to generate an output value having a bit length of a smaller bit length.

A method of identifying at least one field in bits of a bit stream is disclosed. The method includes obtaining multiple first bit streams of a same type and obtaining a number of bit flips for bits in each bit position of multiple first bit streams. The method further includes identifying adjacent bits of a first bit stream that do not yet belong to an identified field as belonging to a NUMERIC field if the corresponding number of bit flips are in a descending order from a least significant bit position to a most significant bit position of the adjacent bits and the adjacent bits are of at least a predetermined bit length. A device including a processor configured to perform the method is also disclosed.

The application discloses a kind of medium wave communication navigation integrated signal design method, comprising: generating frame synchronization code and navigation text;The binary code of navigation text is segmented according to fixed bit length, and segmented binary code is obtained;According to order, segmented binary code is two two as a group, and each group of segmented binary code is first converted into series / parallel, then BHC error correction coding is carried out respectively;For each group of BCH code, parallel / series conversion is carried out according to each bit order to output interleaved code, so as to complete the interleaving coding of navigation text;Interleaved coded navigation text and frame synchronization code are modulated using full hopping MPPSK modulation, framing is carried out, multiple frame signals are formed, the multiple frame signals are used to replace the sine carrier in broadcast signal, and composite modulation signal is generated by composite modulation with analog audio signal and transmitted through broadcast station.The application can realize the dual functions of broadcast and navigation without affecting the normal use of users.

This arithmetic device causes a computer to execute: a processing step for, when the bit length of a key that is generated from a common key allocated for use in communication between a terminal device and a network and that is used for encryption and integrity assurance is longer than the bit length of an input key used in a predetermined algorithm, performing arithmetic processes different from each other on the bit string of the key generated from the common key and used for encryption and integrity assurance on the basis of a predetermined condition to obtain a bit string different from the bit string of the key generated from the common key and used for encryption and integrity assurance; and a hashing step for inputting the bit string obtained in the processing step to a predetermined hash function agreed in advance between the terminal device and the network to obtain a bit string having the same bit length as the bit length of the input key.

The present application discloses an information processing method and apparatus, a terminal device, and a storage medium. The method includes: based on a first bit length and / or a second bit length, determining a first rate matching output sequence length corresponding to first information. The first bit length is determined according in the number of bits of the first information and a code rate corresponding to the first information, and the second bit length is determined according to the number of bits of second information and a code rate corresponding to the second information, and the first information and the second information are transmitted on the same physical channel.

A communication system SYS includes a transmission apparatus 1 and a reception apparatus 2. The transmission apparatus includes: a conversion unit 111 for converting a bit stream Z having a bit length b into a bit stream Y that has w−1 (w is an integer equal to or larger than 2) bit 1 and that has a bit length n (n>b); a conversion unit 112 for converting the bit stream Y into a bit stream X having a bit length t (t<n); and a Neural Network 113 that has a t input node and that outputs a value relating to a feature of a transmission signal Tx when the bit stream X is inputted thereto. The reception apparatus includes: a Neural Network 212 that has a t output node and that outputs a numerical data stream U including t numerical data when a feature of the reception signal is inputted thereto; a conversion unit 213 for converting the numerical data stream U into a numerical data stream Y′ including n numerical data; and a generation unit 214 for generating a bit stream Z′ having the bit length b by performing, on the numerical data stream U, an inverse conversion of a conversion processing performed by the conversion unit 111.

A method for updating an arbitrary length cryptographic key having a bit length greater than 256 bits by a cryptographic key update system includes transmitting, by a transmitter, a first transmission to one or more controllers that are part of a vehicle, and transmitting, by the transmitter, a second transmission to the one or more controllers, wherein the second transmission is symmetric key encryption under a concatenated key encryption key of the plurality of parameters and the new cryptographic key. The transmitter derives a key encryption key by converting a bit string of an authentication key and a constant value based on an N-bit compression function. The method includes transmitting, by the transmitter, a third transmission to the one or more controllers, the third transmission being an N-bit message authentication code concatenated under the first message authentication code (MAC) key of the first transmission and the second transmission.

An apparatus according to various embodiments may receive resource configuration information for a physical uplink control channel (PUCCH) resource, divide the PUCCH resource into a plurality of unit resources on the basis of application of a sequence-based PUCCH format, segment an input bit sequence including input bits into a plurality of segments on the basis of a first bit length, select a first sequence for each of the plurality of segments, and transmit a PUCCH on the basis of the plurality of unit resources to which the plurality of first sequences selected for the plurality of segments are mapped.

The invention discloses an SGPIO (Serial General Purpose Input / Output) unified coding method, system and device, and the method is characterized in that the method comprises the steps: powering on a server host, and completing the initialization of a CPLD (Complex Programmable Logic Device) and an SATA / SAS controller; a register and a counter are established, and an SGPIO input Data buffer register, an output Data buffer register and a Clock counter of the SGPIO are established in the CPLD; data frame bit length calculation: the CPLD waits for receiving the SGPIO signal, and calculates the bit length of the input data frame after receiving the input SGPIO signal; whether the bit length of a data frame is equal to 12 bits or not is judged, if the length of the data frame is 12 bits, Clock, Load and Data signals of input SGPIO are directly transmitted to an output IO pin in a transparent mode, and the SGPIO signals of an output interface are completely equal to the SGPIO signals input by the CPLD; and if the data frame length is greater than 12 bits, the signal is processed, so that the SGPIO data of the output port is unified into 12-bit data. By unifying the SGPIO data of the output port into 12 bits, the problem that the bit lengths of SGPIO signals of different devices or interfaces are inconsistent is effectively solved, and the compatibility and standardization degree of the system are remarkably improved.

To efficiently generate a floating-point pseudo-random number.SOLUTION: A first generation unit generates a first bit string that is random and has a bit length of a floating-point number. A second generation unit generates a second bit string that has the bit length of the first bit string, by using a predetermined sign bit, a predetermined bit string of an exponent part, and a bit string of a mantissa part included in the first bit string.SELECTED DRAWING: Figure 1

A pseudo random number generator includes a first generator configured to generate a random first bit sequence having a bit length with floating-point representation, and a second generator configured to generate a second bit sequence having the bit length, using a predetermined sign bit, a bit sequence of a predetermined exponent part, and a bit sequence of a mantissa part included in the first bit sequence.