67 results about "Bit-length" patented technology

The application discloses a short public parameter identity-based proxy re-encryption method based on an LWE problem, a trapdoor matrix, namely a short base on a lattice, is generated through a more simple and efficient trapdoor generation algorithm, the trapdoor matrix is taken as a master secret key MSK, an identity sequence with an l-bit length is divided into l' = l / β blocks through a block technology, the number of public parameter selection is reduced, the size of the master secret key and the public parameter is reduced, the public parameter calculation complexity is reduced, the calculation efficiency is improved, and the storage cost is reduced. The application satisfies adaptive IND-ID-CPA security under a standard model, has unidirectionality and limited multi-hop nature, and can resist collusion attacks.

This invention discloses a multidimensional coupled chain code encoding method based on generalized integrated interleaving codes. It selects d-dimensional chain codes from s-dimensional chain codes for generalized integrated interleaving encoding, resulting in the l-th... i The code length of the wiry chain code is [value], and the information bit length is [value]. The remaining (s-d) wiry chain code is encoded, and the l′ [value] is [value]. i' Wirachain codes use linear block codes with a code length of and an information bit length of as the basic code, and the sequence c... (t) Initialize to an all-zero sequence; set the information sequence u Divide into sL groups. For the l-th dimensional zip code, divide into groups of length k. t,l -m t,l sequence u (t,l) With a length of m t,l sequence w (t,l) The data is fed into a multiplexer to obtain a length of k. t,l sequence a (t,l) The sequence is fed into a basic code encoder for encoding to obtain a codeword sequence. Simultaneously, the sequence is fed into a generalized integrated interleaved code encoder for encoding to obtain another codeword sequence. c (t,0) , c (t,1) ,…, c (t,s‑1) The encoded output sequence c at time t is obtained by feeding it into the multiplexer. (t) This invention has the advantages of simple coding, ease of implementation, and good performance.

The invention provides a distributed processing method for a model weight, and belongs to the technical field of artificial intelligence, and the method comprises the steps: S1, carrying out the feature extraction of a model weight file, obtaining the feature information of a model weight tensor, and enabling the feature information to be the data information of a preset bit length of the model weight tensor; and S2, performing hash fragmentation processing on the feature information, determining a storage node corresponding to each fragment, and storing each fragment to the storage node corresponding to each fragment. The method has the beneficial effects that the model weights are fragmented and stored in a plurality of nodes, so that the capacity demand of single storage equipment is reduced, the hardware cost and the management difficulty are reduced, and the storage reliability and expandability are improved; the distributed storage model weight is adopted, weight data can be obtained from a plurality of storage nodes in parallel, the loading time is greatly shortened, the model loading efficiency is improved, and the method is suitable for application scenes with high real-time requirements.

The invention discloses an execution uncertainty-oriented air edge computing resource allocation method, device and equipment and a storage medium, and relates to the technical field of air edge computing, and the method comprises the steps: obtaining user number information, edge server task information, bit length information, time delay constraint information and energy constraint information; determining a target system resource allocation probability based on the user number information, the edge server task information, the bit length information, the time delay constraint information and the energy constraint information; and controlling a system to carry out resource allocation based on the target system resource allocation probability, and completing execution uncertainty-oriented air edge computing resource allocation. According to the method and the device, the uncertainty factors in the dynamic environment are quantified into probability constraints, calculation is performed through the optimal resource allocation strategies corresponding to different scenes, and the resource allocation probability of the target system is obtained, so that the system performs resource allocation in a self-adaptive manner, and the utilization efficiency of the system resources is maximized.

This invention discloses a hardware optimization method for shared NTT in a hybrid application scenario of quantum-resistant cryptography ML-KEM and ML-DSA. For the three core basic operators in the NTT module—modular addition, modular subtraction, and modular multiplication—this invention redesigns the corresponding hardware implementation structure. Based on the design of ML-KEM with a smaller modulus bit length, it supports large-bit-width NTT operations by time-division multiplexing small-width arithmetic units, effectively reducing the hardware overhead of the underlying operators. For ML-DSA NTT operations, this invention proposes a dedicated pipeline structure that matches the improved operators. This structure optimizes register overhead through reasonable design of data flow paths and multiplexing mechanisms, further reducing system resource costs. This invention achieves compatibility support for multiple NTT parameters, thereby enabling the simultaneous completion of NTT operation tasks under different algorithms or parameter sets on the same hardware platform.

Methods, systems, and devices for wireless communications are described. A transmitting device may generate cyclic redundancy check (CRC) bits associated with a set of information bits using a CRC generation function configured to generate a plurality of CRC bit lengths, wherein one or more baseline polynomials associated with generating one or more first CRC bit lengths of the plurality of CRC bit lengths are nested within a plurality of polynomials associated with generating one or more second CRC bit lengths of the plurality of CRC bit lengths. The transmitting device may transmit the set of information bits and the CRC bits in accordance with the generating.

Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and / or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.

This arithmetic device causes a computer to execute: a processing step for, when the bit length of a key that is generated from a common key allocated for use in communication between a terminal device and a network and that is used for encryption and integrity assurance is longer than the bit length of an input key used in a predetermined algorithm, performing arithmetic processes different from each other on the bit string of the key generated from the common key and used for encryption and integrity assurance on the basis of a predetermined condition to obtain a bit string different from the bit string of the key generated from the common key and used for encryption and integrity assurance; and a hashing step for inputting the bit string obtained in the processing step to a predetermined hash function agreed in advance between the terminal device and the network to obtain a bit string having the same bit length as the bit length of the input key.

The present application discloses an information processing method and apparatus, a terminal device, and a storage medium. The method includes: based on a first bit length and / or a second bit length, determining a first rate matching output sequence length corresponding to first information. The first bit length is determined according in the number of bits of the first information and a code rate corresponding to the first information, and the second bit length is determined according to the number of bits of second information and a code rate corresponding to the second information, and the first information and the second information are transmitted on the same physical channel.

An apparatus according to various embodiments may receive resource configuration information for a physical uplink control channel (PUCCH) resource, divide the PUCCH resource into a plurality of unit resources on the basis of application of a sequence-based PUCCH format, segment an input bit sequence including input bits into a plurality of segments on the basis of a first bit length, select a first sequence for each of the plurality of segments, and transmit a PUCCH on the basis of the plurality of unit resources to which the plurality of first sequences selected for the plurality of segments are mapped.

This invention provides an adaptive tuning method and system for LSM-Tree key-value indexes. The method includes: configuring a load-aware module on the index receiving side; acquiring load data through the load-aware module and calculating the write load intensity in the load data; calculating and updating the maximum lazy layer based on the write load intensity; adjusting the storage index balancing strategy and tiering strategy adapted to the write load intensity using the maximum lazy layer based on the actual write load intensity; configuring multiple Bloom filter units for shards, generating Bloom filter unit groups, calculating the bit length index of the Bloom filter unit groups for shards, and controlling the number of Bloom filter unit functions based on the adaptation relationship between the bit length index of the Bloom filter unit groups and the actual write load; and embedding the index into the storage index for key-value access based on the adapted storage index balancing strategy and tiering strategy, and the adapted Bloom filter units.

Disclosed are a method and system for generating clock signal of I2S audio bus, and a dac circuit. The method includes: reading an audio file transmitted by the I2S audio bus, by a master controller; the master controller reading sampling rate, data bit length, and number of channels of the audio file, and, calculating data volume for each frame according to the data bit length and the number of channels, generating a master clock signal according to a multiplier requirement of a slave controller on the master clock signal, a frequency of the master clock signal being fs×X, wherein fs is the sampling rate, and X is a selected multiplier; and the slave controller receiving the master clock signal, and using the master clock signal as a clock source, to realize modulation and filtering for an audio digital-to-analog conversion.

An example method of video coding includes receiving a video bitstream comprising a plurality of blocks that includes a current block; selecting, for the current block, an inverse data driven transform (DDT) from a set of inverse DDTs, wherein each inverse DDT in the set of inverse DDTs is restricted to an 8-bit length; and reconstructing the current block by applying the inverse DDT to coded information of the current block.

This invention provides a CAN message analysis device capable of deciphering the format of a CAN message when the format is unknown. [Solution] The candidate data generation unit P3 is capable of performing an extraction process to extract data of a predetermined bit length from the data field of each CAN message having the same identification number ID, data that is stored in a predetermined range of digits of the entire digits of the data field; a conversion process to convert the extracted data into peak values ​​that constitute waveform data potentially indicating a change in any of the vehicle information; and a candidate data acquisition process to acquire the time series of the peak values ​​as candidate data. The candidate data generation unit P3 acquires multiple types of candidate data by performing a series of processes consisting of the extraction process, the conversion process and the candidate data acquisition process each time the digit range is shifted by one bit while keeping the predetermined bit length fixed.

A system is disclosed for securely communicating between a user device and a target device, which includes a user input receiving user inputs and a user device memory for storing at least one fixed dataset having a plurality of data bits and an inherent entropy. At least one predetermined harvest process is stored in ser device memory, which is operable within a main harvest process to distill the dataset to a predetermined bit length to define a private key of the user at a predetermined key length. A processor operates to execute the main harvest process to receive a unique user Personal Information Number (PIN) acquired by the user and having a plurality of digits associated therewith, and wherein the at least one predetermined harvest process is dependent on the user PIN and the value of at least one of the digits therein, such that the at least one predetermined harvest process is parameterized by the value of the at least one of the digits and operates differently for each value of the at least one of the digits. The processor applies the at least one predetermined harvest process to the dataset to distill the dataset down to the predetermined key length to define the private key, and then stores the private key to the user device. A target device memory and an encryption engine on the target device interface with a proximity-based link. The private key is transferred to the target device via the proximity-based link and an interface on the target device stores the transmitted private key in the target device memory.

The application discloses a natural language to SQL conversion method and system based on a large model, and comprises the following steps: constructing a reversible semantic mask tensor which simultaneously carries an explicit mask bit and an implicit semantic embedding; binding a differential distillation cache for the reversible semantic mask tensor; performing schema-agnostic semantic projection on the natural language query through the reversible semantic mask tensor with the mask bit being 0; switching the reversible semantic mask tensor to a schema-aware state according to a gradient difference vector provided by the differential distillation cache, and generating a structure-sensitive SQL output; converting the generated SQL execution result into a structure feedback signal and writing back as a new feedback difference vector; when the database structure signature changes, only extending the mask bit length of the reversible semantic mask tensor, and calling the differential distillation cache to perform local differential correction; and issuing a unified mask control instruction to the reversible semantic mask tensor. The application solves the technical problem of how to construct a schema-aware and schema-agnostic semantic representation.

The invention relates to an auxiliary memory method and system based on machine learning, and belongs to the field of machine learning, and the method comprises the steps: setting the length of a user input bit according to the length of a target memory word letter sequence; obtaining a memory feedback text input by the user; the Hamming distance between the target memory word letter sequence and the memory feedback letter sequence is calculated, and if the Hamming distance is larger than 0, the corresponding position of the target memory word letter sequence reckoned in the Hamming distance is marked as a forgetting position; and when the user interaction module displays the target memory word, the letters of the forgotten positions of the target memory word are displayed differently. According to the method and the device, the word memory effect can be distinguished more finely, the letters of the forgotten positions in the word are displayed differently in combination with the forgotten positions, the user is helped to focus on the part which is easier to forget, and the auxiliary memory effect is improved.

This arithmetic device causes a computer provided with at least a processor and a memory to execute: a processing step for, when the bit length of a common key allocated to be used for communication between a terminal device and a network is longer than the bit length of an input key used in a predetermined algorithm, performing arithmetic processes different from each other on the bit string of the common key on the basis of a predetermined condition to obtain a bit string different from the bit string of the common key; and a hashing step for inputting the bit string obtained in the processing step to a predetermined hash function agreed in advance between the terminal device and the network to obtain a bit string having the same bit length as the input key has.

Systems and methods are provided for performing a reduced precision number multiply-accumulate operation in a systolic array. Each row of the systolic array may receive a reduced input from a respective reducer. The reduced input may include reduced input data elements and / or reduced weights. The systolic array may lack support for an input having a first bit length, and the reducer may reduce a bit length of a given input from the first bit length to a shorter second bit length and provide the reduced input to the array. To reduce the bit length, the reducer may reduce the number of trailing bits of the input. In addition, the systolic array may receive a reduced and rounded input. The systolic array may propagate the reduced input through processing elements in the systolic array. Each processing element may include a multiplier and / or an adder to perform an arithmetic operation based on the reduced input.

The invention discloses an infrared transmitting device and method, an infrared receiving device and an infrared communication system, and relates to the technical field of infrared communication. The infrared transmitting device comprises a first processor used for modulating to-be-transmitted information with a preset bit length to obtain N first digital signals and outputting the N first digital signals in a target symbol period in sequence according to a target sequence, the preset bit length is larger than 1 bit length, N is an integer larger than 1 and smaller than or equal to Nmax, and N is an integer larger than 1 and smaller than or equal to Nmax; the Nmax is determined according to the target symbol period; the first control circuit is used for outputting a first control signal according to the first digital signal; and the infrared transmitter is used for transmitting an infrared signal under the control of the first control signal. According to the infrared communication device, the information to be sent is converted into the N infrared signals sent in the target symbol period, so that information sending with the preset bit length can be realized, and the spectrum utilization rate and the data transmission rate of infrared communication are improved.

This arithmetic device causes execution of: an extraction step for extracting a bit string having the same bit length as the bit length of an input key to be used in a prescribed algorithm when the bit length of a common key is longer than the bit length of the input key; an encryption step for generating ciphertext by executing encryption processing on a prescribed plaintext agreed between a terminal device and a network by using the extracted bit string as a key; and a key generation step for, when the bit length of the generated ciphertext is shorter than the bit length obtained by multiplying the bit length of the input key by an integer, repeatedly executing said processing until the bit length obtained by adding the generated ciphertext becomes longer than the bit length obtained by multiplying the bit length of the input key by an integer, dividing the obtained bit string for each bit length of the input key, and generating a key having the same bit length as the bit length of the input key on the basis of a plurality of bit strings obtained by the dividing.

To provide a moving image decoding device for executing PROF prediction.SOLUTION: Derive an affine prediction parameter from the motion vectors of the plurality of control points, derive a first motion vector difference array from the affine prediction parameter, and clip the first motion vector difference array to derive a second motion vector difference array; An affine prediction unit configured to derive a first variable for calculating a gradient from a prediction array sample array, derive a second variable from a second motion vector difference array and the first variable for calculating the gradient, and derive a prediction sample value from the prediction array sample array and the second variable, wherein the first motion vector difference array is clipped in a range using a fixed value independent of a pixel bit depth, and the fixed value is equal to 32.SELECTED DRAWING: Figure 13

One aspect of the present disclosure relates to a conversion device including an acquisition unit configured to acquire a first bit string having a first bit length L1; a conversion unit configured to convert, in accordance with conversion information that associates respective bit strings each having the first bit length L1 with bit strings each having a second bit length L2 uniquely assigned to the respective bit strings, the first bit string into a second bit string having the second bit length L2. The conversion information is created by searching for a clique that includes 2L1 or more nodes, from a graph including nodes and an edge representing the bit strings each having the second bit length L2 that satisfy a predetermined constraint condition.

The invention provides a communication method and a communication device applied to the field of wireless communication. In the technical scheme provided by the invention, the terminal can receive the RRC signaling and the first DCI, and determines that the bit length of the first field in the first DCI is the first value when the RRC signaling does not indicate the first configuration information. Wherein the first configuration information comprises M first elements, a first field in the first DCI is used for indicating one first element in the M first elements, the format of the first DCI is a DCI format used for scheduling data channels of N cells, the first element comprises N sub-elements, and N is a positive integer greater than or equal to 1; each sub-element in the N sub-elements is used for indicating one line in the configuration table of the first parameter of one cell in the N cells, and M and N are positive integers. According to the technical scheme provided by the invention, the understanding of the network equipment and the terminal on the bit length of the first field is consistent, and the system performance is improved.

The invention discloses a decoding method and electronic equipment. Belongs to the technical field of image processing. The embodiment of the method comprises the following steps: reading a first Huffman code of a first coding unit from a coding bit stream of a JPEG (Joint Photographic Experts Group) format image; a first additional bit length corresponding to the first Huffman code is inquired from a corresponding relation table, and the corresponding relation table is used for storing the corresponding relation between the Huffman code and the additional bit length; reading additional bit data from the coded bit stream based on the first additional bit length, and determining a discrete cosine transform (DCT) coefficient based on the first additional bit length and the additional bit data; and generating image data of the JPEG format image based on the DCT coefficient.

A device according to various embodiments may: receive resource configuration information regarding a physical uplink control channel (PUCCH) resource; divide the PUCCH resource into a plurality of unit resources on the basis of application of a sequence-based PUCCH format; segment an input bit sequence into a plurality of segments on the basis of a first bit length; determine a first sequence having a first length with regard to each of the plurality of segments; and transmit a PUCCH on the basis of the plurality of unit resources to which the plurality of first sequences determined with regard to the plurality of segments are mapped.

The embodiment of the invention discloses an out-of-order processing method and device for a data sequence, a chip, a storage medium and a product. The method comprises the steps of obtaining a normal data sequence capable of disrupting a password operation sequence; traversing the plurality of elements one by one from back to front from the last element of the data sequence, and determining a current random number based on the current bit length when traversing to the ith element corresponding to the current traversing position i; the current bit length is related to the number of traversed elements and the length of the data sequence, and the bit length of the current random number is the same as the current bit length; determining a to-be-exchanged position j based on the current random number and / or the current traversal position i and a size relationship between the current random number and the current traversal position i; and based on the current traversal position i and the to-be-exchanged position j, exchanging the ith element and the jth element to obtain a current out-of-order data sequence. According to the method and the device, the out-of-order processing efficiency of the data sequence can be improved.

The application provides a parallel interleaver and method suitable for 5G-LDPC, and is used for solving the technical problems of high complexity of interleaving address calculation and low throughput in the prior art. The parallel interleaver comprises a read-write cache module and a bit interleaving module connected in sequence, and a parameter calculation module and a parameter storage module connected in sequence; the output end of the parameter storage module is connected with the bit interleaving module; wherein the bit interleaving module comprises Q cyclic shift units arranged in parallel and a code word merging module cascaded with the output end of the Q cyclic shift units, and Q is greater than or equal to 1; the parameter storage module comprises an information storage unit and a counter connected in sequence. The implementation steps are as follows: 1. the read-write cache module stores the data after 5G-LDPC encoding; 2. the parameter calculation module calculates the bit length at the end of the interleaving layer; 3. the parameter storage module calculates the cyclic shift factor; and 4. the bit interleaving module obtains the interleaving result.

The bit length of the given key is compressed to generate a key of equal size to the key used in the cryptographic algorithm. [Solution] The computing device causes a computer, which includes at least a processor and memory, to perform the following steps: when the bit length of a common key assigned for use in communication between a terminal device and a network is longer than the bit length of an input key used in a predetermined algorithm, a processing step of obtaining a bit sequence different from the bit sequence of the common key by performing different arithmetic operations on the bit sequence of the common key based on predetermined conditions; and a hashing step of inputting the bit sequence obtained in the processing step into a predetermined hash function agreed in advance between the terminal device and the network, thereby obtaining a bit sequence having the same bit length as the bit length of the input key.

This invention provides a video metadata structuring device that reduces the data volume required to manage metadata and generates metadata-structured data that allows for quick access to the metadata. [Solution] The video metadata structuring device 1 includes an object recognition unit 10 that performs object recognition in the time direction of the video and generates a track ID, an identification candidate ID, and a plurality of recognition results for individual objects as metadata; a metadata encoding unit 21 that converts the values ​​of the plurality of recognition results for individual objects generated by the object recognition unit 10 into a data sequence of predetermined bit lengths; and a sparse tensor data embedding unit 22 that embeds the data sequence of the corresponding metadata into a sparse tensor data structure with the time-based track ID and identification candidate ID generated by the object recognition unit 10 as multidimensional axes.