198 results about "Bit-length" patented technology

Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reducer can receive a particular input and generate multiple reduced inputs from the input. The reduced inputs can include reduced input data elements and / or a reduced weights. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide multiple reduced inputs with second shorter bit-length to the array. The systolic array may perform multiply-accumulate operations on each unique combination of the multiple reduced input data elements and the reduced weights to generate multiple partial outputs. The systolic array may sum the partial outputs to generate the output.

A cyclic redundancy check bit determination method and system, the method including obtaining an information bit, determining, based on a first correspondence, that a check bit length is L, where L is a natural number, and where the first correspondence includes a correspondence among code length information of to-be-transmitted data including the information bit, length information of the information bit, and the check bit length, and determining a first check bit based on a first cyclic redundancy check (CRC) polynomial, where a length of the first check bit is the check bit length L, where a highest power of terms in the first CRC polynomial is Lmax, where Lmax is a positive integer, and where Lmax is greater than or equal to L.

The invention relates to the technical field of data processing, and discloses a logistics data transmission verification method and system based on hierarchical priority. The method comprises the steps of collecting logistics data, establishing a grading system according to business importance, and generating a weight matrix and a sensitivity matrix; calculating a data change difference value, and performing weighted operation with the matrix to output a deviation vector; extracting position, state and time information in the vector, and calculating correlation degree and consistency to generate a multi-dimensional check value; allocating coding bit length according to the check value, and performing dynamic Huffman coding to generate a data packet; and verifying the data packet, performing incremental decoding to recover information, and reconstructing a database state. The logistics data transmission verification method and device solve the problems that an existing logistics data transmission verification method is low in verification efficiency, cannot adapt to business differentiation requirements and is too large in verification overhead in a bandwidth limited environment, and the efficiency and pertinence of logistics data transmission verification are improved.

A method for decoding a picture comprising a virtual boundary from a coded video bitstream. The method includes determining one or more of a maximum picture width or a maximum picture height from one or more syntax elements S1 in the coded video bitstream and determining one or more of a current picture width or a current picture height from one or more syntax elements S2 in the coded video bitstream. The method also includes determining that a virtual boundary syntax element in the coded video bitstream is encoded with a bit length derived from (i) one or more of the maximum picture width or the maximum picture height or (ii) one or more of the current picture width or the current picture height. The method also includes deriving the bit length for the virtual boundary syntax element based on (i) the one or more of the maximum picture width or maximum picture height as a result of determining that a virtual boundary syntax element in the coded video bitstream is encoded with a bit length derived from one or more of the maximum picture width or the maximum picture height or (ii) the one or more of the current picture width or the current picture height as a result of determining that a virtual boundary syntax element in the coded video bitstream is derived from one or more of the current picture width or the current picture height. The method also includes decoding the virtual boundary syntax element from the bitstream based on the derived bit length and determining a spatial picture position of the virtual boundary based on the decoded virtual boundary syntax element.

The invention relates to the technical field of communication, and provides a downlink control information detection method and device, electronic equipment, a storage medium and a computer program product, and the method comprises the steps: carrying out the rate de-matching based on to-be-processed data, and obtaining the rate de-matching data; the to-be-processed data is obtained by performing resource element channel estimation and equalization in a control channel unit in a downlink control information blind detection process; performing polarization decoding on the rate de-matching data based on the aggregation level corresponding to the to-be-processed data to obtain decoded data; determining a target load length range from two load length ranges preset for the downlink control information based on the bit length information of the decoded data; wherein the two load length ranges are divided according to aggregation grades; and performing data verification on the decoded data based on the target load length range to obtain a detection result of the downlink control information. According to the invention, the detection efficiency of the downlink control information can be improved by reducing the calculation amount and time during detection of the downlink control information.

A method for data transmission is provided. The method includes: in response to the UE being in an inactive state, transmitting a first type acknowledged mode data protocol data unit (AMD PDU), wherein a bit length of a sequence number field of first type AMD PDU is less than a bit length of a sequence number field of a second type AMD PDU used in a connected state.

A method and system for processing a set of ‘k’ floating point numbers to perform addition and / or subtraction is disclosed. Each floating-point number comprises a mantissa (mi) and an exponent (ei). The method comprises receiving the set of ‘k’ floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (mi) with a bit-length of ‘b’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the mantissas of the ‘k’ floating-point numbers, the numbers having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length ‘b’ of the mantissa (mi). The method includes identifying a maximum exponent (emax) among the exponents ei, aligning the magnitude bits of the numbers (yi) based on the maximum exponent (emax) and processing the set of ‘k’ numbers concurrently.

The embodiment of the invention discloses a data processing method, a password service module, a chip and an electronic device. The password service module receives a password service request instruction; the password service request instruction comprises a to-be-processed password and a to-be-processed modulus; under the condition that the bit length of the to-be-processed password is smaller than or equal to the first length, determining an odd modulus according to the to-be-processed modulus, and performing modulo operation on the to-be-processed password by using the odd modulus to obtain a first quotient and a first modulus; wherein the modulus to be processed is an even number; the odd modulus is equal to the to-be-processed modulus plus 1; determining a model result according to the first quotient and the first model; wherein the modulo result represents a result of performing modulo operation on the to-be-processed password by using the to-be-processed modulus; under the condition that the bit length of the to-be-processed password is greater than the first length, splitting the to-be-processed password into a first integer and a second integer; and performing first operation processing based on the first integer, the second integer and the odd modulus to obtain a modulus result.

A system is disclosed for securely communicating between a user device and a target device, which includes a user input receiving user inputs and a user device memory for storing at least one fixed dataset having a plurality of data bits and an inherent entropy. At least one predetermined harvest process is stored in ser device memory, which is operable within a main harvest process to distill the dataset to a predetermined bit length to define a private key of the user at a predetermined key length. A processor operates to execute the main harvest process to receive a unique user Personal Information Number (PIN) acquired by the user and having a plurality of digits associated therewith, and wherein the at least one predetermined harvest process is dependent on the user PIN and the value of at least one of the digits therein, such that the at least one predetermined harvest process is parameterized by the value of the at least one of the digits and operates differently for each value of the at least one of the digits. The processor applies the at least one predetermined harvest process to the dataset to distill the dataset down to the predetermined key length to define the private key, and then stores the private key to the user device. A target device memory and an encryption engine on the target device interface with a proximity-based link. The private key is transferred to the target device via the proximity-based link and an interface on the target device stores the transmitted private key in the target device memory.

Provided is a memory access control unit that performs writing by dividing write data and an error correction code thereof into a plurality of memories, and acquires presence or absence of occurrence of a verify error in each of the plurality of memories related to the writing. In a case where the verify errors occur in at least any of the plurality of memories, an error bit length acquisition unit acquires bit lengths of the verify errors from the plurality of memories and a write control unit determines that the writing has succeeded if a total bit length of the verify errors falls within a range of a capability allocated to an error bit length tolerance of the error correction code, and determines that the writing has failed if the total bit length of the verify errors falls outside the range.

The invention discloses a dynamic quantization method for a low-bit weight and an activation value of a large language model, and the method comprises the following steps: 1, selecting a quantization data type according to different distribution characteristics of the weight and the activation value, employing 4-bit normal floating point quantization for the weight, and employing 8-bit dynamic tree quantization for the activation value; and 2, generating a quantization target code for the 4-bit weight and the 8-bit activation value, and obtaining the quantization target code by calculating quantile and / or exponential bit length. In addition, in the quantization process, the quantization precision can be improved by partitioning the data to be quantized and performing quantization and / or inverse quantization processing. The invention further discloses a dynamic quantization system for implementing the dynamic quantization method and application of the dynamic quantization method or system, and the dynamic quantization method or system has wide application value.

A method and arrangement for converting a digital file into a cryptographic challenge-response-pair mechanism is disclosed. An encrypted digital file is concatenated with a random nonce and subject to one-way cryptographic functions and / or extended output functions such that a result C* is obtained having a known bit length. This result is organized into a series of addressable segments. A random seed is generated and is used to derive a random bit stream that is parsed into segments, each of which is read as an address in C*. These segments are applied as challenges to C*, and the corresponding responses may be used as or to generate or store an encryption key.

The invention discloses a coding and decoding method for LDPC codes under time and frequency selective channels in an NAVDAT system, and the method comprises the steps: determining a basis matrix and an expansion factor Z according to an information bit length and a target code length of an input bit sequence before coding, and the Z is a positive integer; obtaining a low density parity check (LDPC) matrix based on the basis matrix and the expansion factor Z; the method comprises the following steps: encoding an input bit sequence by using a low density parity check (LDPC) matrix under an NAVDAT system time and frequency selective channel, wherein the code rate is 3 / 4 or 1 / 2; wherein a basis matrix of the LDPC matrix comprises a sub-matrix A and a sub-matrix B, if the basis matrix is expressed as an m-row n-column matrix, the sub-matrix A is an m-row n-m-column matrix, the sub-matrix B is an m-row m-column matrix, and the sub-matrix B comprises a double-diagonal structure matrix B1, a single-diagonal structure matrix B2 and a column B3 with the weight of 4; and outputting the coded or decoded bit sequence. According to the invention, the coding requirements of information bit sequences with various lengths can be met.

The invention discloses a communication method and a communication device, and the method comprises the steps: determining the number of coding bits corresponding to to-be-coded information, and determining the length of an LDPC code word according to the number of coding bits. The length of the LDPC code word and the number of coding bits meet the following conditions: when the number of coding bits is in a first value range, the length of the LDPC code word is a first code length; or, when the number of the coding bits is in a second value range, if the number of the coding bits is greater than or equal to the sum of the bit length corresponding to the to-be-coded information and the product of X and (1-R), the length of the LDPC code word is the first code length; otherwise, the length of the LDPC code word is the second code length. R is a coding rate, and X is a common multiple of denominators of all coding rates supported by the system. The longest LDPC code length supported by the system comprises 1944 * n; and / or X = Y + Zt, and Z is the least common multiple of denominators of all coding rates supported by the system. According to the method provided by the embodiment of the invention, the LDPC code length is determined, and the error control performance of the LDPC code can be ensured.

The invention relates to a method for determining the length of an LDPC code word in a UWB system and a related device. The method comprises the steps that a communication device determines the LDPC code length according to the bit length of information to be coded; when the information bit length is 0 to 324, selecting an LDPC code with 648 bits; when the length of the information bit is 325 to 648 and the length of the information bit is 973 to 1296, selecting the LDPC code with 1296 bits; and when the information bit length is 649-972, the LDPC code of 1944 bits is selected. By adopting the embodiment of the invention, better performance gain can be obtained. The application is applied to a UWB-based wireless personal local area network system, a sensing system and the like, and comprises 802.15 series protocols, such as an 802.15. 4 ab protocol or a next generation UWB protocol and the like; and the method can also be applied to wireless local area network systems of 802.11 series protocols, such as 802.11 be or the next generation thereof, Wi-Fi 8 and the like.

The present disclosure generally relates to a photon counting circuitry (11) configured to: determine whether there is a signal coincidence of at least two pixel signals (CLK1, CLK2) based on a degree of overlap in time of the at least two pixel signals (CLK1, CLK2) of the at least two pixels (SPAD1, SPAD2) of a photon counting time-of-flight sensor (10), for determining whether there is a signal coincidence of the at least two pixel signals (CLK1, CLK2) in a case where there is a signal coincidence, or to determine whether there is a signal coincidence of the at least two pixel signals (CLK1, CLK2) of the at least two pixels (SPAD1, SPAD2) of the photon counting time-of-flight sensor (10). Setting the counting operation mode to a coincidence counting operation mode in which counts of the at least two pixel signals are counted together; and generating a coincidence count signal (YES) for setting the count mode of operation to a coincidence count mode of operation. Preferably, the coincidence count signal corresponds to a temporally later pixel signal of the at least two pixel signals (CLK1, CLK2). For example, only one count will be recorded when no coincidence detection is detected. However, the count number of the common counter may be multiplied by two to reproduce the real number of events. Therefore, more counts can be accumulated, which can optimize the signal-to-noise ratio. Further, silicon area can be saved by taking into account correlations between adjacent / neighboring pixels in the sensor. This correlation is utilized to save the total counter bit length for two or more pixels in the group of pixels. Thus, this temporal correlation may be determined, and coincidence counts may be dynamically stored in a common (shared) counter.

The application discloses a short public parameter identity-based proxy re-encryption method based on an LWE problem, a trapdoor matrix, namely a short base on a lattice, is generated through a more simple and efficient trapdoor generation algorithm, the trapdoor matrix is taken as a master secret key MSK, an identity sequence with an l-bit length is divided into l' = l / β blocks through a block technology, the number of public parameter selection is reduced, the size of the master secret key and the public parameter is reduced, the public parameter calculation complexity is reduced, the calculation efficiency is improved, and the storage cost is reduced. The application satisfies adaptive IND-ID-CPA security under a standard model, has unidirectionality and limited multi-hop nature, and can resist collusion attacks.

A method for updating arbitrary length cryptographic keys having a bit length greater than 256 bits by a cryptographic key update system includes transmitting, by a sender, a first transmission to one or more controllers that are part of a vehicle and transmitting, by the sender, a second transmission to the one or more controllers, where the second transmission is a symmetric key encryption under a key encryption key of a concatenation of a plurality of parameters and a new cryptographic key. The sender derives the key encryption key by transforming an authentication key and a bit string of constant values based on an N-bit compression function. The method includes transmitting, by the sender, a third transmission to the one or more controllers that is an N-bit message authentication code under a first message authentication code (MAC) key of a concatenation of the first transmission and the second transmission.

A simplified implementation method for NR Polar coding and a computer-readable storage medium, relating to the field of communications. The method comprises: acquiring original information to be transmitted; on the basis of the original information, determining a bit sequence to be coded; storing said bit sequence according to a data type having a set bit length, so as to form a first array; and using a coding matrix to code said bit sequence so as to determine a code output sequence, comprising: acquiring each column vector in the coding matrix, and storing said column vectors according to the data type having the set bit length, so as to correspondingly form second arrays; storing the second arrays in a row sequence of the coding matrix so as to form a third array; and performing bit operation on the first array and the third array to determine the code output sequence, so as to perform corresponding processing prescribed by a protocol. Therefore, the present application reduces the complexity of coding operation, improves the coding efficiency and reduces memory resources required for coding.

The application discloses an intelligent decoding method for UART serial signals, which comprises the following steps: firstly, automatically recognizing unknown baud rate, data bit number, stop bit length and whether the UART protocol signal contains a parity check bit and other key parameters by using a large amount of data; and secondly, decoding and processing subsequent UART protocol signals according to cascaded decoding modules. Through the intelligent decoding of the UART protocol signal, the correct data information and baud rate can be accurately parsed without manually configuring or trying various decoding settings, so that the decoding process of the UART protocol signal can be greatly simplified, and the operation burden of the user can be reduced.

This invention discloses a multidimensional coupled chain code encoding method based on generalized integrated interleaving codes. It selects d-dimensional chain codes from s-dimensional chain codes for generalized integrated interleaving encoding, resulting in the l-th... i The code length of the wiry chain code is [value], and the information bit length is [value]. The remaining (s-d) wiry chain code is encoded, and the l′ [value] is [value]. i' Wirachain codes use linear block codes with a code length of and an information bit length of as the basic code, and the sequence c... (t) Initialize to an all-zero sequence; set the information sequence u Divide into sL groups. For the l-th dimensional zip code, divide into groups of length k. t,l -m t,l sequence u (t,l) With a length of m t,l sequence w (t,l) The data is fed into a multiplexer to obtain a length of k. t,l sequence a (t,l) The sequence is fed into a basic code encoder for encoding to obtain a codeword sequence. Simultaneously, the sequence is fed into a generalized integrated interleaved code encoder for encoding to obtain another codeword sequence. c (t,0) , c (t,1) ,…, c (t,s‑1) The encoded output sequence c at time t is obtained by feeding it into the multiplexer. (t) This invention has the advantages of simple coding, ease of implementation, and good performance.

Methods and devices are provided for rectifying a forward mapping coding bit length issue introduced by LMCS. In one method, a plurality of prediction samples, in a mapped domain, of luma component of a CU that is coded by a CIIP mode under LMCS framework is obtained, a plurality of residual samples, in the mapped domain, of the luma component of the CU is obtained, the plurality of prediction samples in the mapped domain is added to the plurality of residual samples in the mapped domain, resulting in a plurality of reconstructed samples, in the mapped domain, of the luma component, and the plurality of reconstructed samples of the luma component is converted from the mapped domain into an original domain based on a pre-defined plurality of inverse mapping scaling factors.

The invention provides a distributed processing method for a model weight, and belongs to the technical field of artificial intelligence, and the method comprises the steps: S1, carrying out the feature extraction of a model weight file, obtaining the feature information of a model weight tensor, and enabling the feature information to be the data information of a preset bit length of the model weight tensor; and S2, performing hash fragmentation processing on the feature information, determining a storage node corresponding to each fragment, and storing each fragment to the storage node corresponding to each fragment. The method has the beneficial effects that the model weights are fragmented and stored in a plurality of nodes, so that the capacity demand of single storage equipment is reduced, the hardware cost and the management difficulty are reduced, and the storage reliability and expandability are improved; the distributed storage model weight is adopted, weight data can be obtained from a plurality of storage nodes in parallel, the loading time is greatly shortened, the model loading efficiency is improved, and the method is suitable for application scenes with high real-time requirements.

The invention discloses an execution uncertainty-oriented air edge computing resource allocation method, device and equipment and a storage medium, and relates to the technical field of air edge computing, and the method comprises the steps: obtaining user number information, edge server task information, bit length information, time delay constraint information and energy constraint information; determining a target system resource allocation probability based on the user number information, the edge server task information, the bit length information, the time delay constraint information and the energy constraint information; and controlling a system to carry out resource allocation based on the target system resource allocation probability, and completing execution uncertainty-oriented air edge computing resource allocation. According to the method and the device, the uncertainty factors in the dynamic environment are quantified into probability constraints, calculation is performed through the optimal resource allocation strategies corresponding to different scenes, and the resource allocation probability of the target system is obtained, so that the system performs resource allocation in a self-adaptive manner, and the utilization efficiency of the system resources is maximized.

A method of determining a bit length of an IQ sample associated with a first data frame is provided. The method includes determining a first parameter associated with a payload length of the first data frame, and determining a second parameter indicative of a number of physical resource blocks in the first data frame. A presence of a compression header is detected based on the first parameter and the second parameter, and the bit length of the IQ sample is determined from one of the detected compression header and the first parameter and the second parameter. The bit length of the IQ sample may be determined automatically from information available in the data frame. This eliminates the need for manual entry of parameters into the packet analyzer and eliminates the likelihood of errors to due incorrect entry.

The present specification proposes a method and a device for indicating a bandwidth (BW) of a non-high throughput (HT) PPDU or a non-HT dup PPDU. The bandwidth proposed in the present specification may be at least one band among 320 MHz, 480 MHz, 560 MHz, and / or 640 MHz. For example, some bits of a service field having a 16-bit length, included in a data field, may be used to indicate 320 MHz, 480 MHz, 560 MHz, and / or 640 MHz, described above. The present specification proposes a combination of various bits indicating 320 MHz, 480 MHz, 560 MHz, and / or 640 MHz.

A processor obtains pieces of coded data, which are included in a bitstream and generated by coding tiles, and tile boundary independence information, which indicates whether each boundary between the tiles is a first or second boundary. Image data of a first tile is generated by decoding a first code string included in first coded data with reference to decoding information of a decoded tile when the tile boundary independence information indicates the first boundary, and by decoding the first code string without referring to the decoding information when the tile boundary independence information indicates the second boundary. A bit string is added after the first code string to make a bit length of first coded data a multiple of a predetermined N bits, with N being an integer greater than or equal to 2.

This invention discloses a hardware optimization method for shared NTT in a hybrid application scenario of quantum-resistant cryptography ML-KEM and ML-DSA. For the three core basic operators in the NTT module—modular addition, modular subtraction, and modular multiplication—this invention redesigns the corresponding hardware implementation structure. Based on the design of ML-KEM with a smaller modulus bit length, it supports large-bit-width NTT operations by time-division multiplexing small-width arithmetic units, effectively reducing the hardware overhead of the underlying operators. For ML-DSA NTT operations, this invention proposes a dedicated pipeline structure that matches the improved operators. This structure optimizes register overhead through reasonable design of data flow paths and multiplexing mechanisms, further reducing system resource costs. This invention achieves compatibility support for multiple NTT parameters, thereby enabling the simultaneous completion of NTT operation tasks under different algorithms or parameter sets on the same hardware platform.

The invention relates to the technical field of Internet of Things gateway management, in particular to a remote upgrading method of an Internet of Things gateway, which comprises an upper computer system equipped with a firmware upgrade package and an Internet of Things gateway to be upgraded, and is characterized in that the Internet of Things gateway is internally provided with a receiving RAM buffer area and an FLSAH area; the FLSAH area is divided into an FLSAH buffer area, an FLSAH backup area and an FLSAH execution area; according to the remote upgrading method, the specified length written into the FLSAH buffer area is set, the written length written into the FLSAH buffer area is recorded, the full-bit length of the current RAM buffer area is recorded, and upgrading data received by the RAM buffer area is repeatedly written into the FLSAH area, so that FLSAH resources are fully utilized, and firmware upgrading packages which are several times as large as the RAM buffer area can be received by occupying less RAM resources; remote upgrading of a gateway high-capacity program is realized; time management is carried out on the whole upgrading process, the problem that the gateway cannot operate normally due to upgrading time abnormity caused by upgrading failure or communication interruption and the like is avoided, and the upgrading effect is improved.

The present invention discloses a method for anti-partial leakage secret sharing with perfect security. The distributor selects an AONT and discloses all the inputs and outputs corresponding to the AONT; extracts pairs of inputs and outputs from all the inputs and outputs of the AONT, selects strings of a set bit length from each of them and denotes them as, and uses variables to represent the positions of in ; respectively uses algorithms to calculate the sub-secrets and sub-random numbers for the secret s and the random number r; secretly distributes the pseudo-sub-secrets to the participants through a secure channel; after at least participants contribute their own pseudo-sub-secrets, uses algorithms to gradually reconstruct and calculate the secret s. The solution of the present invention can be applied to a threshold secret sharing scheme with perfect security to generate an LLRSS scheme with perfect security.