521 results about "Logic cell" patented technology

The invention discloses an archive digitization full-life-cycle encryption integrity verification method and system, relates to the field of digital archive safety management, and is used for solving the problem of integrity and safety guarantee in archive digitization management. Logic units are divided through a semantic analysis engine, non-uniform blocks are generated based on sensitivity dynamic partitioning, local hash values are calculated, and a multi-level verification tree is constructed to generate root hash and a hash path mapping table; acquiring visitor identities, terminal environments and timestamps in each stage of an archive life cycle, generating state snapshots in combination with a hash path, and constructing a life cycle state snapshot chain; reconstructing a target logic unit verification path according to the access request, analyzing the structural difference between a current path and a historical snapshot chain through a path reconstruction type difference verification algorithm, and identifying structural offset, node tampering or path loss; and response control is triggered for abnormal verification, including session key updating and permission freezing, so that the security integrity guarantee of the digital archive in the full life cycle is improved.

The invention discloses a storage and calculation integrated server optimization method based on an NPU, relates to the technical field of server architecture, and discloses the storage and calculation integrated server optimization method based on the NPU by dynamically adjusting the configuration of an arithmetic logic unit, a multiplication and accumulation calculation unit and a cache module to generate a reconstruction calculation unit. By combining heterogeneous hardware performance evaluation and a task migration mechanism, dynamic optimal configuration and load balancing of computing resources are realized, the task execution efficiency can be improved, and the heterogeneous hardware collaborative energy efficiency ratio can be optimized.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

The invention relates to the technical field of information extraction, and discloses a long text news event element extraction method and system based on multi-agent collaboration, and the method comprises the following steps: constructing a large language model multi-agent system architecture; the central coordination agent receives the unstructured news text; the text segmentation agent outputs a logic unit and time description thereof; an event extraction agent extracts an event subject, an action and an object, and complements time and entity role information; the scene matching agent judges the fine-grained news scene category to which the scene matching agent belongs; the information extraction agent generates a structured event record; and the central coordination agent performs quality auditing and exception handling on each step of output to ensure the integrity and consistency of the output data. According to the method, the static relationship between the event main bodies can be constructed according to the structured event information through the relationship construction and context sorting agent, the event situation change is summarized based on the timeline, and the feasibility and the visualization of news event analysis of the system are improved.

The invention provides a data writing performance improvement method for a storage device and the storage device, is applied to the storage device, and relates to the technical field of storage. The method comprises the following steps: receiving to-be-written data, and determining a logic unit address and a target address mapping table of the to-be-written data; if neither the meter reading completion chain table nor the meter reading request chain table contains the target address mapping table, adding a meter reading request node in the meter reading request chain table; after reading of the target address mapping table is completed, the target address mapping table is updated; the method comprises the following steps: establishing a meter reading completion chain table and a meter reading request chain table, adding a node for reading a target address mapping table corresponding to data to be written into the meter reading request chain table, after reading is completed, moving the node into the meter reading completion chain table, and hiding time delay in a meter reading process in a time interval when a storage device receives data from a host, and the time delay of reading and writing the address mapping table in the random writing process is reduced, so that the random writing performance is improved.

The invention relates to the field of time capsule interaction, and discloses a time capsule interaction method and system, and the method comprises the steps: carrying out the logic unit segmentation of a to-be-sealed content, and building an encryption baseline which continuously evolves along with a time factor; under the support of an encryption baseline, performing fragmentation processing on the evolved and encrypted content, and triggering copy reconstruction through a witness mechanism when a node failure is detected; on the basis of a content storage link, continuously executing periodic health check in a storage period, and generating a state index in combination with a node online rate, key evolution integrity and user interaction history; when the key has an unrecoverable risk in the state index, triggering a multi-role collaborative recovery mechanism, and requiring a user side to submit a standby identity certificate; and after missing key reconstruction is completed, when preset opening time arrives, decryption operation is executed based on the key set which is finally evolved and completed and the recovered fragments, and an opening response with an interaction attribute is generated. The method has the advantage of improving the trust of the user.

This disclosure provides methods, devices, and systems for audio signal mixing. The present implementations more specifically relate to mixing audio signals from a microphone array by performing fixed beamforming to generate beams, reducing noise on the beams, and mixing the beams to generate a final audio signal for playback. In some aspects, an audio mixing system includes a fixed beamformer to generate beams from audio signals from a microphone array and noise reduction units (NRUs) to reduce a noise component of each audio beam. The system also includes logic to calculate a signal characteristic of each reduced noise audio beam to determine, based on the signal characteristics, the reduced noise audio beams that include a speech component. The logic also generates a gain for each audio beam based on the selection, with the gains used in beam mixing. In some aspects, the NRU includes a neural network noise reduction unit.

A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source / drain feature of a pass-gate transistor of one of the first plurality of the memory cells.

The invention relates to the technical field of current detection, and provides a multi-channel current time division multiplexing detection system and a current sampling chip. The system comprises a current sampling chip and a microcontroller. The current sampling chip is provided with a plurality of current sampling resistors, a plurality of current sampling signal switches, a logic unit and an operational amplifier module, and the plurality of current sampling signal switches are matched with the logic unit to switch current sampling voltage accessed to the operational amplifier module in a time division multiplexing mode, so that intensive detection of multi-channel current is realized; the overall scale of the system circuit is greatly reduced, and the hardware cost and the static power consumption are effectively reduced. Besides, a plurality of current sampling resistors and resistors in the operational amplifier module are arranged on the same chip in a matched manner, so that extremely high ratio consistency among the resistors is ensured, individual differences and mismatch errors caused by using a plurality of discrete devices are eliminated, and the accuracy of multi-channel current measurement is remarkably improved. And the consistency among the channels is particularly improved.

A memory system and an electronic system including the same are provided. The memory system includes a memory device configured to receive data, and a hot page logic configured to receive an address for the data, determine that the address is for a hot page based on an input frequency and an input order of the address, and create hot page information including the address that was determined as associated with the hot page such that a page migration operation of the data is performed.

The invention discloses a dynamic reconfigurable signal processing platform based on a ZYNQ architecture, and belongs to the technical field of digital signal processing, and the dynamic reconfigurable signal processing platform comprises a channel preprocessing unit, a high-speed AD sampling unit, a ZYNQ-PL logic unit and a ZYNQ-PS algorithm processing unit. A radio frequency signal is fed in from an antenna end and then enters the channel preprocessing unit, a balun circuit and a filter bank are adopted to carry out preselection filtering, amplification and conditioning on the radio frequency signal, and the signal is extracted and sent to the high-speed AD sampling unit; the high-speed AD acquisition unit converts a received analog signal into a digital signal and transmits the digital signal to the ZYNQ-PL logic unit, and the ZYNQ-PL logic unit is connected with the ZYNQ-PS algorithm processing unit through an AXI bus; wherein the ZYNQ-PL logic unit is composed of a static region and three dynamic regions, and is mainly used for realizing a logic part of a functional waveform and completing reconstruction and loading of the functional waveform; and the ZYNQ-PS algorithm processing unit completes algorithm processing, realizes modulation and demodulation of a functional waveform and realizes a functional algorithm.

The embodiment of the invention provides a bad block management method for storage equipment, and relates to the technical field of storage. The method comprises the following steps: in response to recognition of generation of a new bad block, determining whether a first logic unit where the new bad block is located has an idle reserved block or not; if yes, replacing the new bad block with the idle reserved block, and recording the replacement relationship between the idle reserved block and the new bad block in a first bad block management sub-table; and according to the updated first bad block management sub-table, updating a first bad block management sub-table copy in the first logic unit: writing a replacement relationship between an idle reserved block recorded in the first bad block management sub-table and a new bad block into the first bad block management sub-table copy, the sequence number of the meta-information field in the copy of the first bad block management sub-table is not updated, and the sequence number is used for indicating the number of times of obtaining the new reserved block. According to the method, a correct bad block management sub-table copy is determined through a sequence number of a meta-information field, and then a correct bad block management table is generated to manage bad blocks.

The invention provides a precision target optimization method and system adaptive to a variable precision arithmetic logic unit, a medium, a terminal and a program product. The method comprises the following steps: acquiring an output feature set of each group of an upper layer; the precision generation network layer generates a corresponding precision target according to the output feature set, and the ALU calculation layer generates a prediction result according to the generated precision target; the teacher model generates a reference target and a real label according to the output feature set; constructing a total loss function according to the calculated task loss, precision generation loss and adversarial loss; performing back propagation optimization on the student model based on the constructed total loss function; repeatedly and iteratively training the student model until convergence to obtain a final student model; and deploying the final student model to generate an optimal precision target corresponding to each group. According to the method provided by the invention, the fine precision adjustment of the bit granularity can be realized, the adaptive ability of the model is enhanced, and the matching degree of the precision and the task demand is improved.

The embodiment of the invention relates to a data processing method and device, computer equipment and a storage medium, and the method comprises the steps: carrying out the coding operation of an erasure code on first data under the condition of receiving a write-in request for the first data, and obtaining a plurality of logic units and a plurality of fragments; according to the first identifier of the logic unit and the second identifier of each fragment, writing the plurality of fragments into a storage node; and under the condition that a reading request is received, obtaining a target first identifier and a target second identifier of the second data, reading the plurality of target fragments of the second data from the plurality of storage nodes, and carrying out merging processing to obtain the second data. Therefore, the data can be divided into the fragments with the unique identifiers for storage in the writing stage, and the target fragments can be quickly positioned according to the logic addresses and the recovered data can be merged in the reading stage, so that the metadata query overhead is reduced, the reading and writing efficiency is improved, and the storage and network transmission cost is reduced; and the overall performance of the distributed storage system in a high-concurrency scene is improved.

The invention discloses an equipment abnormal behavior tracing method and system, a medium and a product, and relates to the field of Internet of Things security. According to the method, a resident service process is monitored to receive network data, version identification is dynamically updated, process fragment nodes are generated, logic isolation of process states is achieved, and precursor context association is established. Meanwhile, a cross-fragment data dependency edge is generated based on the resource version mapping table. And when an abnormal alarm is received, starting from a target process fragment node, and performing priority reverse search by utilizing the fragment association and the cross-fragment data dependency edge. According to the method and the device, the long-term running process is segmented into the discrete logic units according to the business boundary, so that the problems of state pollution and dependency explosion caused by existing full-life-cycle traceability graph construction are solved, irrelevant historical business interference is eliminated, and the accuracy of equipment abnormal behavior traceability is improved.

A system for scalable two-dimensional surface code comprises four sub-lattices of qubits, each selectively controlled by a set of analog lines. Eight sets of analog lines selectively control eight sets of inter-qubit couplers. The qubits and couplers have response homogenization devices comprising control structures to apply analog signals and DACs to apply static bias to qubits and couplers. A second surface code layer compensates for defective qubits. A quantum processor and a method of moving data within a quantum processor are described. The quantum processor has quantum logic units with a plurality of physical qubits and couplers. The logic unit has a plurality of logical qubit blocks making up 2-local interaction registers. A shift register block with one or more logical qubit blocks and merge blocks connecting adjacent logical qubit blocks are provided. The shift register block is selectively communicatively coupled to 2-local interaction registers by a merge block.

The invention relates to a multi-agent code production method and system and electronic equipment. Firstly, on the basis of manually screened source codes and LLM, codes are partitioned according to logic units, and a code knowledge base and an available tool list are formed through deep analysis, classification and storage; based on the user demand, generating a user intention and a tool calling demand through LLM deep analysis; then calling a knowledge base and a tool to generate a preliminary code; and finally, performing multi-round debugging and compiling on the preliminary code by referring to the code knowledge base until no error exists, and outputting a final code. According to the method, the code generation accuracy is improved, compliance is guaranteed through multi-modal analysis, grammar verification and the like, and deviation is reduced; reducing iteration through multi-round debugging, and reducing time consumption; cross-language migration adapts to multiple scenes, and efficiency improvement and quality guarantee are achieved.

The analog-to-digital conversion device includes a signal generating unit that generates a plurality of comparison voltages based on an analog input voltage and generates a plurality of comparison results of the plurality of comparison voltages based on a sampling period, a calculation unit that skips a comparison result generated by a comparison voltage having a smallest difference between the analog input voltages among the plurality of comparison voltages from the plurality of comparison results and generates an end of comparison based on a remaining plurality of comparison results, and a SAR logic unit that generates a digital signal corresponding to the end of comparison and stores information for each bit of the digital signal.

The invention provides a block chain-based clinical test data traceability and sharing platform. The block chain-based clinical test data traceability and sharing platform comprises the following modules: a life cycle state definition module, an on-chain event generation module, an identity verification module, a state transition logic unit and an event chain construction module. According to the invention, through cooperation of a life cycle state definition module, an on-chain event generation module, a state transition logic unit and an event chain construction module, key behaviors generated by a subject in the stages of screening, informed agreement, group entering, visit, adverse event processing, follow-up visit and the like are solidified into a chain event structure according to a time sequence; each event node comprises a behavior abstract, a preorder node hash and a timestamp, continuous association and accurate positioning of cross-stage operation are achieved, a clinical test is converted into a state transition chain capable of tracking the whole process from a fragment type data uplink, and the problem that a continuous behavior chain cannot be constructed in the prior art is solved.

According to the electroencephalogram acquisition and signal processing system and the information processing method provided by the invention, the control module is arranged, so that an upper computer is prevented from directly interacting with massive electroencephalogram acquisition data, and a data processing transfer station and a temporary control core are provided, so that the processing efficiency of electroencephalogram signals is improved. Furthermore, the control module comprises a processing unit and a programmable logic unit, the programmable logic unit can control a plurality of acquisition front ends in parallel to realize high-sampling-rate and high-passband signal acquisition, and the processing unit plays a role in connection in the whole electroencephalogram acquisition and signal processing system and can help the upper computer to control and manage the programmable logic unit, so that the accuracy of the electroencephalogram acquisition and signal processing system is improved. And meanwhile, a part of functions which can be realized without continuous data transmission are shared. The control module is provided with a programmable logic unit and a processing unit to realize parallel operation of two independent threads, namely a control flow thread and a data flow thread, so that the control flow and the data flow of the whole system are separated, and the data processing efficiency and the stability of the system are improved.

The utility model discloses an over-temperature and over-current protection circuit and a power adapter system, and the over-temperature and over-current protection circuit comprises an over-current monitoring assembly which is used for outputting a first fault signal lasting for a first preset time when the load voltage of a load circuit is greater than a set voltage. And the temperature control unit is used for outputting a second fault signal when the temperature of the load circuit exceeds the preset temperature threshold. And the first logic unit is electrically connected with the overcurrent monitoring assembly, the temperature control unit and the execution unit, and is used for controlling the execution unit to disconnect the load circuit when receiving the first fault signal and / or the second fault signal. And when the first logic unit receives the first recovery signal and / or the second recovery signal, the execution unit is controlled to close the load circuit again. The over-temperature and over-current protection circuit can prevent the load circuit from being disconnected for a long time in the over-temperature and over-current protection process.

The invention discloses an electronic equipment data analysis method and system, and relates to the technical field of electronic equipment resource management.The method comprises the steps that physical position information of a logic unit in electronic equipment is obtained; calculating a logical resource quantity set according to the physical location information; according to the logical resource quantity set, calculating a Gini coefficient of target logical resource distribution; and generating a target optimization strategy according to the Gini coefficient and a preset coefficient threshold. Electronic equipment data analysis can be realized by combining the quantity and distribution of the logic resources, and the analysis accuracy and the resource utilization rate are improved.

A semiconductor device includes a substrate comprising a logic cell region and a peripheral region extending around the logic cell region, a logic device in the logic cell region and comprising a plurality of source / drain patterns, an upper active contact on and electrically connected to one of the source / drain patterns, a lower active contact below and electrically connected to another of the source / drain patterns, a conductive structure that penetrates the peripheral region of the substrate, a plurality of peripheral upper wiring lines in the peripheral region and connected to the conductive structure, and a plurality of peripheral lower wiring lines in the peripheral region and connected to the conductive structure opposite the peripheral upper wiring lines. A bottom surface of the conductive structure is lower than a bottom surface of the lower active contact, relative to a bottom surface of the substrate.

A computing method is provided for configuring a tensor operation pipeline. In one example implementation, the method includes receiving a tensor operation pipeline definition and tensor data from a processor, at a configurable pipeline processing element array of a hardware accelerator. The method further includes, in each of a plurality of processing elements of the array, processing the tensor data by implementing a configurable tensor operation pipeline including one or more of the fixed tensor operation logic units according to the tensor operation pipeline definition. The method further includes outputting a tensor operation pipeline result based on the processing of the tensor data by each tensor operation pipeline in each processing element.

The invention provides an anti-interference system for micro-vibration detection. The system comprises a signal acquisition assembly and an anti-interference assembly connected with the output end of the signal acquisition assembly, and the anti-interference assembly comprises a hardware configurable filter network, an interference feature library and a control logic unit. The hardware configurable filter network receives an original vibration signal collected by the signal collection assembly as an input signal, and the control logic unit monitors the amplitude and / or frequency characteristics of the input signal in real time. And querying the interference feature library in which the mapping relationship between the interference source features and the filter configuration parameters is stored according to the monitored amplitude and / or frequency features of the input signal, so as to generate a control instruction corresponding to a query result based on the query result, thereby enabling the hardware configurable filter network to dynamically configure a filtering strategy. And filtering the environmental interference signal in the analog signal domain based on the configured filtering strategy.

The performance of an adaptive microelectronic circuit is at least partly configurable by selecting a value of an operating parameter. On processing paths, data inputs of register units are coupled to outputs of respective logic units for temporarily storing output values of said logic units. A plurality of timing event monitors respond to a digital value at a data input of a monitored register unit changing later than an allowable time limit by generating a timing event observation signal. The plurality of timing event monitors form a plurality of monitor groups, each monitor group being coupled to a branch of a triggering signal tree for coupling a monitor-group-specific triggering signal to the monitor group independently of other monitor groups. A control unit selectively allows or disables the propagation of the respective triggering signals into said branches of the triggering signal tree.

A zero-crossing detection circuit comprises a zero-crossing detection unit for comparing first and second monitoring target signals input from first and second nodes, between which an AC signal is applied, through diodes, respectively, thereby generating a first comparison signal, and a logic unit for estimating a zero-crossing of the AC signal from the first comparison signal, thereby generating a zero-crossing detection signal. The zero-crossing detection circuit preferably comprises a monitoring unit for adjusting the first and second monitoring target signals to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts cycles of the first comparison signal and uses the count value thereof to estimate the zero-crossing of the AC signal.

A positive temperature coefficient (PTC) heater apparatus is provided. The PTC heater apparatus includes a PTC heater, a resistance temperature detector (RTD) sensor mounted to the PTC heater and a controller logic unit electrically connected to the RTD sensor to receive readings of the RTD sensor, which, when the PTC heater is powered on, indicate whether the PTC heater is faulty.

A model training method and system based on artificial intelligence, medium and product, relate to the field of data processing systems or methods specially applicable to administrative, commercial, financial, management, supervision or prediction purposes, in which method, a plurality of model training task ordered logical execution sequences are parsed and extracted, tasks with the same preceding continuous logical unit are aggregated into a practical training task group, the preceding unit is separated from each task as a common baseline workflow, and the remaining independent training logic of each task is converted into an individualized derivative workflow. A first computing resource is allocated to perform a single centralized execution of the common baseline workflow, generating a baseline context slice. A second computing resource is allocated to each derivative workflow, the baseline context slice is distributed for environment reconstruction, and each individualized derivative workflow is executed in parallel, thereby completing the concurrent training of multiple tasks. The present application reduces the redundant consumption of computing power caused by high similarity training tasks and improves the overall efficiency of task scheduling.