833 results about "Logic cell" patented technology

The invention discloses an archive digitization full-life-cycle encryption integrity verification method and system, relates to the field of digital archive safety management, and is used for solving the problem of integrity and safety guarantee in archive digitization management. Logic units are divided through a semantic analysis engine, non-uniform blocks are generated based on sensitivity dynamic partitioning, local hash values are calculated, and a multi-level verification tree is constructed to generate root hash and a hash path mapping table; acquiring visitor identities, terminal environments and timestamps in each stage of an archive life cycle, generating state snapshots in combination with a hash path, and constructing a life cycle state snapshot chain; reconstructing a target logic unit verification path according to the access request, analyzing the structural difference between a current path and a historical snapshot chain through a path reconstruction type difference verification algorithm, and identifying structural offset, node tampering or path loss; and response control is triggered for abnormal verification, including session key updating and permission freezing, so that the security integrity guarantee of the digital archive in the full life cycle is improved.

The invention discloses a cloud server physical GPU acceleration capability release method and system, and belongs to the technical field of computer GPU capability release, and the method specifically comprises the steps: collecting GPU operation parameters in real time, carrying out the preprocessing, storing the GPU operation parameters in a shared state database, constructing a lightweight virtualization abstraction layer on a physical GPU, dividing the physical GPU into a plurality of logic units, and storing the logic units in a shared state database; the method comprises the following steps: establishing a physical GPU, constructing an isolation layer, utilizing a three-dimensional resource segmentation strategy, adopting a priority queue, a jump mechanism and a delay tolerance mechanism in a scheduling process, dynamically allocating logic unit resources of the physical GPU, accelerating release of GPU resources, and realizing unification and real-time updating of physical GPU state information among nodes of a cloud server through a distributed state synchronization mechanism; through dynamic task scheduling, a jumping mechanism, a delay tolerance mechanism and distributed state synchronization, efficient GPU resource management is realized, and GPU capability release is accelerated.

The present disclosure relates to a data processing method, a processor, a chip, and an electronic device. The method comprises: on the basis of an obtained control instruction, a control logic unit sequentially reads, from a memory to a dot product unit array, loop tiling data of data to be processed; the dot product unit array performs multiply-accumulate operation on the loop tiling data of the data to be processed that is received each time, and determines a loop tiling result of the data to be processed that is received each time; and on the basis of a plurality of loop tiling results obtained from the dot product unit array, the control logic unit determines a logic operation result of the data to be processed. The embodiments of the present disclosure can convert, into the reading and logic operation of multiple pieces of loop tiling data of the data to be processed, the reading and logic operation of the data to be processed, so that data with larger size can be processed under the condition that the hardware resources of the processor are not changed, and the pressure on the storage bandwidth is reduced.

The invention provides a single instruction stream multi-fiber programming model and a construction method thereof. The method comprises the following steps: constructing a task, thread and fiber three-level concurrent unit; different code logic units are configured for each task, and one task is mapped to a plurality of threads; mapping the threads and processor cores one by one, and mapping one thread to a plurality of threads; the threads within the thread are caused to share all registers on the processor core. According to the single-instruction-stream multi-fiber-thread programming model and the construction method thereof, the programming model is constructed based on the fiber threads, concurrent execution of asynchronous data streams is achieved, the resource utilization rate is effectively increased, and redundant calculation is eliminated.

Provided herein are systems, methods, and computer-readable media for improving results from machine learning models. An example method may include obtaining a user input query; generating first logits from a first language model by applying the first language model to the user input query; generating second logits from a second language model by applying the second language model to the user input query; combining the first logits and the second logits; determining probabilities associated with tokens from the combined first logits and second logits; and generating an output token based on the determined one or more probabilities.

The invention discloses a storage and calculation integrated server optimization method based on an NPU, relates to the technical field of server architecture, and discloses the storage and calculation integrated server optimization method based on the NPU by dynamically adjusting the configuration of an arithmetic logic unit, a multiplication and accumulation calculation unit and a cache module to generate a reconstruction calculation unit. By combining heterogeneous hardware performance evaluation and a task migration mechanism, dynamic optimal configuration and load balancing of computing resources are realized, the task execution efficiency can be improved, and the heterogeneous hardware collaborative energy efficiency ratio can be optimized.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

The invention discloses an air conditioner pipeline intelligent manufacturing and fault detection method based on digital twinning, relates to the technical field of data center infrastructure and fault detection, and aims to solve the problems of low construction efficiency, serious error accumulation, operation and maintenance logic faults and the like in a traditional process. The system is split into five functional modules through modular assembly design, a prefabricated straight pipe section and a combined section are combined with an equipment decoupling adjusting section to eliminate errors, and a standardized machining drawing is output; the quality is ensured through laser cutting, precise welding and galvanization processes, and high-precision field installation is achieved by combining paper number dual-mode guidance; a valve unique coding system is constructed based on BIM mapping, a two-dimensional code is generated to realize three-dimensional model calling and emergency guidance, a digital twin platform dynamically associates equipment control logic and a spatial position through a logic unit group, pushes hierarchical positioning guidance and links AR technology guidance operation when a fault occurs, and realizes full life cycle data tracing based on a block chain.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.

The invention discloses a low-orbit satellite-borne digital logic anomaly inspection method and a navigation baseband chip. Comprising the following steps: setting a corresponding verification data set and a configuration item for each digital logic unit; setting timing duration to inspect each digital logic unit in the chip at fixed time; judging whether the current polled digital logic unit is idle or not, if so, continuing to execute the subsequent steps, otherwise, switching to the next digital logic unit to continue polling; obtaining a verification data set and a configuration item corresponding to the current digital logic unit; configuring according to the configuration item, and sending standard data into a digital logic unit for starting to obtain feature data; judging whether the feature data is consistent with expected data or not, and if yes, judging that the digital logic unit works normally; if not, judging that the digital logic unit is abnormal; and repairing and reconfiguring the digital logic unit which is judged to be abnormal. According to the scheme of the invention, independent detection and anomaly repair of each digital logic unit can be realized, and the method is more targeted.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

The invention provides a logic separation type multi-servo-motor electric control system. According to the logic separation type multi-servo-motor electric control system, collaborative operation of high-precision control and data transmission is achieved through three independent loops. The system comprises a PC end computer, a control unit, an industrial bus, a servo driving unit, a logic unit and a controlled object. Wherein the first loop is formed by a PC end computer through a control unit, an industrial bus and a servo driving unit, and is responsible for transmitting a real-time control signal and position updating data; the second loop is returned to the PC end computer by the servo driving unit through the logic unit and is used for feeding back execution state data of the servo driver; and in the third loop, the controlled object is transmitted to the PC end computer through the logic unit, and real-time position signals and mechanical state data of the controlled object are transmitted. Through the logic layering and loop separation design, the control real-time performance, the data transmission reliability and the system expansibility of the system are remarkably improved, meanwhile, the signal interference during multi-task processing is reduced, and the system is suitable for a high-precision industrial automation scene.

The invention relates to the technical field of information extraction, and discloses a long text news event element extraction method and system based on multi-agent collaboration, and the method comprises the following steps: constructing a large language model multi-agent system architecture; the central coordination agent receives the unstructured news text; the text segmentation agent outputs a logic unit and time description thereof; an event extraction agent extracts an event subject, an action and an object, and complements time and entity role information; the scene matching agent judges the fine-grained news scene category to which the scene matching agent belongs; the information extraction agent generates a structured event record; and the central coordination agent performs quality auditing and exception handling on each step of output to ensure the integrity and consistency of the output data. According to the method, the static relationship between the event main bodies can be constructed according to the structured event information through the relationship construction and context sorting agent, the event situation change is summarized based on the timeline, and the feasibility and the visualization of news event analysis of the system are improved.

A high performance (HP) standard cell architecture for logic cells used in a semiconductor device or product. An example semiconductor device includes a plurality of cells surrounded by a cell boundary, and a backside power delivery network (PDN) routed to the plurality of cells. At least one cell of the plurality of cells has an arrangement of transistors within the cell boundary, the arrangement of transistors coupled together to generate an output signal at an output signal node. There is a metal 0 layer above the arrangement of transistors, the metal 0 layer includes one or more input signal traces and an output signal trace. The output signal trace and the input signal traces are substantially parallel inside the cell boundary and have a first width near the cell boundary; the output signal trace has a region of a wider metal 0 inside the cell boundary.

The invention provides a data writing performance improvement method for a storage device and the storage device, is applied to the storage device, and relates to the technical field of storage. The method comprises the following steps: receiving to-be-written data, and determining a logic unit address and a target address mapping table of the to-be-written data; if neither the meter reading completion chain table nor the meter reading request chain table contains the target address mapping table, adding a meter reading request node in the meter reading request chain table; after reading of the target address mapping table is completed, the target address mapping table is updated; the method comprises the following steps: establishing a meter reading completion chain table and a meter reading request chain table, adding a node for reading a target address mapping table corresponding to data to be written into the meter reading request chain table, after reading is completed, moving the node into the meter reading completion chain table, and hiding time delay in a meter reading process in a time interval when a storage device receives data from a host, and the time delay of reading and writing the address mapping table in the random writing process is reduced, so that the random writing performance is improved.

The invention provides an arithmetic logic unit parallel processing system and method and electronic equipment, and relates to the field of chip architecture processing, and the arithmetic logic unit parallel processing system comprises an instruction transmitting unit, a write-back unit and a plurality of ALU groups containing a plurality of arithmetic logic units; wherein the instruction transmitting unit is respectively connected with the input end of each ALU group; the output end of each ALU group is connected with the write-back unit; the input end of each ALU group is respectively connected with the input ends of all the arithmetic logic units in the current ALU group; the output end of each ALU group is respectively connected with the output ends of all the arithmetic logic units in the current ALU group; according to the scheme, the reduction instruction and the vector arithmetic logic operation can be realized by using the same arithmetic logic operation component, the number and the area of the vector arithmetic logic operation component are reduced, and the utilization rate of the vector arithmetic logic operation component is improved.

Embodiments disclose a level shifter including a logic unit configured to receive timing data and channel data and output an edge signal and a channel signal at a time point defined in the timing data, and a channel selection unit configured to select at least one channel from among a plurality of connected channels according to the channel signal and transmit the edge signal, and a display device including the same.

A monotonic capacitor digital-to-analog converter (CDAC) is provided. The CDAC includes a converter array comprising a plurality of CDAC units, wherein each CDAC unit comprises a logic unit, a switch, and a capacitor, and wherein each logic unit comprises a first input, a second input, and a third input. The CDAC further includes a first set of control lines, and each of the first set of control lines is connected to the first inputs of the logic units of the CDAC units in a corresponding column of the converter array. The CDAC further includes a second set of control lines, and each of the second set of control lines is connected to the second inputs of the logic units of the CDAC units in a corresponding row of the converter array, but is disconnected from the second input of the logic unit of a CDAC unit in the corresponding row and the last column of the converter array. Each of the second set of control lines is further connected to the third inputs of the logic units of the CDAC units in a row of the converter array adjacent to the corresponding row.

The invention relates to the field of time capsule interaction, and discloses a time capsule interaction method and system, and the method comprises the steps: carrying out the logic unit segmentation of a to-be-sealed content, and building an encryption baseline which continuously evolves along with a time factor; under the support of an encryption baseline, performing fragmentation processing on the evolved and encrypted content, and triggering copy reconstruction through a witness mechanism when a node failure is detected; on the basis of a content storage link, continuously executing periodic health check in a storage period, and generating a state index in combination with a node online rate, key evolution integrity and user interaction history; when the key has an unrecoverable risk in the state index, triggering a multi-role collaborative recovery mechanism, and requiring a user side to submit a standby identity certificate; and after missing key reconstruction is completed, when preset opening time arrives, decryption operation is executed based on the key set which is finally evolved and completed and the recovered fragments, and an opening response with an interaction attribute is generated. The method has the advantage of improving the trust of the user.

The invention discloses a low-power-consumption small-area on-chip temperature sensor based on an MOS tube and a method thereof. Comprising a temperature sensing circuit and an analog-to-digital conversion circuit which are connected with each other, the temperature sensing circuit is used for generating a voltage signal related to the temperature and outputting the voltage signal to the analog-to-digital conversion circuit to achieve digital quantization of the temperature, and the output end of a CTAT branch is connected to the input end of a switched capacitor amplifier through a buffer. The output end of the switched capacitor amplifier is connected to the non-inverting input end of the comparator, the output end of the PTAT branch is connected to the inverting input end of the comparator, the output end of the comparator is connected with the input end of the successive approximation logic unit, and the output end of the successive approximation logic unit is connected to the switched capacitor amplifier. According to the temperature sensing circuit structure, the problem of power supply sensitivity existing when voltage is generated is effectively solved, reference signals do not need to be additionally generated in the quantization process, and the problem of error accumulation is avoided.

The invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, counting fan-out information of all registers in a circuit netlist; s2, according to the fan-out information of the registers, screening out the registers of which the fan-out quantity is greater than a first preset threshold value and the logic series is greater than a second preset threshold value and which are located on the critical path, and generating a candidate register list; s3, obtaining register fan-out first-level combinatorial logic information; s4, performing clustering operation on the logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to the physical position relationship of the logic units; s5, associating the clustered logic units together and adjusting the connection relation of the logic units; s6, carrying out equivalence check; and S7, rearranging and wiring the circuit according to the modified netlist. The physical distance of a time sequence path can be effectively reduced, the time sequence performance of the circuit is optimized, and the method is suitable for large-scale integrated circuit design.

This disclosure provides methods, devices, and systems for audio signal mixing. The present implementations more specifically relate to mixing audio signals from a microphone array by performing fixed beamforming to generate beams, reducing noise on the beams, and mixing the beams to generate a final audio signal for playback. In some aspects, an audio mixing system includes a fixed beamformer to generate beams from audio signals from a microphone array and noise reduction units (NRUs) to reduce a noise component of each audio beam. The system also includes logic to calculate a signal characteristic of each reduced noise audio beam to determine, based on the signal characteristics, the reduced noise audio beams that include a speech component. The logic also generates a gain for each audio beam based on the selection, with the gains used in beam mixing. In some aspects, the NRU includes a neural network noise reduction unit.

The invention belongs to the technical field of semiconductor design automation, and provides a digital circuit engineering correction method and related equipment. The method comprises the following steps: after wiring of a digital circuit is completed, performing static time sequence analysis based on actual circuit resistance-capacitance parasitic parameters of a time sequence path in the digital circuit to obtain global time sequence information of the time sequence path, and screening out an abnormal time sequence path containing an abnormal logic unit from the digital circuit based on the global time sequence information; performing logic unit change on the abnormal time sequence path containing the abnormal logic unit, and performing wiring change on the digital circuit after the logic unit change; and if the wiring violation does not exist in the digital circuit, returning to execute the step of performing the static time sequence analysis based on the actual circuit resistance-capacitance parasitic parameter of each time sequence path in the digital circuit until the abnormal time sequence path does not exist in the digital circuit. According to the technical scheme provided by the invention, the correction efficiency of the digital circuit engineering can be improved.

The invention provides a solid state disk garbage collection method and device, electronic equipment and a storage medium. The method comprises the steps that first effective data parameters of a plurality of logic units in a storage system and second effective data parameters of physical blocks contained in the logic units are obtained; based on the first effective data parameter and the second effective data parameter, evaluating the distribution uniformity of the effective data in the plurality of logic units, and based on a distribution uniformity evaluation result, screening at least one target logic unit needing garbage collection; based on the second valid data parameter, determining a data migration mode of valid data stored in the target physical block in each target logic unit, and performing data migration; and after the effective data is migrated, judging whether the target physical block needs resource recovery or not according to a data migration mode of the effective data stored in the target physical block, and carrying out resource recovery on the target physical block needing resource recovery. Compared with the prior art, the screening precision can be improved, and the garbage recycling efficiency is improved.

According to an embodiment of the present disclosure, a processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand and a target operand. The target opcode indicates the vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading data to be processed. The target operand specifies a target storage location in the memory for writing a processing result. The processor also includes an arithmetic logic unit coupled to the instruction decoder and the memory. The arithmetic logic unit is configured to: read data to be processed from a source storage location in the memory; perform an arithmetic logic operation associated with the vector operation specified by the target instruction on the data to be processed; and write the processing result to a target storage location in the memory. In this way, the efficiency of vector calculations can be improved.

The invention belongs to the technical field of automatic driving, and particularly relates to a reasoning method, device and equipment of a visual language model for automatic driving. The method comprises the following steps: acquiring a token combination corresponding to a memory of a moment before a target moment and the probability of each token in the token combination in the visual language model; if the probabilities of all the tokens are greater than a preset threshold value, taking the memory of the previous moment as the memory of the target moment, if the tokens lower than the preset threshold value exist, segmenting the token combination into logic units, checking whether the tokens lower than the preset threshold value exist in each logic unit, and if the tokens lower than the preset threshold value exist in each logic unit, taking the memory of the previous moment as the memory of the target moment; if yes, refreshing the logic unit, and taking the memory of the previous moment after refreshing as the memory of the target moment; and based on the multi-view image flow and the memory of the target moment, utilizing the visual language model to generate an inference state and a meta-action for determining an automatic driving track.

A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source / drain feature of a pass-gate transistor of one of the first plurality of the memory cells.

The invention relates to the technical field of current detection, and provides a multi-channel current time division multiplexing detection system and a current sampling chip. The system comprises a current sampling chip and a microcontroller. The current sampling chip is provided with a plurality of current sampling resistors, a plurality of current sampling signal switches, a logic unit and an operational amplifier module, and the plurality of current sampling signal switches are matched with the logic unit to switch current sampling voltage accessed to the operational amplifier module in a time division multiplexing mode, so that intensive detection of multi-channel current is realized; the overall scale of the system circuit is greatly reduced, and the hardware cost and the static power consumption are effectively reduced. Besides, a plurality of current sampling resistors and resistors in the operational amplifier module are arranged on the same chip in a matched manner, so that extremely high ratio consistency among the resistors is ensured, individual differences and mismatch errors caused by using a plurality of discrete devices are eliminated, and the accuracy of multi-channel current measurement is remarkably improved. And the consistency among the channels is particularly improved.