Digital integrated circuit perceptible optimization before-wiring time sequence prediction method, electronic equipment and storage medium

Abstract

The invention discloses a perceptually optimized wiring time sequence prediction method for a digital integrated circuit, electronic equipment and a storage medium, and the method comprises the steps: constructing a heterogeneous graph according to a circuit netlist, fusing the heterogeneous graph with feature vectors corresponding to all units and interconnection lines, inputting the fused heterogeneous graph into a trained heterogeneous graph neural network, and obtaining graph network embedding; inputting the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding; splicing graph network embedding and convolutional network embedding to obtain multi-modal local embedding; constructing a feature sequence of the path according to a connection relationship between a logic unit and an interconnection line in the path by multi-modal local embedding, and inputting the feature sequence of the path into the trained Transform network to obtain a path delay residual prediction value after wiring; and adding the path delay value after layout and the path delay residual prediction value after wiring, and finally obtaining a path delay prediction value after wiring. According to the method, the path delay after wiring can be accurately and efficiently predicted before wiring.

Description

Technical Field

[0001] The invention relates to a pre-wiring timing prediction method, electronic equipment and storage medium capable of perceivably optimizing a digital integrated circuit, and belongs to the technical field of electronic design automation. Background Art

[0002] In the process of circuit physical design, multiple rounds of circuit optimization are usually required to achieve a compromise between power consumption, performance, and area. Static timing analysis is frequently called to check whether the circuit timing is closed and converged, so as to guide designers to fix timing violations in time and optimize the circuit. Timing analysis and timing optimization often take up 60% of the entire circuit design time, so the accuracy and efficiency of static timing analysis are crucial to circuit design.

[0003] The physical design of the circuit starts with the circuit netlist obtained after logic synthesis, and goes through the steps of floorplanning, layout, clock tree synthesis, wiring, etc., and finally generates the circuit layout. As the physical design proceeds, the timing analysis results of the circuit become more accurate. However, in the layout stage, since the circuit has not been wired at this time, the lack of the true parasitic parameters of the wire leads to a large difference between the timing analysis results at this time and the timing after wiring. Under advanced process nodes, the proportion of line delay is larger and the wiring behavior is more complex. Congestion, wire detours, metal layer allocation and other factors have an even greater impact on timing that cannot be ignored. And in the wiring stage, in addition to the timing changes caused by wire parasitic parameters, some necessary timing optimization measures, such as gate size adjustment, threshold voltage allocation, buffer insertion, logic reorganization, etc., will also cause the timing to change again.

[0004] Therefore, how to perform accurate pre-routing timing estimation in the layout stage has become an urgent problem to be solved in circuit physical design. Inaccurate pre-routing timing estimation results will have a great impact on the quality and efficiency of circuit layout and routing. Summary of the invention

[0005] Purpose: In order to overcome the deficiencies in the prior art, the present invention provides a digital integrated circuit perceptually optimized pre-wiring timing prediction method, electronic device and storage medium, which can accurately predict the path delay after wiring in the layout stage before wiring, thereby effectively guiding the circuit pre-wiring design and optimization.

[0006] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:

[0007] In a first aspect, a method for predicting timing before wiring a digital integrated circuit that can perceive optimization specifically includes:

[0008] The static timing analysis of the laid-out circuit is performed to obtain the characteristic vectors corresponding to the circuit layout and each unit and interconnection line as well as the path delay value after layout, and the characteristic matrix of the layout is constructed according to the physical information of the circuit layout.

[0009] Construct a heterogeneous graph based on the circuit netlist, fuse the heterogeneous graph with the feature vectors corresponding to each unit and interconnection line, and input them into the trained heterogeneous graph neural network to obtain the graph network embedding. Input the feature matrix of the layout into the trained convolutional neural network to obtain the convolutional network embedding. Concatenate the graph network embedding with the convolutional network embedding to obtain a multimodal local embedding.

[0010] The multimodal local embedding is spliced ​​according to the connection relationship between the logic units and the interconnection lines in the path to obtain the embedding of the timing stage of the path, and the feature sequence of the path is constructed by the embedding of the timing stage of the path. The feature sequence of the path is input into the trained Transformer network to obtain the post-routing path delay residual prediction value; the post-layout path delay value is added to the post-routing path delay residual prediction value to finally obtain the post-routing path delay prediction value.

[0011] As a preferred solution, the characteristic vectors corresponding to each unit and interconnection line include but are not limited to: the timing of each unit, the physical information of each unit and the physical information of the interconnection line. The characteristic matrix of the layout includes: unit density, pin density, rectangular uniform line density and pin rectangular uniform line density.

[0012] As a preferred solution, the heterogeneous graph is constructed according to the circuit netlist, and the heterogeneous graph is fused with the feature vectors corresponding to each unit and interconnection line, and then input into the trained heterogeneous graph neural network to obtain the graph network embedding. The feature matrix of the layout is input into the trained convolutional neural network to obtain the convolutional network embedding. The graph network embedding and the convolutional network embedding are spliced ​​to obtain a multimodal local embedding, which specifically includes:

[0013] According to the connection relationship of the circuit netlist, a heterogeneous graph is constructed using unit nodes, pin nodes and interconnection lines, wherein unit timing arcs, interconnection line timing arcs and edges connecting unit nodes and pin nodes are three different adjacency relationships.

[0014] The heterogeneous graph is fused with the feature vectors corresponding to each unit and interconnection line, and then input into the trained heterogeneous graph neural network to output the graph network embedding, where the graph network embedding includes: graph network local node embedding and graph network local edge embedding.

[0015] The feature matrix of the layout is input into the trained convolutional neural network to obtain the convolutional network embedding, wherein the convolutional network embedding includes: unit convolutional network embedding, pin convolutional network embedding, unit timing arc convolutional network embedding and interconnection line timing arc convolutional network embedding.

[0016] The unit timing arc graph network embedding, interconnection line timing arc graph network embedding and unit timing arc convolution network embedding and interconnection line timing arc convolution network embedding in the graph network local edge embedding are spliced ​​according to the positional relationship of the timing arcs in the layout in the corresponding network to obtain a multimodal local embedding, wherein the multimodal local embedding includes: multimodal local embedding of unit timing arcs and multimodal local embedding of interconnection line timing arcs.

[0017] As a preferred solution, the multi-modal local embedding is spliced ​​according to the connection relationship between the logic units and the interconnection lines in the path to obtain the embedding of the timing phase of the path, and the feature sequence of the path is constructed by the embedding of the timing phase of the path, which specifically includes:

[0018] Each unit timing arc and the subsequent interconnection line timing arc are regarded as a timing stage, and each timing path is composed of a sequence of multiple timing stages.

[0019] The multimodal local embedding of the unit timing arc and the multimodal local embedding of the interconnection timing arc are spliced ​​according to the connection relationship between the unit timing arc and the interconnection timing arc in the timing stage to obtain the embedding of the timing stage of the path.

[0020] The embeddings of the temporal stages of the path are constructed as a feature sequence of the path.

[0021] As a preferred solution, the method for obtaining the trained heterogeneous graph neural network and convolutional neural network specifically includes:

[0022] The characteristic matrix of the layout of the circuit after layout, and the characteristic vectors corresponding to each unit and interconnection line are obtained.

[0023] Obtain delay values ​​of cells and interconnect lines of a routed circuit corresponding to a laid out circuit.

[0024] The characteristic matrix of the layout of the circuit after layout, the characteristic vectors corresponding to each unit and interconnection line, and the delay values ​​of the units and interconnections of the circuit after wiring are used as training samples. The training samples are used to train the convolutional neural network, the heterogeneous graph neural network and the local prediction model composed of the first multi-layer perception mechanism to obtain the trained convolutional neural network and heterogeneous graph neural network.

[0025] As a preferred solution, the method for obtaining the trained Transformer network specifically includes:

[0026] The circuit layout corresponding to the laid-out circuit and the feature vectors corresponding to each unit and interconnection line are obtained, and the feature matrix of the layout is constructed according to the physical information of the circuit layout.

[0027] Construct a heterogeneous graph based on the circuit netlist, fuse the heterogeneous graph with the feature vectors corresponding to each unit and interconnection line, and input them into the trained heterogeneous graph neural network to obtain the graph network embedding. Input the feature matrix of the layout into the trained convolutional neural network to obtain the convolutional network embedding. Concatenate the graph network embedding with the convolutional network embedding to obtain a multimodal local embedding.

[0028] The multimodal local embedding is spliced ​​according to the connection relationship between the logical units and the interconnection lines in the path to obtain the embedding of the timing stage of the path, and the characteristic sequence of the path is constructed by the embedding of the timing stage of the path.

[0029] Obtain a path delay value of a routed circuit corresponding to a laid out circuit.

[0030] The feature sequence of the path and the path delay value of the circuit after wiring are used as training samples. The training samples are used to train the entire prediction model composed of the Transformer network, the pooling layer and the second multi-layer perceptron to obtain a trained Transformer network.

[0031] In a second aspect, a computer-readable storage medium stores a computer program, which, when executed by a processor, implements a pre-routing timing prediction method for digital integrated circuits that can perceive optimization as described in any one of the first aspects.

[0032] According to a third aspect, a computer device includes:

[0033] Memory, used to store instructions.

[0034] The processor is used to execute the instructions so that the computer device performs the operations of the pre-routing timing prediction method for digital integrated circuits that can perceive optimization as described in any one of the first aspects.

[0035] Beneficial effects: The present invention provides a digital integrated circuit that can perceive optimization before wiring timing prediction method, electronic device and storage medium. First, the present invention establishes a local timing prediction model based on graph neural network and convolutional neural network, which aligns and fuses the netlist heterogeneous graph embedding and layout image embedding to generate multimodal local embedding of circuit pins, units and interconnects for local timing prediction. Secondly, the present invention establishes a global timing prediction model based on transformer network, which uses the multimodal local embedding of units and interconnects generated by the local timing prediction model as feature input, and captures the global physical and timing correlations on the timing path through a multi-head self-attention mechanism to generate a multimodal global embedding of the timing path for global timing prediction.

[0036] Compared with the traditional static timing analysis process, the advantages of the present invention are as follows:

[0037] The present invention can accurately and efficiently predict the path delay after wiring before wiring, can better discover the optimization difficulties, and thus effectively guide the design and optimization of circuits before wiring, which is of great significance for accelerating the digital integrated circuit design process. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of the overall framework of the delay prediction method of the present invention.

[0039] Figure 2 Schematic diagram of the local time series prediction method.

[0040] Figure 3 This is a schematic diagram of the convolutional neural network structure used in the present invention.

[0041] Figure 4 Schematic diagram of the global time series prediction method. DETAILED DESCRIPTION

[0042] The following is a clear and complete description of the technical solutions in the examples of the present invention in conjunction with the accompanying drawings in the examples of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present invention.

[0043] The present invention will be further described below in conjunction with specific embodiments.

[0044] Embodiment 1:

[0045] This embodiment introduces a method for predicting timing before wiring a digital integrated circuit that can be perceived and optimized. Figure 1 As shown, the post-wiring delay prediction refers to the prediction of the delay after circuit optimization and wiring in the layout stage of the back-end design process of the digital integrated circuit; the delay prediction includes the prediction of the local delay and the path delay; the local delay includes the delay of the timing arc of the combinational logic unit and the timing arc of the metal interconnection line; the path contains at least two levels of combinational logic units and does not contain a sequential logic unit; the method includes the following steps:

[0046] Step S1: Physically design the circuit netlist after logic synthesis by using a physical design tool. The design steps include layout planning, layout, layout optimization, clock tree synthesis, and routing to obtain the circuit after layout and the circuit after routing.

[0047] Step S2: Extract sample data, perform static timing analysis on the circuit after layout and the circuit after routing in step S1 respectively through a static timing analysis tool, extract the timing, physical information and post-layout path delay value of each unit and interconnection line from the static timing report of the circuit after layout and the circuit layout information, extract the connection relationship of the circuit netlist, construct the circuit layout and the feature vectors corresponding to each unit and interconnection line; construct the feature matrix of the layout according to the physical information of the overall circuit layout; extract the delay values ​​of the corresponding units, interconnections and paths as labels from the static timing analysis report of the circuit after routing.

[0048] Furthermore, the characteristic vectors corresponding to each unit and interconnection line include, but are not limited to: the timing of each unit, the physical information of each unit and the physical information of the interconnection line.

[0049] The timing of each unit includes: the timing arc delay of the unit at this level, and the timing of the pins of the unit at this level. Among them, the timing arc delay of the unit at this level selects the worst delay among the timing arcs of the unit at this level; the timing of the pins of the unit at this level selects the longest conversion time among the pins of the unit at this level.

[0050] The physical information of each unit includes: the fan-in number of the unit at this level, the driving strength of the unit at this level, the fan-out number of the unit at this level, the type of the unit at this level, the threshold voltage type of the unit at this level, whether the driving strength of the unit at this level can be adjusted, the threshold voltage type and the physical information of the unit pin.

[0051] The physical information of the interconnection line includes: the distances between the driving pins and the receiving pins of the interconnection line in the x-axis and y-axis directions respectively.

[0052] The timing arc delay of the current level unit includes: the rising delay and the falling delay of the timing arc.

[0053] The timing of the unit pins at this level includes: the rising and falling transition time of the unit pins, and the rising and falling timing margin of the unit pins.

[0054] The physical information of the unit pin includes: whether the unit pin is an output pin, the rising and falling capacitance of the unit pin, and the position coordinates of the unit pin in the x and y directions.

[0055] Furthermore, the feature matrix of the layout includes: cell density, pin density, rectangular uniform line density (RUDY) and pin rectangular uniform line density (pinRUDY).

[0056] The cell density represents the number of cells in the grid and is expressed as follows:

[0057] (1)

[0058] in, is the cell density of the grid in row k and column l, is the grid at row k and column l, and is the coordinate of the cell c in the x-axis and y-axis directions. The cell coordinate is defined as the coordinate at the center of the cell.

[0059] Pin density indicates the number of pins in the grid.

[0060] The rectangular uniform line density represents the sum of the rectangular uniform line densities of all interconnects within the grid.

[0061] The rectangular uniform line density expression of an interconnection line e is as follows:

[0062] (2)

[0063] in, is the rectangular uniform line density of the interconnection line e of the grid in the kth row and lth column, , , and are the minimum coordinate of the network in the x-axis direction, the maximum coordinate in the x-axis direction, the minimum coordinate in the y-axis direction, and the maximum coordinate in the y-axis direction, respectively. Represents the grid where the interconnection line e is located.

[0064] The pin rectangular uniform line density represents the rectangular uniform line density of interconnection lines connecting pins, wherein the pin rectangular uniform line density in the grid is the sum of the pin rectangular uniform line densities of all pins in the grid.

[0065] Furthermore, the circuit layout is divided into 512×512 grids.

[0066] S3: Use the circuit netlist connection information to construct a heterogeneous graph, and input the feature vectors of the cells and interconnects into the heterogeneous graph neural network for aggregation and update to obtain the graph network embedding. Input the feature matrix of the layout into the convolutional neural network to obtain the convolutional network embedding. According to the position of the cells and interconnects in the circuit layout, splice the two embeddings to obtain a multimodal local embedding, and then pass it through a multi-layer perceptron to obtain the delay prediction value of the cells and interconnects. Use the post-wiring cell and interconnect delays extracted in step S2 as labels to train the heterogeneous graph neural network and the convolutional neural network.

[0067] Furthermore, the step S3 is as follows: Figure 2 , 3 As shown, specifically including:

[0068] S31: constructing a heterogeneous graph using unit nodes, pin nodes and interconnection lines according to the connection relationship of the circuit netlist, wherein unit timing arcs, interconnection line timing arcs and edges connecting unit nodes and pin nodes are three different adjacency relationships.

[0069] S32: According to the feature vectors corresponding to each unit and interconnection line, an initial feature vector is assigned to each corresponding node and edge in the heterogeneous graph, and then each node and edge initial feature vector is passed through the fully connected layer, and the output dimension is d n The feature vector of the node , the feature vector of the edge with dimension de ,in, represents the feature vector of the 0th layer node, Represents the feature vector of the unit node at layer 0, The feature vector representing the pin node at level 0; represents the eigenvector of the edge at level 0, The feature vector representing the temporal arc edge of the 0th layer unit, The feature vector representing the timing arc edge of the interconnect line at layer 0.

[0070] S33: Input the heterogeneous graph and the feature vectors of nodes and edges into the heterogeneous graph neural network to perform neighbor aggregation and information update of node and edge embeddings. For the k-th layer network, the embedding output by the k-1th layer is used for aggregation, first through edge aggregation and node aggregation, and the edge and node embeddings before and after aggregation are then added and normalized through residual connections to finally obtain the node and edge graph network embedding output by the k-th layer network.

[0071] S34: The total number of layers of the heterogeneous graph neural network is K1. The output embedding of each layer of the network is connected through residual connection and then input into the second fully connected layer to retain the node and edge embeddings from different neighbor aggregation distances in each layer. After splicing and transformation, the local node embedding H and the local edge embedding E of the graph network are finally generated. The process expression is as follows:

[0072] { H = W h K 1 [ H ( 1 ) ‖ … ‖ H ( K 1 ) ] E = W e K 1 [ E ( 1 ) ‖ … ‖ E ( K 1 ) ] (3)

[0073] in, represents the node weight parameter of the K1th layer network, represents the node embedding of the layer 1 network, represents the node embedding of the K1-th layer network, represents the edge weight parameter of the K1th layer network, represents the edge embedding of the layer 1 network, represents the edge embedding of the K1-th layer network, Indicates splicing.

[0074] S35: Input the feature matrix of the layout into the convolutional neural network, first through the K2 encoder layer, and then through the K2 decoder layer. After each encoder layer, the height and width of the image will be reduced by half, but the number of channels will be doubled; after each decoder layer, the height and width of the image will be doubled, but the number of channels will be reduced by half. There is a jump connection between the encoder layer and the decoder layer to splice the images of the same size output by the encoder layer and the decoder layer, and output the next decoder layer. The output image of the decoder has the same size and number of channels as the input. Finally, the output image passes through another output convolutional layer to obtain 4 types of convolutional network local embeddings for the units, pins, unit timing arcs, and interconnect timing arcs in the circuit, respectively. .

[0075] S36: Embedding the local edges of the graph network into the unit temporal arc graph network in E , Interconnection timing arc graph network embedding and convolutional network local embedding Mid-unit temporal arc convolutional network embedding , Interconnection Line Sequential Arc Convolutional Network Embedding According to the position relationship of the timing arc in the layout, the graph network embedding in the corresponding grid point is spliced ​​with the convolutional network embedding to obtain the multimodal local embedding of the unit timing arc. Multimodal local embedding of interconnect timing arcs .

[0076] Furthermore, the heterogeneous graph neural network adopts a heterogeneous graph attention network (HGAT).

[0077] Furthermore, the convolutional neural network adopts a U-type convolutional neural network.

[0078] S4: After training the heterogeneous graph neural network and convolutional neural network, the multimodal local embedding after splicing the outputs of the two networks is spliced ​​according to the connection relationship in the circuit and the unit-interconnection rule to obtain the embedding of the timing stage. Then, according to the connection relationship of each stage in the timing path, the feature matrix of each timing path is constructed and input into the Transformer network to obtain the difference between the predicted path delay after wiring and after layout. After outputting through pooling and multi-layer perceptron, the predicted path delay after wiring is obtained. The path delay after wiring extracted in step S2 is used as the label to train the Transformer network.

[0079] Furthermore, the step S4 is as follows: Figure 4 As shown, specifically including:

[0080] S41: Serialize the timing paths in the circuit. Each unit timing arc and its subsequent interconnection timing arc are considered as a timing stage, and each timing path is considered as a sequence of multiple timing stages. The multimodal local embeddings are spliced ​​according to the connection relationship of the timing stages to obtain the embedding of the timing stages. The initial features of each timing stage in the timing path constitute the initial feature sequence of the timing path, which will generate the global embedding of the timing path through sequence learning.

[0081] S42: During the input embedding process, there is a dedicated trainable embedding layer for each input feature sequence, which converts each element in the input feature sequence into a dim dimension. k That is, the input feature sequence with dimension (samples, max_len) is converted to a vector with dimension (samples, max_len, dim k ), where samples is the number of samples, max_len is the maximum number of paths, dim k is the word vector dimension specified by the kth feature sequence in the embedding layer, k=1,2,…,n, and n is the number of feature sequences. In the position encoding process, the trigonometric functions shown in formulas (4) and (5) are used to help the network understand the position relationship of the features of each level of the path in the sequence. Where pos represents the position of a feature value in the sequence, pos =1,2,…,max_len, m is the dimension index of the position encoding sequence of the feature value, m=0,1,…,dim k / 2-1, where the even dimension (2m) is encoded using the sine function (sin), and the odd dimension (2m+1) is encoded using the cosine function (cos). The dimension of the output tensor after position encoding is also (samples, max_len, dim k ). That is, the position coding sequence of the feature value at the feature sequence pos has a coding value of PE at 2m. (pos,2m) , the encoding value at 2m+1 is PE (pos,2m+1) For each feature sequence, the positional encoding output tensor is added to the input embedded output tensor to obtain n dimensions (samples, max_len, dim k )

[0082] (4)

[0083] (5)

[0084] S43: Merge the n new tensors in step S42 to obtain a tensor with a dimension of (samples, max_len, dim) as the input X of the multi-head self-attention mechanism, where dim=dim1+dim2+…+dim n , n is the number of input feature sequences. The j-th row vector of X is the comprehensive feature expression of the j-th level unit in the path in terms of timing and physical information, j=1,2,…,max_len. Through three trainable matrices W i Q , W i K , W i V , i=1,2,…,h, perform h linear transformations on X respectively, and obtain h groups of word vectors with dimensions of d k = dim / h matrix Q i , K i 、V i , h is the number of heads of the self-attention mechanism, Q, K, and V represent query, key, and value respectively. i , K i 、V i The attention function is executed in parallel. The calculation formula of the dot product-based attention mechanism is formula (6). First, calculate Q i With K i Transpose the dot product and divide by the coefficient d k 1 / 2 , then the weight matrix C is obtained by the softmax operation, and finally the weight matrix C is multiplied by V i Get the dimension d k The matrix Z i , which is the calculation result of the attention mechanism Attention (Q i ,K i ,V i ). The elements in the ath row and bth column of the weight matrix C can be considered as the timing and physical correlation between the ath level unit and the bth level unit in the path, a=1, 2,…,max_len; b=1,2,…,max_len, and the matrix Z i The number of row vectors is the same as the input X, so Z i The row vector has similar unit timing and physical meaning as X.

[0085] (6)

[0086] Merge the calculation results of the h head attention mechanism head i , i=1,2,…,h, and through a trainable matrix W OPerform a linear transformation to obtain the output MultiHead(X) of the multi-head self-attention mechanism. The calculation formula of the multi-head self-attention mechanism is formula (7), where X is the input of the multi-head self-attention mechanism, W i Q , W i K , W i V , W O is a trainable matrix, i=1,2,…,h.

[0087] (7)

[0088] S44: Add the input X and output MultiHead(X) of the multi-head self-attention mechanism in step S43 and normalize them to avoid gradient vanishing and gradient exploding. The output of the normalization layer of the multi-head self-attention mechanism can be expressed as formula (8), where LayerNorm() is the output function of the normalization layer.

[0089] (8)

[0090] S45: Connect the standardized output of the multi-head self-attention mechanism in step S44 to a fully connected feedforward neural network, where the neurons in two adjacent layers are fully connected. First, the input is linearly transformed, then passed through the linear rectification activation function max(0,s), where s is the input of the linear rectification activation function, and finally passed through a linear transformation. t is the input of the fully connected feedforward neural network, W1, b1 and W2, b2 are the parameters of the two linear transformations respectively, and the output calculation formula of the fully connected feedforward neural network is formula (9):

[0091] (9)

[0092] S46: Add the input t and output FFN(t) of the fully connected feedforward neural network in step S45 and normalize them to avoid gradient vanishing and gradient exploding. The output of the normalization layer of the connected feedforward neural network can be expressed as formula (10), where LayerNorm() is the output function of the normalization layer.

[0093] (10)

[0094] S47: Connect the output of the fully connected feedforward neural network normalization layer in step S46 to the pooling layer, flatten the three-dimensional data into two-dimensional data, and connect it to the fully connected (dense) layer for nonlinear transformation, and randomly discard some information through the dropout function to prevent overfitting. Then merge the data with the pre-routing path delay value features after nonlinear transformation and random information discarding, and nonlinearly transform the merged data into one dimension to obtain the residual prediction value of the path delay before and after wiring.

[0095] Furthermore, the transformer network includes: input embedding and position encoding, multi-head self-attention mechanism, fully connected feedforward network, addition and normalization.

[0096] S5: Input the circuit layout connection information and feature vectors of each unit and interconnection line extracted after step S2 of the circuit to be predicted into the trained heterogeneous graph neural network, and obtain the graph network embedding output of each unit and interconnection line after aggregation. Input the feature matrix of the extracted layout into the trained convolutional neural network, and obtain the corresponding convolutional network embedding output of each unit and interconnection line according to the positional relationship of each unit and interconnection line in the circuit layout. The two different embedding outputs are spliced ​​according to the positional relationship of the unit and interconnection line in the circuit layout to obtain the multimodal local embedding of each unit and interconnection line.

[0097] S6: The multimodal local embedding of the cells and interconnects obtained in step S5 is concatenated according to the connection relationship between the logic cells and the interconnects in the path to obtain the timing phase embedding of the path, and the characteristic matrix of the timing path is constructed by the timing phase embedding of the path, and the matrix is ​​input into the trained Transformer network to obtain the residual prediction value of the path delay after routing. The post-layout path delay value is added to the post-routing path delay residual prediction value to finally obtain the post-routing path delay prediction value.

[0098] Embodiment 2:

[0099] This embodiment introduces a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, a pre-routing timing prediction method for digital integrated circuits that can perceive optimization as described in any one of Embodiments 1 is implemented.

[0100] Example 3

[0101] This embodiment introduces a computer device, including:

[0102] Memory, used to store instructions.

[0103] The processor is used to execute the instructions so that the computer device performs the operations of a pre-routing timing prediction method for digital integrated circuits that can perceive optimization as described in any one of Embodiment 1.

[0104] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0106] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0107] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0108] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for predicting timing before wiring a digital integrated circuit that can be perceived and optimized, characterized in that: Specifically include: Perform static timing analysis on the circuit after layout to obtain the characteristic vectors corresponding to the circuit layout and each unit and interconnection line as well as the path delay value after layout, and construct the characteristic matrix of the layout according to the physical information of the circuit layout; Construct a heterogeneous graph based on the circuit netlist, fuse the heterogeneous graph with the feature vectors corresponding to each unit and interconnection line, and input them into the trained heterogeneous graph neural network to obtain graph network embedding; input the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding; splice the graph network embedding with the convolutional network embedding to obtain multimodal local embedding; The multimodal local embedding is spliced ​​according to the connection relationship between the logic units and the interconnection lines in the path to obtain the embedding of the timing stage of the path, and the feature sequence of the path is constructed by the embedding of the timing stage of the path. The feature sequence of the path is input into the trained Transformer network to obtain the post-routing path delay residual prediction value; the post-layout path delay value is added to the post-routing path delay residual prediction value to finally obtain the post-routing path delay prediction value.

2. The method for predicting timing before wiring a digital integrated circuit with perceptual optimization according to claim 1, characterized in that: The characteristic vectors corresponding to each unit and interconnection line include but are not limited to: the timing of each unit, the physical information of each unit and the physical information of the interconnection line; the characteristic matrix of the layout includes: unit density, pin density, rectangular uniform line density and pin rectangular uniform line density.

3. The method for predicting timing before wiring a digital integrated circuit with perceptual optimization according to claim 1, characterized in that: The method comprises constructing a heterogeneous graph according to the circuit netlist, fusing the heterogeneous graph with the feature vectors corresponding to each unit and interconnection line, and inputting the resultant into a trained heterogeneous graph neural network to obtain a graph network embedding; inputting the feature matrix of the layout into a trained convolutional neural network to obtain a convolutional network embedding; and splicing the graph network embedding with the convolutional network embedding to obtain a multimodal local embedding, which specifically includes: According to the connection relationship of the circuit netlist, a heterogeneous graph is constructed using unit nodes, pin nodes and interconnection lines, wherein unit timing arcs, interconnection line timing arcs and edges connecting unit nodes and pin nodes are three different adjacency relationships; After fusing the heterogeneous graph with the feature vectors corresponding to each unit and interconnection line, the result is input into the trained heterogeneous graph neural network, and the graph network embedding is output, wherein the graph network embedding includes: graph network local node embedding and graph network local edge embedding; Input the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding, wherein the convolutional network embedding includes: unit convolutional network embedding, pin convolutional network embedding, unit timing arc convolutional network embedding and interconnection line timing arc convolutional network embedding; The unit timing arc graph network embedding, interconnection line timing arc graph network embedding and unit timing arc convolution network embedding and interconnection line timing arc convolution network embedding in the graph network local edge embedding are spliced ​​according to the positional relationship of the timing arcs in the layout in the corresponding network to obtain a multimodal local embedding, wherein the multimodal local embedding includes: multimodal local embedding of unit timing arcs and multimodal local embedding of interconnection line timing arcs.

4. The method for predicting timing before wiring a digital integrated circuit with perceptual optimization according to claim 1, characterized in that: The multi-modal local embedding is spliced ​​according to the connection relationship between the logic units and the interconnection lines in the path to obtain the embedding of the timing phase of the path, and the feature sequence of the path is constructed by the embedding of the timing phase of the path, which specifically includes: Each unit timing arc and the subsequent interconnection line timing arc are regarded as a timing stage, and each timing path is composed of a sequence of multiple timing stages; The multimodal local embedding of the unit timing arc and the multimodal local embedding of the interconnection timing arc are spliced ​​according to the connection relationship between the unit timing arc and the interconnection timing arc in the timing stage to obtain the embedding of the timing stage of the path; The embeddings of the temporal stages of the path are constructed as a feature sequence of the path.

5. The method for pre-routing timing prediction of a digital integrated circuit with perceptual optimization according to claim 1, characterized in that: The method for obtaining the trained heterogeneous graph neural network and convolutional neural network specifically includes: Obtaining a characteristic matrix of the layout of the circuit after layout, and characteristic vectors corresponding to each unit and interconnection line; Obtaining delay values ​​of cells and interconnect lines of a routed circuit corresponding to a laid out circuit; The characteristic matrix of the layout of the circuit after layout, the characteristic vectors corresponding to each unit and interconnection line, and the delay values ​​of the units and interconnections of the circuit after wiring are used as training samples. The training samples are used to train the convolutional neural network, the heterogeneous graph neural network and the local prediction model composed of the first multi-layer perception mechanism to obtain the trained convolutional neural network and heterogeneous graph neural network.

6. The method for predicting timing before wiring a digital integrated circuit with perceptual optimization according to claim 1, characterized in that: The method for obtaining the trained Transformer network specifically includes: Obtain the circuit layout corresponding to the laid-out circuit and the feature vectors corresponding to each unit and interconnection line, and construct a feature matrix of the layout according to the physical information of the circuit layout; Construct a heterogeneous graph based on the circuit netlist, fuse the heterogeneous graph with the feature vectors corresponding to each unit and interconnection line, and input them into the trained heterogeneous graph neural network to obtain graph network embedding; input the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding; splice the graph network embedding with the convolutional network embedding to obtain multimodal local embedding; The multi-modal local embedding is spliced ​​according to the connection relationship between the logical units and the interconnection lines in the path to obtain the embedding of the time sequence phase of the path, and the feature sequence of the path is constructed by the embedding of the time sequence phase of the path; Obtaining a path delay value of a routed circuit corresponding to a laid out circuit; The feature sequence of the path and the path delay value of the circuit after wiring are used as training samples. The training samples are used to train the entire prediction model consisting of the Transformer network, the pooling layer and the second multi-layer perceptron to obtain a trained Transformer network.

7. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, a pre-routing timing prediction method for digital integrated circuits that can be perceptibly optimized is implemented as claimed in any one of claims 1 to 6.

8. A computer device, characterized in that: include: A memory for storing instructions; The processor is used to execute the instructions so that the computer device performs the operations of the pre-routing timing prediction method for digital integrated circuits that can be optimized perceptually as described in any one of claims 1 to 6.

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