3235results about "Computer aided design" patented technology

A dynamic vision system includes a variable focus liquid lens optical assembly. The dynamic vision system includes a variable lighting assembly. The dynamic vision system includes a control system configured to adjust one or more optical parameters and data collected from the variable focus liquid lens optical assembly in real time. The dynamic vision system includes a control system configured to adjust the variable lighting assembly. The dynamic vision system includes a processing system that dynamically learns on a training set of outcomes, parameters, and data collected from the variable focus liquid lens optical assembly to train a set of machine learning models to control the variable focus liquid lens optical assembly to optimize collection of data for processing by the set of machine learning models.

The invention discloses a pulse stable output control method and system for an ns-level high repetition frequency fast pulse power supply, and relates to the technical field of automatic control, the system is composed of a plurality of functional modules, and the system comprises a self-adaptive absorption module, a control module and an output control module, and the self-adaptive absorption module obtains power supply parameters through real-time sampling, and the power supply parameters comprise load impedance and switch tube parasitic parameters; dynamically optimizing R and C parameters of the RCD absorption circuit and the active clamping circuit based on power supply parameters; the feed-forward prediction module is used for extracting derivative state information according to the power supply parameters, acquiring load current feed-forward and resonant circuit states based on the derivative state information, modeling based on the load current feed-forward and resonant circuit states, and predicting the drain-source voltage valley bottom moment of the switch tube; and the multi-section variable impedance transmission module adopts a three-section variable impedance structure, performs broadband impedance matching based on R and C parameters of the optimized RCD absorption circuit and the active clamping circuit, inhibits pulse leading edge reflection distortion, and outputs undistorted pulse signals.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

The invention discloses a graph mapping method based on precise synthesis, and the method comprises the steps: constructing a precise synthesis structure library based on NPN equivalence classes, and inputting the precise synthesis structure library into a Boolean network; k-Cut cutting enumeration is carried out on the input Boolean network, a truth table is calculated, cutting is matched with a structure in a precise comprehensive structure library through Boolean matching, and rapid search is realized in combination with NPN classification; the overlay network is generated through multi-round mapping optimization, logic sharing nodes are mined in combination with structural hash, and the multi-round mapping optimization comprises delay-oriented mapping, global area topological optimization and local accurate area optimization; and a new target network is generated based on the optimized overlay network, redundant nodes are removed, and final network construction is completed. According to the method, manual intervention is not needed through full-process automatic mapping and a redundancy removal mechanism, the labor cost of a technical mapping link in chip design is remarkably reduced, and the method is particularly suitable for efficient design of complex circuits and emerging majority of logic base technologies.

The invention provides a chip design and verification system and method.The system comprises a tool chain integration and automation module, the tool chain integration and automation module is provided with a tool containerization unit and a multi-physics field collaborative optimization unit, and the tool containerization unit is used for containerizing and packaging an EDA tool into an independent functional unit; each EDA tool container comprises a complete runtime environment, a dependency library and a license; the multi-physics field collaborative optimization unit is used for acquiring design parameters of the chip and evaluating the performance of the chip design scheme; the system further comprises a chip particle heterogeneous integration module which is used for carrying out system modeling and layout planning on the chip according to the received chip design file and carrying out multi-physics field simulation on a chip model. The system further comprises a security and credibility verification module which is used for carrying out vulnerability detection and security analysis on the chip design file in a credible environment in the chip design process. The invention further provides a working method of the system. According to the invention, the problem of isolation of a chip design tool chain can be avoided.

The invention provides a chip interconnection line delay prediction method and device, equipment and a storage medium, and the method comprises the steps: combining geometric design parameters generated in a chip wiring stage with electrical attribute parameters, and generating a distributed RC network model; carrying out electromagnetic field solving on interconnection lines of the distributed RC network model, extracting coupling capacitance parameters of interconnection line segments, and generating a parasitic parameter file; correcting the resistance value and the capacitance value of the parasitic parameter file according to the PVT environment data of the chip interconnection line, and generating target RC network data; inputting the target RC network data and the interconnection line delay value of the parasitic parameter file into a preset deep neural network for training to obtain a first delay prediction result; and fusing the first delay prediction result with a second delay prediction result calculated by the distributed RC network model to generate a delay prediction value. According to the scheme, the accurate delay prediction value can be generated in a complex interconnection wiring environment, and the accuracy of delay prediction is improved.

The invention discloses a distributed layout information reading method and system, a storage medium and electronic device.The distributed layout information reading method comprises the steps that a task configuration file is read through a master control node, the task configuration file comprises layout information configuration, and the layout information configuration comprises a layout processing area and a single task processing area; the main control node is used for dividing the layout processing area according to the single-task processing area to obtain a plurality of sub-task areas, and each sub-task area corresponds to one sub-task; adopting the master control node to respectively distribute the plurality of subtasks to the corresponding slave nodes according to the distribution strategy; the slave node sends a layout reading request corresponding to the subtask to a target database based on a load balancing mechanism; returning layout information corresponding to the layout reading request to the slave node through the target database; and performing corresponding task processing on the layout information through the slave node, and returning a processing result to the master control node. The layout information reading efficiency can be improved.

The invention provides a design method of a high-uniformity Bitter coil, which belongs to the field of Bitter coils, and comprises the following steps: calculating the maximum electromagnetic stress of a first Bitter coil; on the basis of the thickness of the Bitter piece, the thickness of the Bitter piece is gradually increased according to a set increment, the thickness of the Bitter piece is obtained, a second Bitter coil is obtained, a turn coil in the center area of the first Bitter coil is replaced with a turn of the second Bitter coil, a new coil is obtained, the number of turns is gradually increased from one turn according to the step length of one turn, and the number of turns is gradually increased according to the step length of one turn; the magnetic field uniformity is smaller than a set value, and the coil height is smaller than a set height; calculating the center field of the coil, and selecting the highest number of turns of the center field; the invention further provides a Bittter coil. And the annular conductive pad processing workload is saved.

The invention relates to the technical field of circuit board conductivity detection, and discloses a circuit board conductivity detection method and system based on deep learning, and the method comprises the steps: obtaining high-resolution image data and circuit design parameters of a to-be-detected circuit board, and generating a circuit board feature data set; calculating theoretical impedance distribution of each area of the circuit board by using a physical constraint neural network based on the circuit board feature data set, and outputting an impedance prediction parameter set; inputting the impedance prediction parameter set and the circuit symbol rule into a neural symbol inference device to generate a conductance fault diagnosis result; and obtaining diagnosis results of a plurality of detection sites, executing cross-site diagnosis fusion, and outputting a unified circuit board conductivity detection report. The method overcomes the limitation that a traditional visual detection method cannot identify electrical characteristic defects, and solves the detection problem of hidden faults such as discontinuous impedance of the high-frequency circuit board.

The invention discloses a code generation method and system based on multi-objective reinforcement learning, and belongs to the technical field of digital integrated circuit design, and the method comprises the following steps: S1, generating an SFT training data set; s2, generating an MORL data set; s3, performing supervision and fine tuning on the model by taking the SFT training data set as input, so that the model masters the basic RTL code generation capability; s4, taking the MORL data set as input to train the model after supervision and fine tuning in the S3, and realizing multi-objective optimization; and S5, according to a user demand, describing a multi-target constraint through vector rewards, screening non-dominated candidate codes by using Pareto optimization to obtain an optimal RTL code, and outputting the optimal RTL code, vector reward details and a PPA equilibrium curve. According to the method and the system, basic constraints are met, and meanwhile generation of RTL codes with PPA indexes capable of being customized according to requirements is achieved.

The invention discloses a time sequence convergence method and device based on a clock tree, and relates to the technical field of circuit design. The method comprises the following steps: performing automatic layout on devices; determining a time sequence path needing to be optimized in the one-to-many structure time sequence path; performing establishment time sequence margin optimization, and determining a setting pattern of useful clock skew adjustment based on the optimized establishment time sequence margin; determining the number of buffers based on the setting pattern of useful clock skew adjustment and the optimized setup time sequence margin, and generating a clock tree; on the basis of the generated clock tree, determining whether the time sequence violation of the retention time of the time sequence path needing to be optimized meets a preset requirement or not, and if the preset requirement is not met, adjusting the setting pattern of the useful clock skew adjustment, and returning to the step of generating the clock tree; and completing automatic wiring based on the clock tree meeting the predetermined requirement. According to the invention, the problem of power consumption increase caused by restoration of Hold time sequence violation can be solved.

The invention provides a biphase composite magnetic material magnetically controlled reactor electromagnetic transient simulation method, device and equipment and a medium, and relates to the technical field of power equipment magnetic material testing and electromagnetic transient simulation. According to the invention, the test winding is arranged on the excitation winding of the magnetically controlled reactor, and multi-dimensional means of obtaining total iron loss through an open circuit test, obtaining magnetic hysteresis loss through a frequency reduction test, obtaining copper loss and leakage reactance through a short circuit test and the like are combined, so that separation of magnetic hysteresis loss, eddy current loss and additional loss can be realized; a high-fidelity hysteresis loop and a magnetic conductivity change rule are obtained, and the nonlinear characteristic and hysteresis response of the magnetic core can be accurately captured, so that the predictive capability of equipment performance and the sensing capability of an operation state are improved.

The invention relates to the technical field of battery simulation, in particular to a solar battery simulation method and system. The method comprises the following steps: obtaining solar cell structure data; dividing the surface of the battery into a plurality of subunits based on the solar battery structure data, initializing electrical parameters of each subunit, and generating a battery partition parameter set; acquiring global incident light intensity information, and calculating ray tracing of intersection points of rays of each battery surface unit and a plane through the battery partition parameter set to obtain local light intensity distribution data; performing photoelectric conversion parameter mapping on the local light intensity data to obtain partitioned photo-generated current data; and constructing an equivalent circuit model of the solar cell by using the partitioned photo-generated current data. According to the method, the problem of insufficient precision caused by model simplification and uneven illumination in existing solar cell simulation is solved by refining structure partitioning, precise ray tracing, multi-subunit equivalent circuit combination and system performance evaluation.

The invention provides a project state summarizing method and device, and belongs to the technical field of DFT (Discrete Fourier Transform), and the project state summarizing method comprises the following steps: distributing a plurality of test tasks to a plurality of predefined categories according to the corresponding test steps according to the mapping relation between the test steps and the predefined categories; and based on the task state of the test task included in each predefined category, determining the category state of the corresponding predefined category. Through a predefined mapping relation, original and scattered test tasks and states thereof are aggregated into classified and macroscopic class states.

The invention discloses a distributed dynamic time sequence monitoring circuit and a self-adaptive adjusting system, which comprise a plurality of monitoring units deployed in different IR voltage drop hot spot areas of a chip, each monitoring unit is configured as a delay chain, and the delay of the delay chain is determined by the local power supply voltage and temperature of the area where the monitoring unit is located. The delay variation is equal to the delay variation of the longest key path determined by simulation; the input end of the dynamic aggregation unit is connected with the monitoring unit, and the dynamic aggregation unit is used for comparing delays of all the input signals and outputting the input signal with the longest delay; a central monitor including a configurable delay pad circuit for providing a reference delay; the input end of the delay gasket circuit is connected with the output end of the dynamic aggregation unit, and the delay of the input signal with the longest delay and the reference delay are summed to obtain the total delay of the virtual key path for the real-time longest key path delay of the mirror image chip. According to the invention, non-intrusive monitoring can be realized, and all possible IR voltage drop hot spot areas can be fully covered.

The invention provides a design rule checking method and device based on a multi-modal large model, a terminal, a medium and a product. The method comprises the following steps: acquiring a to-be-analyzed multi-modal DRC rule file; generating a JSON code corresponding to the DRC rule file by utilizing a visual language model according to a preset JSON code format; and converting the JSON code into a corresponding DRC code by using a pre-constructed knowledge base, and carrying out conflict detection on the JSON code through a large language model to obtain a corresponding conflict detection result. According to the method and the device, the multi-modal DRC rule file can be processed, the rule file analysis efficiency is relatively high, and the conflict detection efficiency and the accuracy are relatively high.

The present invention relates to a circuit including a plurality of routers arranged as a 2D flattened array, each router in the 2D flattened array comprises: a routing network configured to route data between the router and other routers in the 2D flattened array, an input interface configured to receive data from a memory, and an output interface configured to output data to the memory. The 2D flattened array implements a logical butterfly network, and is configurable as a gather circuit, operable to gather high-magnitude tensor data from a dense tensor into a condensed tensor, or a scatter circuit, operable to scatter tensor data from the condensed tensor into a sparse uncondensed tensor based on a given mask.

The invention relates to the technical field of circuit performance testing, in particular to an integrated circuit aging effect prediction and circuit life reliability evaluation method. The specific implementation process comprises the following steps: acquiring a physical design netlist and a basic process library, analyzing a test load into transient upset density, and generating a time-varying excitation flow in combination with layout geometric information; dividing an aging sensitive domain by using a double-track aging difference mechanism, and performing integration processing on the time-varying excitation flow to quantify a circuit aging parameter; performing full-chip time sequence simulation on the circuit aging parameter, and predicting a performance erosion index; and calculating a dynamic redundancy retraction vector, adjusting the reduction amplitude of the guard band, and converging the evaluation in a target design interval. According to the method, the time-varying excitation flow and the sensitivity partition topology are utilized, the multi-physical field coupling effect under the dynamic load is effectively captured, the problem of prediction distortion caused by static hypothesis is solved, and the balance of the chip area, the power consumption and the reliability service life is achieved through the dynamic redundancy retraction vector optimization design protection band.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

The invention belongs to insulation of superconducting power equipment, and particularly relates to a breakdown voltage prediction method for a liquid nitrogen, insulation barrier and bubble composite system. Comprising the following steps: acquiring electric field distribution characteristic parameters of the resistance type superconducting current limiter through simulation, and designing an equivalent electrode structure capable of reproducing electric field characteristics in a liquid nitrogen environment; establishing a first breakdown voltage prediction model taking the insulation barrier position parameters and the electrode spacing as variables; calculating the surface heat flux of the superconducting strip in the quench fault state; and introducing a bubble influence factor for correction to obtain a second breakdown voltage prediction model. A complex actual insulation system prediction problem is converted into an equivalent model problem which can be verified in a laboratory. And an accurate basis is provided for the insulation design of the resistance-type superconducting current limiter.

The invention belongs to the field of electronic design automation, and discloses a multi-agent radio frequency circuit netlist generation method and system based on a large language model, and the method comprises the steps: preparing a data set, and constructing a knowledge base; the method comprises the following steps: receiving and analyzing a natural language demand of a user, combining a cue word project and an RAG mechanism, carrying out chained reasoning, introducing a radio frequency design rule, and converting the information into structured parameter information; combining RAG knowledge base retrieval and new topology generation, and fusing PDK process constraints to obtain candidate topologies and a simulation netlist; a simulation tool is called to execute parameter analysis, iterative optimization is conducted on parameters in combination with a closed-loop feedback mechanism, and a final netlist meeting user requirements is obtained. Automatic decomposition, parallel cooperation and high-speed iteration of design tasks are achieved through multi-agent cooperation and in combination with the radio frequency knowledge graph and the RAG; introducing physical constraints to enable the generated topological structure and parameters to meet the physical constraints; and a closed-loop simulation feedback mechanism is fused, so that the dependence on manpower is reduced.

A system includes a fleet resources data store that maintains a fleet resource inventory indicating fleet resources that can be assigned to perform tasks. For each fleet resource, the inventory indicates features of each fleet resource and a respective status. A set of task definitions is accessible to an intelligence layer to facilitate improving task definition based on feedback from task-specific outcomes. The system receives a job request for a robotic fleet to perform a job and determines a job definition data structure indicating a set of tasks to be performed for the job. The system applies an outcome of performing a task by a resource assigned to perform the task to a machine learning system of the intelligence layer that facilitates improving, based on the outcome, the set of task definitions. The system updates the set of task definitions based on a result of applying the machine learning system.

The invention provides an integrated circuit power supply network wiring optimization method, a computer device and a storage medium. The method comprises the steps of performing initial wiring based on initial parameters and constraint conditions; evaluating the connectivity state of the power supply network after initial wiring, if the number of unconnected pins of the power supply network does not meet the set requirement, performing connectivity optimization calculation on the power supply network, and adjusting wiring parameters of the power supply network to enable the number of the unconnected pins to meet the set requirement; the power supply voltage drop state of the power supply network is evaluated, if the power supply voltage drop value under the worst condition is larger than a preset power supply voltage drop threshold value, power supply voltage drop optimization calculation is carried out, and the power supply voltage drop value under the worst condition is reduced to be below the power supply voltage drop threshold value by adjusting wiring parameters of the power supply network; and carrying out wiring on the power supply network based on the finally determined wiring parameters obtained by power supply voltage drop optimization calculation. The computer device and the storage medium can realize the method. According to the invention, the calculation efficiency of wiring optimization can be improved.

The invention relates to the technical field of chip test vector intelligent generation scheme design, in particular to a failure analysis-oriented chip test vector intelligent generation method and system. The method comprises the following steps: acquiring a chip design netlist, a fault model and a known failure mode; analyzing potential design or manufacturing defects based on the information; and according to an analysis result, a targeted test vector capable of effectively exciting and isolating potential defects is automatically generated. The system comprises a corresponding input module, an analysis module and a generation module. According to the method, the design information, the fault model and the historical failure mode are intelligently fused, automatic and precise generation of the test vector is achieved, and the defects that a traditional method is insufficient in test coverage rate, low in failure positioning efficiency and limited in automation degree are overcome. According to the method, the test completeness and the failure analysis efficiency can be remarkably improved, the dependence on artificial experience is reduced, and an efficient technical means is provided for guaranteeing the reliability of the chip.

The invention belongs to the technical field of electromechanical transient modeling, and particularly discloses a PSASP-based electromechanical transient modeling method for a network-building converter, and the method comprises the steps: setting the voltage of a grid-connected point and an equivalent impedance parameter of a converter transformer; the method comprises the following steps: in a PSASP custom modeling platform, establishing a network construction type converter control model, and obtaining a reference voltage signal through the control model; performing voltage-current conversion to obtain a real part and an imaginary part of current injected into the bus; setting a virtual impedance link in a control model of the network-forming converter, calculating virtual voltage drop by combining a current real part and an imaginary part with a virtual impedance parameter, correcting a reference voltage signal, and performing voltage-current conversion to obtain the corrected current real part and imaginary part; and injecting the corrected real part and imaginary part of the current into a PSASP bus in a current source form, and establishing an electromechanical transient model of the grid-forming converter.

The invention discloses a conversion circuit for measuring time sequence arc delay of a standard unit, which belongs to the field of integrated circuits and comprises a time sequence arc delay clock generation circuit of the standard unit, a clock frequency dividing circuit, a control module and an IO output module. The standard unit time sequence arc delay clock generation circuit connects a plurality of same standard units in series to form a test chain, delays the time sequence arc of a single standard unit, and outputs the time sequence arc in a stable-frequency clock form; the clock frequency division circuit performs frequency division on the stable clock generated by the standard unit time sequence arc delay clock generation circuit through an algorithm, so that the stable clock can be detected by a machine table; the control module selects a plurality of standard cell types from the control signal, selects a time sequence arc, selects a cascade stage number, and controls the output of the clock frequency dividing circuit; and the IO output module outputs the frequency-divided clock generated on the chip through an IO port so as to be detected by a machine. According to the invention, extra power consumption, area and design complexity caused by an extra on-chip high-frequency clock can be effectively avoided.

The invention relates to the technical field of power systems, and particularly provides a network construction type energy storage wide and low frequency disturbance suppression method suitable for a weak power grid environment. The method comprises the following steps: constructing an equivalent impedance model, and analyzing RLC resonance impedance matching conditions; constructing a quantitative model of impedance dynamic correlation; designing a multi-parameter adaptive virtual impedance module; constructing a cooperative control architecture of the adaptive virtual impedance and the network construction type energy storage converter; through verification of a continuous voltage drop simulation scene, adaptive adjustment parameters are optimized by adopting indexes of oscillation amplitude attenuation rate and stabilization time so as to ensure a wide and low frequency disturbance suppression effect under a weak power grid, and according to the method, broadband oscillation suppression under the continuous voltage drop scene is realized through adaptive virtual impedance, and dynamic accurate compensation is realized.

An example chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh.

The invention relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) surge failure real-time discrimination method and system, and the method comprises the steps: 1, collecting SiC MOSFET surge waveform data, and carrying out the multi-scale physical feature extraction, and obtaining a physical frequency band energy feature; 2, performing feature alignment on the physical frequency band energy features to form a standardized feature vector; and 3, constructing a surge failure prediction model, performing temperature compensation on an output result of the surge failure prediction model, and judging a failure state. Current and voltage waveforms in a surge event are captured through a high-speed data acquisition system, key physical frequency band energy features are extracted by adopting an adaptive wavelet packet decomposition technology, a pulse width normalization coding model is constructed to realize feature alignment, and a physical guide degradation path auto-encoder model is designed to perform failure prediction. The method innovatively solves the problem of failure discrimination of surges with different pulse widths, and has the characteristics of high precision and strong real-time performance.