6983results about "Computer aided design" patented technology

The invention discloses a verification method and system of a chip simulation model, a medium and a program product, and relates to the technical field of chip verification, and the method comprises the steps: obtaining a simulation model and a performance parameter index of a to-be-verified chip; generating model training data based on the historical performance indexes, the corresponding historical use case set and the historical verification result, and performing model training based on the model training data to obtain a use case generation model; inputting the performance parameter indexes to a case generation model to obtain a test case set and a test verification expectation; executing a plurality of test cases in the test case set based on the simulation model, and recording an actual response result of the simulation model; based on the actual response result and the test verification expectation, generating a test log, and determining an abnormal mark in the test log; and marking the fault features corresponding to the exception, taking the test cases as newly added training data, and optimizing the case generation model based on the newly added training data. According to the invention, the chip verification efficiency can be improved.

Disclosed in the present invention are a method and system for small-signal stability analysis of a power plant containing grid-forming converters. The method comprises: establishing a grid-following converter impedance model; establishing a grid-forming converter impedance model; constructing a new energy power plant grid-connected system model containing grid-following converters and grid-forming converters; establishing a simplified equivalent circuit of a power plant grid-connected system; establishing a small-signal stability Nyquist criterion for a grid-connected new energy power plant containing grid-forming converters; and using a Nyquist plot to analyze the small-signal stability characteristics of the power plant grid-connected system. According to the present invention, the problem in the prior art of lacking quantitative and effective analysis of small-signal stability in new energy power plants containing grid-following converters and grid-forming converters is solved, and establishing a small-signal stability criterion for the power plants on the basis of established small-signal models enables quantitative analysis of the small-signal stability characteristics of a new energy power plant containing grid-forming converters under low grid strength conditions, and compared with conventional impedance modeling methods for new energy power plants, the impact of grid-forming converter integration on the small-signal stability of the new energy power plants is better reflected.

The invention relates to the technical field of chip design, in particular to a system-on-chip design method and system and a medium. The method comprises the following steps that a chip design target and basic parameters are collected, a constraint condition set is generated through demand constraint analysis, the basic parameters of a system are subjected to parallel recombination, functional prototype data are generated, the functional prototype data are used for chip behavior design, functional unit groups are generated, a network architecture is reconstructed to form a functional module network, and the functional module network is used for chip behavior design. And carrying out clock domain mapping and competition compensation processing based on the network to obtain a function scheduling sequence, carrying out resource matrix remapping on the basic parameters according to the function scheduling sequence, generating hardware abstract data, carrying out chip layout simulation, and finally generating a simulation chip blueprint. According to the system-on-chip design method, the more efficient system-on-chip design method is achieved.

The invention discloses a PCB three-proofing coating quality detection method and system. The method comprises the steps that a visible light reflection image of the surface of a PCB and scattering spectrum data of a near-infrared band are acquired; performing spatial filtering processing on the visible light reflection image to extract interface area pixels, calculating coating layer thickness gradient distribution based on Mie scattering characteristics in scattering spectrum data, and fusing to generate an edge gradient distribution map; and according to the gradient amplitude change rate in the edge gradient distribution map, segmenting the effective coverage area of the coating layer by adopting a self-adaptive dynamic threshold algorithm, and extracting curvature extreme point density and boundary fractal dimension parameters at the segmentation boundary. According to the invention, three technical barriers of difficult microdefect capture, unmeasurable interface performance and delayed failure risk in traditional detection are solved, and two-dimensional accurate diagnosis of the structural compactness and interface reliability of the coating layer is realized.

An information technology system for a distributed manufacturing network includes an additive manufacturing management platform configured to manage process and production workflows for a set of distributed manufacturing network entities through design, modeling, printing, and supply chain stages. The information technology system includes an artificial intelligence system configured to learn on a training set of outcomes, parameters, and data collected from the set of distributed manufacturing network entities of the distributed manufacturing network to optimize digital production processes and workflows. The information technology system includes a distributed ledger system integrated with a digital thread configured to provide unified views of workflow and transaction information to entities in the distributed manufacturing network.

The invention relates to the technical field of battery model construction, in particular to a construction method and system of a lithium ion battery equivalent circuit model and a medium. The method comprises the following steps: collecting initial battery electrochemical parameters, obtaining ion migration characteristic data through charge density gradient decoupling, further reconstructing a polarization potential field to generate a lithium ion battery charge-discharge curve, performing potential migration analysis on the curve, mapping the curve into time domain charge mapping data, and calculating the time domain charge mapping data according to the time domain charge mapping data. Voltage distribution data are captured through transient voltage, circuit topology is reconstructed, circuit temperature distribution data are obtained, electric field-temperature field cross locking is carried out to determine a temperature influence coefficient, an initial equivalent circuit model is corrected based on the temperature influence coefficient, charging and discharging simulation is carried out on the corrected model, and aging factors are embedded. And finally generating an equivalent circuit model of the lithium ion battery. The method for constructing the equivalent circuit model of the lithium ion battery is more reliable and more intelligent.

The present invention relates to the technical field of calculation, estimation or counting. Disclosed is a critical path sorting method based on a graph neural network. The method comprises: first, obtaining a potential critical path set in a netlist by means of a static timing analysis tool; next, converting a netlist file comprising circuit function information into a graph data structure, and obtaining an initial training set on the basis of a relevant process configuration file; then, inputting the initial training set into a graph neural network for training to obtain a critical unit prediction model, wherein the critical unit prediction model consists of three parts, namely, a deep structure auto-encoder, a nonlinear attribute auto-encoder and a joint error reconstruction module; and finally, quantifying the criticality of each path in the potential critical path set on the basis of critical unit information and a path criticality calculation algorithm in the netlist, and obtaining a critical path sequence under process awareness. According to the method, critical paths in circuits influenced by process deviations can be effectively sorted, providing valuable reference for circuit optimization.

A robot fleet management platform includes a job configuration system that determines tasks to be performed by robots of a robot fleet based on a job request and a first fleet objective. A proxy service applies fleet configuration services to the tasks to produce a data structure. An intelligence layer activates intelligence services to produce a robot task and associated contextual information that facilitates robot selection and task ordering. A job workflow system generates a workflow defining a performance order of the tasks. A workflow simulation system simulates performance of the job request based on the workflow to recursively redefine the tasks, the data structure, or the workflow until the simulation result satisfies a second fleet objective. In response to the simulation result satisfying the set of fleet objectives, a plan generator generates a job execution plan based on the set of robot tasks, the data structure, and the workflow.

The invention provides a temperature compensation method and device for a silicon carbide MOS drive control chip, and the method comprises the steps: obtaining a junction temperature-electrical parameter set of a silicon carbide MOS, and carrying out the thermoelectric coupling simulation modeling processing of a junction temperature-electrical parameter mapping data set, and obtaining three-dimensional temperature-efficiency characteristic data; performing real-time parameter analysis and dynamic execution on the three-dimensional temperature-efficiency characteristic data to obtain an optimized switching characteristic waveform; extracting the optimized switching characteristic waveform frequency domain characteristics, and generating a dynamic frequency modulation parameter; and performing dead time iterative optimization on the dynamic frequency modulation parameters to obtain a control parameter combination of the silicon carbide MOS.

A dynamic vision system includes a variable focus liquid lens optical assembly. The dynamic vision system includes a variable lighting assembly. The dynamic vision system includes a control system configured to adjust one or more optical parameters and data collected from the variable focus liquid lens optical assembly in real time. The dynamic vision system includes a control system configured to adjust the variable lighting assembly. The dynamic vision system includes a processing system that dynamically learns on a training set of outcomes, parameters, and data collected from the variable focus liquid lens optical assembly to train a set of machine learning models to control the variable focus liquid lens optical assembly to optimize collection of data for processing by the set of machine learning models.

The invention relates to the technical field of chip verification, and discloses a chip verification method, test equipment and a chip verification system.The method comprises the steps that a template file is built, a verification environment and a test case are generated based on the template file, a configuration file is obtained, and parameters in the verification environment and the test case are updated through parameters in the configuration file; according to the method, the verification environment and the test case are updated, the updated verification environment and the updated test case are obtained, regression testing is carried out on the chip on the basis of the updated verification environment and the updated test case, the test result is obtained, the verification environment can be rapidly generated on the basis of the template file, parameters can be rapidly replaced, and the chip testing efficiency is improved.

The invention provides a method and system for preparing a high-temperature anti-aging test board for chip testing, and relates to the technical field of data energy storage and resource scheduling, and the method comprises the steps: designing a schematic circuit diagram and a PCB wiring scheme; a test plate is made of a high-temperature resistant material; bare board verification, electrical performance verification, program setting verification, high temperature verification and junction temperature measurement verification are carried out; using data is recorded, ultrasonic cleaning and drying are carried out, and a performance evaluation model is established through a hardware management system to judge whether maintenance or replacement is needed. According to the invention, the accuracy of chip testing in a high-temperature environment is improved, and the service life of the test board is prolonged.

The invention discloses a current transformer real-time state diagnosis system based on Internet of Things, which relates to the technical field of electrical equipment state diagnosis and comprises a reference construction module, a disturbance excitation module, a modeling identification module, a driving unwrapping module, a self-adaptive setting module and a closed-loop control module, in the operation process of a secondary winding loop of the current transformer, a nanosecond time synchronization reference is established, a phase reference baseline is locked, current vector trajectories are continuously collected based on the time synchronization reference and the phase reference baseline, and a discrete phase residual image is constructed. According to the method, through high-precision time synchronization, phase disturbance excitation, sparse modeling identification, driving unwrapping and self-adaptive setting control, hysteresis oscillation of the secondary circuit of the current transformer is accurately identified and suppressed, the fault diagnosis accuracy and the system stability are remarkably improved, and the limitation of a traditional method in the aspects of identification sensitivity and response capability is broken through.

The invention discloses an E-mode device nonlinear current model parameter extraction method considering a gate current effect, and relates to the technical field of enhanced device modeling. Comprising the following steps: establishing a nonlinear current model of an E-mode device; extracting parasitic resistance of the transistor; removing the influence of parasitic resistance of the transistor, and calculating gate-source and gate-drain node voltages of an intrinsic region in the nonlinear current model to obtain an intrinsic gate-source voltage and an intrinsic drain-source voltage; extracting intrinsic gate current model parameters; obtaining the drain-source current component of the intrinsic part from the influence of the fused gate current component in the actually measured drain-source current of the transistor; extracting intrinsic nonlinear drain-source current model parameters; and substituting the intrinsic nonlinear drain-source current model parameter value into an intrinsic nonlinear drain-source current model equation for verification. According to the method, gate current component calculation is introduced into a traditional nonlinear current model parameter extraction method, and accurate extraction of intrinsic nonlinear current source parameters is achieved.

The present invention discloses an integrated circuit chip with a data line, a key and a mechanical keyboard, wherein the integrated circuit chip integrates a magnetic induction integrated circuit and an RGB magic color driving circuit; the integrated circuit chip includes a power pin, a ground pin, a data information input pin and a data information output pin, and the connection between the data information input pin and the data information output pin of a plurality of integrated circuit chips forms a data line and is connected to the MCU; an integrated circuit chip cooperates with a key with a magnetic element to obtain a key information, and according to different communication protocols, the RGB magic color driving circuit and the magnetic induction integrated circuit share the data line, and transmit the RGB color grayscale information and the key information in a time-sharing manner. The present invention cascades all the key information through the data line, saves a lot of wiring space, reduces the design difficulty of the PCB, reduces the number of electronic components by multiples, and provides a variety of different code sending methods and working methods, making its application simpler and more efficient.

The invention discloses a perceptually optimized wiring time sequence prediction method for a digital integrated circuit, electronic equipment and a storage medium, and the method comprises the steps: constructing a heterogeneous graph according to a circuit netlist, fusing the heterogeneous graph with feature vectors corresponding to all units and interconnection lines, inputting the fused heterogeneous graph into a trained heterogeneous graph neural network, and obtaining graph network embedding; inputting the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding; splicing graph network embedding and convolutional network embedding to obtain multi-modal local embedding; constructing a feature sequence of the path according to a connection relationship between a logic unit and an interconnection line in the path by multi-modal local embedding, and inputting the feature sequence of the path into the trained Transform network to obtain a path delay residual prediction value after wiring; and adding the path delay value after layout and the path delay residual prediction value after wiring, and finally obtaining a path delay prediction value after wiring. According to the method, the path delay after wiring can be accurately and efficiently predicted before wiring.

The invention discloses a process deviation-oriented analog circuit parameter optimization method, which comprises the following steps of: S1, carrying out multi-objective optimization on a given analog circuit under a nominal process condition, identifying and eliminating a design region with poor performance according to an optimization result, and carrying out clustering analysis to obtain an optimal design region; dividing the remaining high-quality areas into a plurality of initial trust areas; s2, modeling the finite Monte Carlo simulation data in the initial trust area by using a heterovariance Gaussian process model, capturing an average level and a change trend of circuit performance, and predicting behaviors of the circuit under process change; and S3, the required yield is kept while the performance is optimized, probability assurance is provided for the performance value by adopting the risk value, and a design point optimization set and a corresponding Pareto optimal solution set are finally obtained through multiple iterations in the optimization stage of considering the process change. According to the method, the high-quality Pareto optimal solution set meeting the yield constraint is found under the process change of unknown distribution, and the size of an analog circuit is optimized.

The invention belongs to the technical field of electronic design automation, and provides a dynamic power consumption optimization method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design, and determining a starting point of a specific type in the circuit design; performing backward traversal on the circuit design along a signal propagation direction from the starting point to determine circuit branch structure information and a specific type of termination point in the circuit design; starting from the termination point, establishing an ODC expression, performing forward traversal on the circuit design in an inverse signal propagation direction, and in the forward traversal process, based on the circuit branch structure information, propagating the ODC expression in the circuit design until ODC distribution of the circuit design is determined; based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. According to the method, the ODC expression can be quickly and efficiently propagated in the whole circuit design, so that a designer can conveniently optimize the dynamic power consumption through ODC distribution.

The invention discloses a chip design and manufacturing optimization system and method based on edge reinforcement learning, and relates to the field of data analysis, and the system comprises a scene recognition module, a strategy selection module, a decision correction module and a cloud updating module. A fuzzy recognition and alarm mechanism is introduced to enhance the adaptability; inter-process linkage optimization is realized by means of a double-index strategy library and an influence gradient transmission mechanism, and the process collaboration is improved; through dynamic uploading of the state tetrad and cloud oscillation identification, the system can automatically enter cold-quiet period locking under strategy abnormity and energy consumption fluctuation, and abnormal diffusion is effectively inhibited. Meanwhile, a lightweight edge deployment and reinforcement learning mechanism enables the system to have high response, low communication and self-learning capabilities, and the system is suitable for a large-scale complex chip manufacturing environment.

The invention discloses a printed circuit board production parameter intelligent dynamic optimization method and system, and relates to the technical field of circuit board processing optimization, and the method comprises the steps: monitoring the real-time temperature data of a lamination part in real time; processing the real-time temperature data, and identifying a temperature unstable region in the production process; screening hot pressing roller process sections with stable temperature distribution to execute lamination operation; evaluating the risk level of the current lamination process; screening a low-risk temperature distribution mode based on the risk level to carry out lamination production, obtaining a quality deviation coefficient, and judging whether a preset process standard is met or not based on the quality deviation coefficient; and for products which do not meet the preset process standard, temperature control parameters in the production process of the products are traced, and the temperature set value of the hot pressing roller is dynamically adjusted. The method has the advantages that the real-time quantitative evaluation of the wear state of the hot pressing roller is realized, and the line width precision control capability and the interlayer alignment consistency are remarkably improved.

The invention discloses a pulse stable output control method and system for an ns-level high repetition frequency fast pulse power supply, and relates to the technical field of automatic control, the system is composed of a plurality of functional modules, and the system comprises a self-adaptive absorption module, a control module and an output control module, and the self-adaptive absorption module obtains power supply parameters through real-time sampling, and the power supply parameters comprise load impedance and switch tube parasitic parameters; dynamically optimizing R and C parameters of the RCD absorption circuit and the active clamping circuit based on power supply parameters; the feed-forward prediction module is used for extracting derivative state information according to the power supply parameters, acquiring load current feed-forward and resonant circuit states based on the derivative state information, modeling based on the load current feed-forward and resonant circuit states, and predicting the drain-source voltage valley bottom moment of the switch tube; and the multi-section variable impedance transmission module adopts a three-section variable impedance structure, performs broadband impedance matching based on R and C parameters of the optimized RCD absorption circuit and the active clamping circuit, inhibits pulse leading edge reflection distortion, and outputs undistorted pulse signals.

The invention relates to the technical field of chip testing, in particular to a testing method and system for a chip simulation model. The method comprises the following steps: collecting a target chip simulation model and performing time sequence compensation to generate jitter compensation data, then performing eye pattern reconstruction to obtain waveform eye pattern data, performing amplitude normalization and time sequence phase correction on the waveform data to obtain purified alignment data, and performing phase correction on the purified alignment data. The method comprises the following steps: generating main modal data through orthogonal mapping processing and modal projection analysis, constructing nuclear space data, carrying out manifold cognitive aggregation to generate test coverage features, carrying out boundary analysis and density distribution analysis on the features to obtain clustering boundary data, finally adjusting and optimizing boundary precision, executing an adaptive test sequence, and generating a test case result. According to the invention, a more efficient chip simulation model test method is realized.

The invention provides a circuit logic synthesis method for FPGA mapping based on reinforcement learning, and aims at solving the problem that in a traditional netlist optimization method, a circuit is not seen in model optimization, and the capacity is insufficient. The method comprises the following steps: firstly, constructing a logic comprehensive data set, and then preprocessing the data set to obtain statistical characteristics and a graph structure of a circuit; then, a logic comprehensive model based on reinforcement learning and aiming at FPGA mapping is constructed, pre-training is conducted through the preprocessed data set, and finally logic optimization is conducted on a circuit through the pre-trained logic comprehensive model based on reinforcement learning and aiming at FPGA mapping. According to the circuit feature extraction module, a GNN module is adopted to analyze a logic circuit and a netlist structure to obtain graph embedding, statistical features of the logic circuit and the netlist are analyzed through an FCN module, the features of the two parts are spliced to obtain an accurate enhanced representation state of the circuit, and the understanding capacity of a reinforcement learning model on different circuits is improved.

The invention discloses a design optimization method of a radio frequency power amplifier, and relates to the technical field of design optimization. The method comprises the following steps: collecting the working frequency and the circuit topological structure of the radio frequency power amplifier, establishing a digital twin simulation model, and generating an initial impedance value; simulation performance indexes of the amplifier under the input signal are obtained through simulation; matching network parameters are adjusted according to a dynamic reconstruction matching network algorithm, and a dynamic optimization impedance set is generated; controlling the tunable element to reconstruct the actual impedance value of the radio frequency power amplifier, and collecting the actual performance index of the output signal; comparing an error between the simulation performance index and the actual performance index, and if the error exceeds a preset error threshold, iteratively updating a parasitic parameter of the digital twinborn model; and if the error is within the threshold value, locking the actual impedance value as the optimal configuration, and amplifying and outputting the input signal. The working efficiency of the radio frequency power amplifier is improved.

The embodiment of the invention discloses a chip verification environment generation method and system, electronic equipment and a storage medium, relates to the technical field of integrated circuit verification, can adapt to verification environments with different configurations, and improves verification efficiency. The method comprises the following steps: constructing or calling a verification environment template; analyzing the initial configuration information and the routing topology information, and generating a target configuration file according to an interface protocol and an interconnection rule of a register transfer level and a model; the routing topology information indicates an interconnection link topology structure between the devices, and the target configuration file indicates a component type corresponding to each device required by simulation forming of each interconnection link and a matched verification component type; loading and instantiating the register transfer level component and the model component based on the verification environment template according to the component type; and according to the verification component type, interconnection is carried out between the register transfer level component and the model component through the verification component, and a chip executable verification environment is generated. The method and the device are suitable for a scene for constructing a chip verification environment.

Disclosed in the present application are an integrated circuit routing method and system, and a device and a medium. The method comprises: acquiring an integrated circuit layout model; performing routing area generation processing on the integrated circuit layout model on the basis of a particle swarm optimization algorithm, so as to obtain a routing area; performing routing processing on the routing area on the basis of an improved A* search algorithm, so as to obtain a routing path; on the basis of the routing path, removing a redundant segment, so as to obtain a post-processed path; and performing dictionary conversion processing on the post-processed path, so as to obtain a routing layout. In the embodiments of the present application, a discrete particle swarm optimization algorithm can be used to reduce a routing search space, and a detailed routing area is determined by means of an improved A* search algorithm, thereby further enhancing routing speed, and improving the routing efficiency of an integrated circuit. The embodiments of the present application can be widely applied to the field of integrated circuits.

The invention discloses an integrated circuit heat distribution optimization method driven by fusion situation awareness, and particularly relates to the technical field of integrated circuit heat distribution optimization, which comprises the following steps: acquiring a behavior fragment set in an integrated circuit, performing regulation and control trigger sequence adjustment and regulation and control chain atlas construction operation, constructing a regulation and control chain atlas, and establishing a regulation and control chain atlas; performing identification and extraction operation of path traversal on the regulation and control chain atlas, and performing mapping to generate a disturbance input variable set; extracting data in the disturbance input variable set, performing normalization processing and time sequence reconfiguration operation, and constructing a disturbance response track; a regulation and control path structure caused by a temperature control behavior in an integrated circuit is extracted, and a stability identification model is constructed based on path disturbance propagation characteristics and behavior feedback offset, so that dynamic judgment and regulation and control structure optimization of a potential thermal feedback chain in a multi-core environment are realized, and task scheduling imbalance caused by path evolution accumulation is avoided.

The invention discloses a chip verification method and device, equipment, a storage medium and a program product. The method comprises the steps that a first executable file of a C model is obtained, the first executable file comprises an original code and a target code which are designed based on a verified function in a chip, and the verified function comprises a plurality of algorithm steps; running the first executable file based on the input signal to obtain running data of each algorithm step; extracting simulation data of each algorithm step from the simulation waveform file with the verified function; and respectively comparing the operation data and the simulation data of each algorithm step to determine an abnormal algorithm step in which the operation data and the simulation data are inconsistent. Therefore, by automatically comparing the operation data and the simulation data of each algorithm step, the abnormal algorithm step with the problem can be quickly determined, and the manual inspection and analysis time is shortened.

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The embodiment of the invention provides a defect detection method, electronic equipment, a storage medium and a program product, and the method comprises the steps: obtaining the actual morphology data of one or more local regions of a target wafer and a global layout of the target wafer, and carrying out the global layout of the target wafer for each local region based on the mapping relation between the wafer morphology and technological parameters, determining a prediction process parameter corresponding to the actual morphology data of the local region, and predicting the wafer morphology of the global layout under the prediction process parameter of the local region for each local region based on a mapping relationship between the wafer morphology and the process parameter to obtain wafer morphology prediction data, and determining the defective pixel areas of the target wafer based on the predicted wafer morphology prediction data corresponding to each local area, determining a to-be-detected area from all the defective pixel areas, and scanning the to-be-detected area of the target wafer by using defect scanning equipment to obtain a defect detection result, so as to effectively improve the efficiency and precision of defect detection.