59 results about "Antenna effect" patented technology

The invention belongs to the technical field of fluorescent sensing materials, and particularly relates to a ratio metering type fluorescent probe based on a metal organic framework (MOF) material as well as a preparation method and application of the ratio metering type fluorescent probe. The probe material emits blue light, after 2, 6-dipicolinic acid (DPA) is added, the DPA enhances fluorescence emission of Tb < 3 + > and inhibits emission of coumarin through an antenna effect, the fluorescence intensity ratio (I548 / I429) between two emission bands is changed, a good linear response relation is shown in the concentration range of 0-90.0 mu M, the detection limit is 0.13 mu M, and high-sensitivity ratio type detection of the DPA is achieved. After detection is finished, phosphate radical (PO4 < 3->) ions are added, so that the antenna effect can be effectively quenched, the initial fluorescence state is recovered, and meanwhile, the method can be used for detecting the concentration of phosphate radicals. After DPA is added again, reactivation can be realized, so that recycling can be realized, and the limitation of disposable use of a traditional fluorescent probe is broken through.

The invention discloses a light capture system based on a polybenzyl ether dendrimer as well as a preparation method and application of the light capture system. According to the light capture system, a core mono-cyano ethylene modified polybenzyl ether dendrimer is used as a light acquisition antenna and an energy donor, and a fluorescent dye is used as an energy receptor; the core mono-cyano ethylene modified polybenzyl ether dendrimer and the fluorescent dye are co-assembled in a solution to form a light capture system. The light capture system provided by the invention has excellent aggregation-induced emission performance, obviously enhanced fluorescence and narrower emission band, and can still maintain better energy transfer and ultrahigh antenna effect under a high donor-acceptor ratio; in addition, the preparation process is green and environment-friendly, and the light capture system is stable in structure and can be stored for a long time.

The utility model provides a floating terminal and a connector. The floating terminal comprises a welding part, a floating part and an elastic part, the first end of the floating part is connected to the welding part, and the floating part is located between the welding part and the elastic part; the floating terminal further comprises a first fixing part, and the second end of the floating part is connected to the elastic part through the first fixing part. An opening groove is formed in the bottom of the first fixing part. According to the floating terminal, under the condition of a limited space, the length of the elastic arm of the floating terminal is prolonged structurally, so that the floating terminal has relatively large elastic deformation quantity and relatively good elastic performance, and even if the floating terminal has relatively large compression quantity, the floating terminal is not tired; the bottom of the first fixing part is provided with the open slot, so that the antenna effect is effectively reduced, the impedance is adjusted, and the high-frequency performance of the connector is improved.

The invention discloses an unsupervised deep learning rainfall dry and wet period classification and monitoring method, which adopts dry period CML signal training, learns normal signal features through an auto-encoder, a variational auto-encoder and a fusion model thereof, and realizes rainfall abnormal attenuation detection by taking reconstruction errors and potential distribution deviation as discrimination indexes. According to the method, extra equipment and manual marking are not needed, rainfall events can be automatically identified, cross-link and cross-region generalization ability is achieved, robustness to non-rainfall interference such as a wet antenna effect is high, large-scale real-time monitoring can be achieved in a smart city and a 6G integrated sensing scene, and the method is widely applied to the fields of weather, hydrology and disaster early warning.

The invention relates to an optimization method and device of an integrated circuit, electronic equipment, a computer readable storage medium and a computer program product, and belongs to the field of computers. The optimization method of the integrated circuit comprises the following steps: acquiring an antenna effect check report of the integrated circuit; determining whether the integrated circuit has antenna effect violation according to the antenna effect check report; under the condition that the integrated circuit has the antenna effect violation, determining diode information required for repairing the antenna effect violation based on the antenna effect check report and a preset diode standard unit; wherein the diode information is used for optimizing and repairing the antenna effect violation of the integrated circuit. According to the method and the device, the diode information required for repairing the violation of the antenna effect can be quickly and accurately determined, the reduction of design iteration is facilitated, and repeated tests are avoided, so that the design period of chip design can be shortened.

This invention belongs to the field of immunoassay and biosensing technology, and discloses a method for preparing a ratiometric ECL biosensor based on Eu / Tb-Lu MOGs. Using Eu / Tb-Lu MOGs as the luminescent material and H3-tctpy and luminol as ligands, a single-luminescent material with dual ECL emission is synthesized. Lanthanide ions provide the cathode ECL emission, enhanced by the antenna effect and Tb→Eu energy transfer; the anode emits light from luminol using dissolved oxygen in water, requiring only the addition of K2S2O8 as a single co-reactant, resulting in fewer side reactions and a stable signal. The dual-potential ratiometric sensing utilizes the dual ECL signal for self-calibration, improving anti-interference and reliability; the single-luminescent dual-potential system achieves synchronous anode / cathode luminescence, simplifying the system and improving detection accuracy. By detecting changes in the ECL signal of different concentrations of analytes, the detection of microRNA-126 is achieved.

The invention relates to the technical field of electromagnetic shielding, and discloses electronic equipment which comprises a metal assembly, a flexible circuit board assembly and a fixing piece. The flexible circuit board assembly and the metal assembly are arranged at an interval, and a first gap is formed between the metal assembly and the flexible circuit board assembly; the fixing piece is arranged in the first gap, and the fixing piece is connected with the metal assembly and the flexible circuit board assembly. According to the electronic equipment, the flexible circuit board assembly and the metal assembly are arranged at intervals, parasitic capacitance can be reduced, the antenna effect can be effectively restrained, the fixing piece is connected with the metal assembly and the flexible circuit board assembly, the flexible circuit board assembly can be fixed relative to the metal assembly, and the structural stability is improved.

An electronic device includes a circuit module and a protection module. The circuit module includes a P-N junction between a reference terminal and an electrical node, and metal connection lines coupled to the electrical node and configured to be charged due to antenna effect. The protection module includes an HV transistor and a capacitor. The capacitor is connected between the electrical node and the HV transistor and configured to turn on the HV transistor when the electrical node charges positively due to the antenna effect. The circuit module is thus maintained at a potential that does not damage the electronic device.

This application provides a method, apparatus, electronic device, and storage medium for analyzing the top layer of a digital-to-analog chip. The method includes: determining first parameter information of metal line segments connected to a third-party module in the top layer of the digital-to-analog chip based on a chip layout data file of the top layer; determining antenna risk values ​​of connection nodes between the top layer of the digital-to-analog chip and the third-party module based on the first parameter information; when the antenna risk value is higher than a preset risk threshold, converting the chip layout data file into a first diagram structure and determining second parameter information between the third-party modules based on the first diagram structure; and analyzing antenna effects occurring at connection nodes between the top layer of the digital-to-analog chip and the third-party module based on the second parameter information. This application can perform analysis of the top layer of a digital-to-analog chip without using GDSII for antenna effect analysis.

The invention belongs to the technical field of chemical analysis sensing and materials, and particularly relates to an L-histidine functionalized lanthanide series metal-organic gel sensor as well as a preparation method and application thereof. According to the sensor, a stable 353 nm reference signal generated by Zr < 4 + >-L-His ligand-metal charge transfer (LMCT) is combined with a formaldehyde responsive 546 nm signal output by a BTC-Tb < 3 + > antenna effect to construct a self-calibration double-signal ratio detection mechanism (I546 / I353), so that the detection reliability is remarkably improved. The sensor can be integrated on a fluorescent test strip and a molecular logic gate, realizes on-off type visual grading detection, is suitable for on-site rapid quantitative and qualitative analysis of formaldehyde in complex scenes such as environmental water bodies and industrial products, and solves the problems of poor stability, weak interference resistance and insufficient single-signal reliability of a traditional sensor.

A low formation voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that is embedded with a pair of second conductive structures and a patterned material stack. One of the sacrificial conductive pads has a first region and contacts a surface of one of the second conductive structures that contacts a surface of an underlying first conductive structure, and the other of the sacrificial conductive pads has a second region different from the first region and contacts a surface of the other of the second conductive structures that contacts a surface of a top electrode of the patterned material stack. A plasma treatment is performed to induce an antenna effect and convert a dielectric switching material of the patterned material stack into a conductive filament. After the plasma treatment, the pair of sacrificial conductive pads is removed.

The present disclosure provides an antenna effect processing method, relates to the technical field of artificial intelligence, and particularly relates to the technical field of chip design, integrated circuit design and manufacturability design. The method comprises the following steps: based on the port correspondence relationship between a target module and an interaction module, determining an interaction port for a target port to be designed in the target module among ports included in the interaction module; based on an interaction metal layer required by a wire of the interaction port and a corresponding interaction layer area of the interaction metal layer, and an actual gate oxide layer area corresponding to the interaction port, determining an equivalent gate oxide layer area corresponding to the interaction metal layer; and based on the equivalent gate oxide layer area corresponding to the interaction metal layer, designing a target layer area used by a target metal layer corresponding to the interaction metal layer for wire of the target port. The present disclosure realizes accurate quantification and pre-constraint of cross-module interconnection antenna effect at the module level, shortens the design iteration period, and optimizes the chip area efficiency.

A three dimensional (3D) Integrated Circuit (IC) package is provided. The 3D IC package includes a first IC die having a first substrate at a back side of the first IC die and a second IC die stacked at the back side of the first IC die and facing the first substrate. The 3D IC further includes a Through Silicon Via (TSV) through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV. A protection module is fabricated in the first substrate. The protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

An integrated circuit (IC) device includes an antenna effect protection device, and a to-be-protected device. A first source / drain of the antenna effect protection device is electrically coupled to a gate of the to-be-protected device. The antenna effect protection device is a bulk-less device.

An RF coaxial jumper, its wire-end connector and assembly method. Through the structural cooperation of two buckled metal shells, a shielding structure is provided at the joint of the wire-end connector and the coaxial cable core wire layer to avoid wave leakage at the joint of the wire-end connector and the coaxial cable core wire layer, and the shielding structure overlaps the exposed outer conductor layer of the coaxial cable to form a shielding loop to avoid the antenna effect of the shielding structure. Therefore, the RF coaxial jumper of the present invention can transmit millimeter-wave high-frequency signals in the frequency range of 28-45 GHz or even higher than 45 GHz to meet the millimeter-wave high-frequency signal transmission of 5G communication.

The present disclosure provides a semiconductor test structure and a preparation method thereof. The semiconductor test structure comprises a substrate, the substrate comprises a first doped region and a second doped region, a transistor is arranged on the substrate of the first doped region, and a first conductive layer, a dielectric layer and a second conductive layer are sequentially arranged on the substrate of the second doped region. The material of the first conductive layer comprises a metal material, the material of the substrate comprises a semiconductor material, the first conductive layer is electrically connected with a gate of the transistor, the first conductive layer forms a Schottky contact with the substrate, and the first conductive layer and the second conductive layer are electrically isolated by the dielectric layer. The charge on the gate can be discharged through the first conductive layer and the substrate. The first conductive layer, the dielectric layer and the second conductive layer can jointly form a capacitor structure, and the capacitor structure can share the charge on the gate. Therefore, the semiconductor test structure and the preparation method thereof provided by the present disclosure can more comprehensively reduce or avoid the damage of the antenna effect to the transistor, thereby improving the protection effect of the transistor.

The invention discloses a semiconductor device and a preparation method of the semiconductor device, the semiconductor device comprises a substrate, the substrate is provided with a memory device region and a protection device region, the protection device region surrounds the memory device region, and the protection device region contains doping ions of a first doping type; the multiple memory devices are arranged in the memory device area in a stacked mode in the direction perpendicular to the substrate; the protection contact is connected with the protection device region, the protection contact comprises doping ions of the second doping type, and the protection contact surrounds the memory device; wherein the first doping type is opposite to the second doping type. The combined action of the protection contact and the protection device area can release charges generated by plasma induction, the influence of the antenna effect on the chip manufacturing process is solved, meanwhile, the protection device area surrounds the storage device area, the area of the storage device is not occupied, the storage density can be improved, and a certain protection effect can be achieved on the storage device.

The invention discloses a fluorescence detection method of tin ions Sn < 4 + >, which is characterized in that on the basis of a dual-emission ratio sensing mechanism of a europium metal organic framework, Eu < 3 + >, 2-hydroxyterephthalic acid (HTPA) and 1, 10-phenanthroline are coordinated and self-assembled to synthesize cubic EuMOF, and the cubic EuMOF simultaneously generates dual-emission fluorescence of HTPA and Eu < 3 + > at 430 nm and 614 nm respectively. When Sn < 4 + > exists, the EuMOF structure collapses, so that the antenna effect between the ligand and Eu < 3 + > is destroyed, the I614 / I430 fluorescence intensity ratio change is initiated, the Sn < 4 + > quantitative detection is realized, the detection limit is as low as 54.37 nM, and the linear range is 0.1-100 [mu] M. Aiming at field detection requirements, EuMOF test paper is further combined with RGB analysis application assisted by a smart phone to construct a portable visual sensing platform. The fluorescent sensor constructed by the invention can realize quantitative analysis and rapid detection of Sn < 4 + >, has high sensitivity, high selectivity and good anti-interference capability, and can be used for detecting Sn < 4 + > in an actual sample.

The invention relates to an antenna effect driving layer distribution method considering the size of a through hole, and the method comprises the following steps: (1) an initialization stage: restoring abstract mass points in a 3D grid chart into rectangular grid units with geometric sizes, carrying out the statistics of the wiring resource information of each wiring layer, and obtaining an initial 2D wiring scheme; (2) legalization stage: on the basis of a parameter selection strategy of wire net dissimilation, setting differentiated weight parameters for wire nets with different time sequence criticality, eliminating wire overflow through wire clearing and rewinding, and optimizing the time sequence performance of the wire nets; and (3) an optimization stage: simulating a stacking sequence of metal layers from bottom to top in a chip manufacturing process by adopting a wire moving strategy considering a wire net structure, calculating an antenna effect violation number layer by layer, and cutting an antenna effect violation area by adjusting a wiring layer where a wire is located, so as to reduce the antenna effect violation number. According to the method, under the condition that various through hole sizes and wire sizes are considered, the number of antenna effect violations can be reduced, and the performance of a chip is improved.

This invention discloses a layout structure, design method, and system-on-a-chip for a clock buffer module. The layout structure of the clock buffer module includes: a standard buffer unit; multiple functional element units, including at least one pre-embedded coupling capacitor unit and at least one pre-embedded charge discharge unit; multiple functional element units are integrated in the layout in a manner surrounding the standard buffer unit; signal pins and power pins are located on different preset high-layer metal layers, and the signal connection terminals and power connection terminals of the standard buffer unit are electrically connected to the signal pins and power pins respectively through internal connection holes. The technical solution provided by this invention improves upon the uncontrollable problems such as wiring, voltage drop, and antenna effects caused by directly using high-drive-force devices provided in the process library, while also avoiding the dependence on customized high-drive-force devices for high-speed, long-distance, low-latency applications.

An exemplary apparatus includes a through-silicon via (TSV) and circuit that protects against the antenna effect and electrostatic discharge (ESD). The circuit can include a plurality of transistors whose gates are each electrically coupled to a signal that passes through the TSV. Various other apparatuses, systems, and methods are also disclosed.

The semiconductor structure includes a substrate, an active element, at least one discharge structure, a gate pad, a plurality of interconnection metal layers, and a fuse structure. The substrate has an active region and a dummy region. The active element is arranged in the active area of the substrate. The discharge structure is disposed in the dummy region of the substrate. The gate pad is disposed over the active device and the discharge structure. The multi-layer interconnection metal layer is arranged above the substrate and located among the grid electrode connecting pad, the discharging structure and the grid electrode connecting pad, and the active component is electrically connected with the grid electrode connecting pad through the multi-layer interconnection metal layer. The fuse structure is provided with a first part and a second part which are separated from each other, the first part is connected with the multiple interconnection metal layers, and the second part is connected with the at least one discharge structure. The invention further provides a manufacturing method of the semiconductor structure, which has the advantage of reducing the antenna effect.

The invention relates to a circuit structure and a semiconductor structure for eliminating an antenna effect, the circuit structure for eliminating the antenna effect comprises at least one diode and a buffer, one end of the diode and the input end of the buffer are connected with the input end of the circuit structure, and the output end of the buffer is the output end of the circuit structure. The other end of the diode is grounded. In the embodiment of the invention, through the above circuit structure, charges accumulated in the circuit can be exported through the diode, that is to say, when the charges are accumulated too much, reverse breakdown can be preferentially carried out on a grid tube of the diode, so that charge leakage is realized, damage to a grid electrode in a semiconductor device needing to eliminate an antenna effect can be avoided, and the antenna effect can be eliminated. And the antenna effect in the circuit is effectively eliminated.

The invention discloses a process method for eliminating an antenna effect of a power device with an ESD (Electro-Static Discharge) structure, which comprises the following steps of: after etching a polycrystalline silicon grid of the power device, depositing to form a silicon nitride layer; forming an ESD (Electro-Static Discharge) oxide layer on the silicon nitride layer, and depositing a polycrystalline silicon layer on the ESD oxide layer; performing ion implantation of the ESD structure; carrying out photoetching and etching on the polycrystalline silicon layer of the ESD structure, completing pattern formation of the polycrystalline silicon structure in the ESD structure, and then carrying out thermal annealing; carrying out a wet etching process of the ESD oxide layer, and removing the redundant ESD oxide layer; removing the silicon nitride layer by a wet etching process; and performing body region injection of the power device. SiN is introduced to serve as a barrier layer for wet etching of the ESD oxide layer, the antenna effect caused by ESD OX local over-etching can be effectively prevented, the convergence of BV voltage resistance and IDSS electric leakage is improved, and the occurrence probability of low product yield can be remarkably reduced.

The present application provides an antenna effect electrostatic discharge detection circuit and a method for measuring electrostatic discharge quantity. The antenna effect electrostatic discharge detection circuit includes a first antenna effect electrostatic discharge detection device and a first electrostatic discharge protection device. The first antenna effect electrostatic discharge detection device is coupled between a first pad and a second pad. The first electrostatic discharge protection device is coupled between an input / output pad and the first pad. An internal circuit is coupled to the input / output pad, the first external electrostatic discharge protection device and the first antenna effect electrostatic discharge detection device.

The invention discloses a power supply integrity repairing method and device and a storage medium, and belongs to the technical field of semiconductors, and the power supply integrity repairing method comprises the steps: obtaining layout power supply distribution network data, executing voltage drop analysis and electromigration analysis, and generating voltage drop distribution data and electromigration hotspot data; identifying an intersection region which conforms to the minimum punching rule and is associated with the voltage drop difference value and the electromigration value in the adjacent metal layers as a candidate punching region; for each candidate region, calculating the maximum number of through holes based on a voltage drop difference value when the region has no through hole, and calculating the maximum number of through holes based on an electromigration value when the region has the through hole; and executing a through hole adding operation according to a calculation result, and generating optimized layout data. The number of the through holes is dynamically determined through collaborative analysis of voltage drop and electromigration, the influence of parasitic parameters can be reduced while the integrity of the power supply is improved, the process reliability is ensured, the antenna effect is prevented, and comprehensive optimization of the power supply network is achieved.

This invention discloses a multifunctional integrated transparent antenna, belonging to the field of wireless communication technology. It includes a transparent antenna plate, the upper surface of which is printed with a radiator and a first coplanar waveguide using a metal mesh or nano-silver process. A coupling plate, on which a second coplanar waveguide is disposed, is fixedly connected to the first coplanar waveguide by screws, used for feeding or receiving radio frequency signals to the transparent antenna plate via capacitive coupling. A coaxial cable is welded and fixed to the coupling plate. A light source circuit board is disposed on the back of the transparent antenna plate, and has a power supply and multiple LEDs on it. A housing is fixedly connected to the transparent antenna plate, the coupling plate, and the light source circuit board. This invention covers multiple frequency bands of indoor distribution systems and integrates radiated radio frequency signals and information indication functions. Its appearance does not affect the aesthetics of the environment. Furthermore, by suppressing the antenna effect of the traces on the light source circuit board of the indicator, it avoids the influence of the radiation from the light source circuit board on the radiation and passive intermodulation performance of the transparent antenna.

The invention provides an analysis method and device for a top layer of a digital-analog chip, electronic equipment and a storage medium, and the method comprises the steps: determining first parameter information of a metal line segment, connected with a third-party module, of the top layer of the digital-analog chip according to a chip layout data file of the top layer of the digital-analog chip; according to the first parameter information, determining an antenna risk value of a connection node with the third-party module in the top layer of the digital-analog chip; when the antenna risk value is higher than a preset risk threshold value, converting the chip layout data file into a first graph structure, and determining second parameter information between the third-party modules according to the first graph structure; and according to the second parameter information, analyzing an antenna effect of a connection node between the top layer of the digital-analog chip and the third-party module. According to the application, the analysis of the top layer of the digital-analog chip can be realized in the GDSII which is not used for the running antenna effect.

The invention discloses an outrigger in-wall communication system which comprises an in-arm controller, an optical fiber cable, a cable drum and a main controller, the in-arm controller, the optical fiber cable and the cable drum are arranged in a crane outrigger, the main controller is arranged on a crane rotary table, the optical fiber cable stretches out and draws back on the cable drum, one end of the optical fiber cable is connected with the in-arm controller through a first optical fiber converter, and the other end of the optical fiber cable is connected with a second optical fiber converter. The other end is connected with the main controller through the second optical fiber converter; the in-arm controller collects internal signals of the crane extending arm and transmits the internal signals to the main controller through the first optical fiber converter, the optical fiber cable and the second optical fiber converter in sequence. By means of the anti-electromagnetic interference characteristic of optical signals, electromagnetic interference generated by the antenna effect caused by the fact that the cable of the cable drum in the arm is pulled up too long can be effectively avoided, and stable transmission of signals in the arm is achieved.

The invention relates to a radio frequency signal rhombic ground-covering hole shielding design in PCB layout. The design comprises a radio frequency signal line arranged on a PCB wiring layer, grounding copper sheets symmetrically arranged on two sides of the signal line, and a plurality of rhombic grounding holes arranged on the grounding copper sheets according to a preset interval. The long axis direction of the rhombic grounding hole is parallel to the radio frequency signal line, the ratio of the long axis to the short axis is 2: 1, and the array spacing is 1.2 mm. The width of the radio frequency signal line is 0.3 mm, and the distance between the radio frequency signal line and the grounding copper sheet is 0.15 mm. The technical scheme further comprises arc-shaped corner design, arc tear point connection and staggered ground hole design in the multi-layer board structure. According to the invention, the problems of electromagnetic leakage, antenna effect, impedance abrupt change, discontinuity of corner protection and the like in the traditional radio frequency PCB design are solved through a three-dimensional continuous ground covering shielding technology. The actual measurement shows that the design reduces the distortion of radio frequency signals by about 20-22%, improves the insertion loss by 0.3 dB, provides 24dB isolation in a 3.5 GHz frequency band, reduces the highest temperature point on the surface of a PCB by 8 DEG C, and significantly improves the performance and reliability of a radio frequency circuit.