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A Method for Optimizing a Compact Standard Cell Library

A standard cell library and basic cell technology, applied in the direction of instruments, calculations, electrical digital data processing, etc., can solve the problem of low usage of low power consumption cells, improve manufacturability, be conducive to lithography friendly, resolvable The effect of rate enhancement

Active Publication Date: 2011-12-14
WUXI ZHONGKE MICROELECTRONICS IND TECH RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The consensus in the industry is that low-power designs are not required for designs below a few million gates, so the utilization rate of low-power units is low.

Method used

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  • A Method for Optimizing a Compact Standard Cell Library
  • A Method for Optimizing a Compact Standard Cell Library
  • A Method for Optimizing a Compact Standard Cell Library

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Embodiment Construction

[0027] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0028] The present invention reduces the types of units contained in the standard unit library to a critical value under the condition of ensuring circuit performance, that is, uses as few and frequently needed units as possible to traverse all complex logics as much as possible, thereby realizing the unit library Streamlining, simplifying manufacturability issues.

[0029] The method for optimizing the streamlined standard cell library provided by the present invention includes: selecting a basic unit that realizes required circuit functions, and the basic unit includes at least an inverter, a buffer, a basic gate unit, a mixed gate unit, an arithmetic unit, and a sequence unit; add delay unit, pull-up / pull-down unit, fi...

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Abstract

The invention discloses a method for optimizing a simplified standard unit library. The method comprises the following steps of: selecting a basic unit for realizing a needed circuit function, wherein the basic unit at least comprises a phase inverter, a buffer, a basic gate unit, a mixed gate unit, an operation unit and a time sequence unit; arranging a delay unit, a pull-up / pull-down unit, a filling unit, a capacitance filling unit, a substrate link and an antenna effect restraining unit in the simplified standard unit library; selecting a multi-input logic by adopting a logical decomposition mode; and realizing a multi-driving capability by adopting a driving decomposition mode. In the method, the performance and the realizing complexity of a circuit are compromised, the quantity of domain pattern shapes is reduced, friendly photolithography is facilitated, the resolution is increased, the manufacturability and realizing efficiency of the circuit are improved, and the performance of the circuit is ensured to a certain degree.

Description

technical field [0001] The invention relates to the technical field of 65nm integrated circuit manufacturing technology and layout design, in particular to a method for optimizing a simplified standard cell library. Background technique [0002] The standard cell library is a necessary condition for LSI / VLSI automated design, supporting the entire automated design process from front-end function simulation to back-end layout implementation. When the feature size of integrated circuits is reduced to 65 nanometers, IC manufacturing technology has encountered unprecedented challenges, because the design scale is getting larger and the complexity is getting higher and higher. Manufacturability has become an important consideration in integrated circuit design. From the perspective of the existing design process, the design technology of 65nm standard cells is also facing major challenges. Optimizing the standard cell library for manufacturability is the most critical step. [...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 罗海燕陈岚尹明会赵劼
Owner WUXI ZHONGKE MICROELECTRONICS IND TECH RES INST
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