275 results about "Protocol processing" patented technology

The invention discloses a semiconductor device communication system and method based on an SECS / GEM protocol. The system comprises an SECS / GEM protocol processing module, a PLC communication module and a service logic processing module. The protocol processing module realizes message coding and decoding and state management through an HSMS / GEM layered architecture, and supports equipment capability dynamic negotiation; the PLC communication module adopts a factory mode to adapt to a multi-manufacturer controller to realize online mapping of a physical register and a logic address; and the business logic module dynamically loads the command processor based on a reflection mechanism, and realizes multi-condition event triggering through a rule engine. The method comprises the processes of system initialization, message priority scheduling, composite alarm processing and exception recovery, and the equipment integration efficiency and the communication reliability are remarkably improved. The method solves the problems of rigid parameter mapping, single event processing and poor equipment compatibility of a traditional scheme, and can be widely applied to equipment automation control of scenes such as semiconductor wafer manufacturing and packaging testing.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

The invention discloses a direct memory access (DMA) communication device for a computing network convergence computing architecture and a working method of the DMA communication device. The DMA communication device comprises a DMA transaction processing module and a protocol conversion module; the DMA transaction processing module is used for analyzing related DMA read-write requests, realizing processing of the DMA read-write requests and receiving of response data of the DMA read requests and completing processing of interrupt requests at the same time, and the protocol conversion module is used for completing conversion of read-write requests between a DMA interface and an AXI interface and mapping of response states. The invention aims to realize efficient protocol conversion between AXI and DMA interfaces, avoid the problem of DMA read request starvation caused by resource competition and ensure the consistency of DMA data access so as to improve the performance of an accelerator in high-performance calculation and artificial intelligence application, reduce transmission delay and improve data transmission bandwidth and energy efficiency.

The invention discloses a PON-based multi-protocol communication method and device, and the method comprises the steps: distributing a corresponding internal scheduling time slot to each network protocol processing unit for data uploading to each network protocol processing unit when a data processing module detects that the network protocol processing units connected with each field bus device have to-be-uploaded service data; and when one internal scheduling time slot is used up, interrupting the uploading of the service data until the next internal scheduling time slot allocated to the internal scheduling time slot is recovered from interrupting the uploading of the data. And the PON module monitors a global scheduling time slot allocation instruction issued by the optical line terminal in real time, converts an uploaded data frame into an electric signal, transmits the electric signal to the optical module through an internal link, converts the electric signal into an optical signal through the optical module in an allocated global scheduling time slot, and uploads the optical signal to the optical line terminal through an optical distribution network. Real-time performance and orderliness of transmission of service data in multiple field bus devices in a PON network are achieved, the requirement of industrial communication for data transmission is met, and transmission resource distribution is optimized.

The invention relates to the technical field of data processing, in particular to an FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit) cooperative network data processing system, which comprises a network interface module for receiving and forwarding an external data flow, and a protocol analysis module for distinguishing a service message and a protocol message based on a message header characteristic and a load mode; the service processing module executes protocol format conversion, security encryption and data extraction in the FPGA; the protocol stack interaction module transmits a protocol message to the CPU through the MAC layer communication interface; the protocol stack module activates necessary protocol services in the CPU and generates a resource allocation instruction; and the data integration module receives the service data flow and the protocol processing result, and dynamically adjusts the encryption rule. According to the invention, FPGA business data closed-loop processing and CPU protocol service physical isolation are realized, a double-processing-unit architecture supports financial signature and industrial filtering cascade operation, the MAC layer interface is additionally provided with cyclic redundancy check to guarantee transmission reliability, and equipment processing efficiency and anti-attack capability under a fusion scene are improved.

The invention discloses an SATA (Serial Advanced Technology Attachment) bus system based on an FPGA (Field Programmable Gate Array) and an implementation method thereof, and the SATA bus system comprises a hierarchical protocol processing unit which is used for realizing command analysis, data encapsulation, channel coding and signal conversion functions; the control module is used for receiving a read-write command and read-write parameters sent by the host, and then controlling the hierarchical protocol processing unit to read target data of the storage device according to the read-write command and the read-write parameters, or controlling the hierarchical protocol processing unit to write the target data into the storage device; the command and data processing module is used for caching read-write commands, read-write parameters and upper computer data in FIFO (First In First Out) in a layered manner; and the test data processing module is used for testing whether the storage equipment reads and writes the data normally to obtain a test result. According to the method, the interface design is simple and clear, the delay is low, the data reading and writing function of the storage medium can be tested without intervention of a host or a CPU, and the method can be widely applied to the technical field of serial advanced technology accessory interface control.

The invention relates to the technical field of intelligent interface generation, in particular to an interactive interface generation method and system, computer equipment and a medium. The method comprises the following steps: receiving a multi-protocol interaction request, and extracting natural language context information carried in the multi-protocol interaction request through a protocol processing layer; according to the natural language context information, executing cue word processing to generate interface generation trigger judgment; when the interface generation trigger judgment indicates that an interface needs to be generated, generating an interface mode definition instance based on the natural language context information and a preset cue word template; and according to the interface mode definition instance, generating an interactive interface through a rendering output device. In this way, the technical problem that in an existing interface generation technology based on natural languages, it is difficult to collaboratively optimize the interface dynamic adaptation capacity and the system expansibility is solved, and the intelligent level, cross-platform compatibility and service response agility of interface generation are improved.

The PIO communication device comprises a protocol conversion module and a PIO transaction processing module, the protocol conversion module and the PIO transaction processing module are connected with each other, the protocol conversion module is connected with a computing component connected to a network-on-chip NoC through an AXI interface, and when the computing component initiates a PIO read-write request, the PIO transaction processing module sends the PIO read-write request to the computing component; the protocol conversion module performs conversion of read-write requests between an AXI protocol and a PIO protocol and mapping of response states, and the PIO transaction processing module initiates register access and descriptor writing operation to the network protocol processing component by analyzing the converted PIO read-write requests and receives register read response data returned by the network protocol processing component. According to the invention, a decoupling design of an address channel, a data channel and a response channel is adopted, conversion of a PIO read-write transaction between an AXI interface and a network protocol interface is completed, and high-bandwidth and low-delay non-blocking PIO data transmission and processing are realized.

The invention relates to the technical field of encoder communication interface circuits, in particular to a multi-protocol encoder communication interface circuit based on hardware configuration, which comprises a core control and protocol processing module, a hardware configuration and mode recognition module, an RS-485 differential driving and receiving module and an interface protection circuit module. In the invention, the problems that the hardware cost is high, the PCB layout is complicated, the overall size of the system is increased, the types of connectors are diversified and the wiring difficulty is increased due to the fact that an independent physical interface circuit needs to be independently designed for each protocol such as BISS and Tamagawa or a special integrated chip with a solidified factory function is adopted in the existing scheme are thoroughly solved; and meanwhile, the problems that chips need to be replaced or hardware needs to be redesigned and the configuration flexibility is poor in the protocol updating of an existing scheme are solved, the time sequence conflict risk existing in software dynamic switching protocols is avoided, and the defects that a traditional circuit is poor in surge resistance, signal crosstalk is caused and debugging and maintenance are complex are overcome.

The invention relates to the technical field of communication, in particular to a three-network convergence communication terminal system based on core size level heterogeneous integration and an implementation method, and the system comprises a radio frequency transceiving core particle, a baseband processing core particle, a storage core particle, a control scheduling core particle and a power management core particle. According to the invention, systematic linkage optimization of cross-domain parameters is realized through a core size level heterogeneous integration and state space cooperation mechanism, and real-time channel state information directly drives a scheduling algorithm to solve in a global state space. According to the method, the problems of low energy efficiency utilization rate, lagged resource scheduling response, low power consumption and the like of a terminal in a multi-network concurrency and switching scene due to the fact that a multi-network communication module is discrete and a cross-hardware-level dynamic coordination mechanism is lacked are effectively solved, and the service life of the terminal in a multi-network concurrency and switching scene is prolonged. And therefore, the problems of limited terminal volume, high power consumption and poor service continuity can be solved.

The invention provides a PLC integrated digital twinning control enhancement system and method, and relates to the technical field of cloud PLC control, a PLC integrated development environment module comprises an instruction set generation unit, a digital twinning function plug-in library and a PLC compiler unit which are connected in sequence, the instruction set generation unit comprises an FB library, a PLC control instruction generation unit, a control instruction mapping form and a server intermediate variable set which are connected in sequence; the PLC operating environment module comprises a protocol processing unit, a PLC main control logic unit and a server driving program which are connected in sequence, the PLC main control logic unit comprises a DT decision triggering subunit, and the server driving program comprises a strategy control subprogram and a virtual control instruction sending subprogram; the DT decision triggering subunit is connected with the server driving program; and the PLC virtual space module comprises a client driving unit, a virtual IO management unit and a data analysis unit which are connected with one another.

The invention discloses a construction method for dynamically reconstructing a multi-modal edge computing hardware architecture and a cross-industry application method, and relates to the field of edge computing hardware architectures. A five-level heterogeneous architecture is adopted to construct a field self-adaptive dynamic reconstruction calculation unit, and an equipment abstraction layer is constructed to realize module hot plugging and calculation power distribution; a multi-protocol ubiquitous interconnection interface engine is established, a hardware-level analysis architecture is integrated, and multi-protocol analysis and rapid switching are supported; an environment self-adaptive energy efficiency regulation and control system is deployed, and wide-temperature operation is realized by adopting a bionic composite heat dissipation design; an edge-region-cloud three-layer elastic scheduling network is constructed, cross-domain computing power arrangement is realized through federal learning, and the method is adaptive to multi-industry scenes. According to the method, the hardware reuse rate and the wide-temperature environment adaptability are improved, the multi-protocol processing delay is reduced, the computing power scheduling efficiency is optimized, the limitation of traditional equipment is broken through, and the efficient and stable operation requirements of cross-industry scenes such as electric power and medical treatment are met.

The invention relates to the technical field of electric digital data processing, and discloses an intelligent campus network security protection system. A network data acquisition module of the system continuously monitors data transmission flow of a smart campus network environment to obtain an original data packet; the chaotic encryption engine encrypts an original data packet by using a key stream based on dynamic chaotic mapping, wherein the key stream is generated by multi-chaotic system switching and a random parameter distribution mechanism; the security protocol processing module converts the encrypted data packet into a format conforming to a network security protocol standard and transmits the encrypted data packet; the data decryption unit decrypts the received encrypted data packet; the security threat analysis module identifies and estimates potential network attack behaviors according to the decrypted plaintext data; and the protection strategy controller generates and executes a network security protection instruction according to the threat analysis result. The system can effectively protect the network security of the smart campus, resist various network attacks, and ensure the security of data transmission and storage.

The invention is suitable for the technical field of Ethernet data transmission, and provides a system and a method for enhancing the reliability of Ethernet non-connection protocol data transmission. The system comprises an Ethernet data receiving module, a receiving RAM cache module, a protocol judgment module, an ARP table cache updating module, a UDP application layer protocol processing module, a UDP protocol response module, an ARP, ICMP and UDP data FIFO cache module, a protocol arbitration reply module, a sending RAM cache module and an Ethernet data sending module. On the basis of CRC data verification, the UDP response module is added, certain data is replied when the non-connection protocol data of the sending end is received, the sending end is informed of whether the data packet is successfully received or not, the sending end can retransmit the lost data packet according to the response message, the stability of data transmission is improved, and the user experience is improved. And the reliability of Ethernet non-connection protocol data transmission can be greatly enhanced.

The invention discloses an access request processing method under centralized storage and electronic equipment, and relates to the technical field of centralized storage, and the method comprises the following steps: setting a virtual file system in a node, and carrying out cache mirror image synchronization among the nodes by utilizing the virtual file system. After any node receives an access request, the node firstly determines whether the access request is a read request or a write-in request, and then processes the read request or the write-in request by using the cache mirror image. The problems that when multiple nodes of a local file system are used for providing read-write services to the outside, data are damaged easily due to the fact that a memory structure has no consistency protection, and protocol processing is conducted depending on one node can be solved. According to the method, the virtual file system is introduced into the nodes, so that the nodes are mounted on the same volume, cache synchronization between the nodes is performed by using the virtual file system, and unification of cache mirror images between the nodes is realized. Through the cache mirror image between the nodes, the capability of providing services to the outside by the multiple nodes is realized.

The invention discloses a protocol message tamper-proofing method and system based on symmetric encryption and a medium, and relates to the technical field of industrial automation Ethernet time synchronization. According to the method, mirror image monitoring is carried out on the message receiving and sending process in the protocol processing process of time synchronization equipment, a protocol message is obtained and analyzed, and the protocol message tamper-proofing effect is achieved; a message abstract and encrypted verification data thereof are generated at a sending end, and a corresponding abstract is obtained through decryption at a receiving end; consistency comparison is carried out on the sending side abstract and the receiving side abstract based on the time window, and a tamper-proof consistency coefficient is calculated to judge the integrity of the protocol message; on the basis that the integrity is qualified, performing difference analysis on an encryption verification result, and calculating an encryption credibility coefficient to evaluate the credibility state of the symmetric encryption link; and further performing coupling calculation to obtain a time synchronization security coupling coefficient, comprehensively evaluating the influence of tamper-proofing and symmetric encryption on the time synchronization operation security, and implementing a security regulation and control strategy according to the influence, thereby improving the security and stability of the time synchronization system.

The embodiment of the invention provides a multi-communication interface expansion device based on an SPI protocol. In one specific embodiment, the expansion device comprises a storage unit and a communication unit; the communication unit comprises a control interface, a control module and a driving isolation device; the control module comprises a protocol control module, a protocol selection module and a plurality of protocol processing modules for respectively processing different protocols; the communication unit further comprises a plurality of first communication interfaces corresponding to the protocol processing modules; the control interface is an SPI (Serial Peripheral Interface); the protocol control module configures a corresponding first communication interface through the gated protocol processing module; the protocol control module controls the gated protocol processing module to call and process the to-be-sent data from the storage unit, and outputs the to-be-sent data to a fourth external device; and the gated protocol processing module receives to-be-received data sent by the third external equipment, processes the received to-be-received data and stores the processed to-be-received data to the storage unit, so that multi-communication interface expansion of the SPI protocol is realized.

The invention discloses a real-time communication system, client equipment, a real-time communication method and a communication network. The real-time communication system comprises a webpage view subsystem which comprises a webpage real-time communication module and a view interface module; the native code subsystem comprises a native bridging module and a protocol processing module; and the operating system subsystem comprises a plurality of native interface modules. According to the real-time communication system, an interface generated after rendering of data generated based on a native code subsystem and an operating system subsystem is displayed through a view interface module for interface construction, media transmission and processing are achieved through introduction of a webpage real-time communication module, and signaling interaction is achieved through introduction of a protocol processing module. Through the system, the interface development efficiency can be effectively improved, the client development cost and technical barriers are reduced, and the cross-platform compatibility and media processing efficiency of real-time communication are improved.

The invention belongs to the technical field of space communication protocol processing, and particularly relates to an intelligent frame packaging method and device for a satellite internet heterogeneous link. Comprising the steps that an IP packet is preprocessed and packaged into a CCSDS packet, and bytes are processed based on a general cycle to adapt to different link requirements; an insertion domain differentiation strategy and a multi-pointer cooperation mechanism are adopted to complete MPDU dynamic adaptation filling and cross-domain processing, and the cross-MPDU data splicing problem is solved through accurate boundary judgment and a differentiation filling strategy; fully effective or partially effective filling of the VCDU frame is realized through multi-pointer cooperation; a self-adaptive verification mechanism parallel to the packaging process is constructed, a WA-TOPSIS multi-attribute decision algorithm is fused, and an optimal verification strategy is selected according to multi-dimensional indexes; a bucket reset flow control algorithm based on a time interval is adopted, a credit overdraft and debt compensation mechanism is combined, and flow parameters are dynamically adjusted to avoid congestion; according to the method, the data transmission stability and the link utilization rate in a heterogeneous link environment can be effectively improved.

The invention discloses an industrial Internet of Things data transmission method, and relates to the technical field of industrial Internet of Things. The system comprises a protocol adaptation analysis module, a data standardization processing module, a heterogeneous data fusion module and a deterministic transmission management module. The plug-in protocol analysis engine comprises a protocol feature fingerprint database and a plug-in engine maintenance unit, and breaks through the traditional curing mode of one protocol and one program: on one hand, the protocol feature fingerprint database can collect bottom features of more than 30 industrial protocols, and rapid matching is realized through a structured index table; and on the other hand, when the protocol is newly added or updated, only a new plug-in needs to be developed and put into a specified directory, the plug-in manager loads in real time without restarting an engine, the tedious operation of rewriting a program in a traditional scheme is reduced, meanwhile, the deep packet detection unit ensures the protocol analysis accuracy, and the protocol processing reliability is further improved through an abnormal alarm mechanism.

The invention provides an FPGA (Field Programmable Gate Array)-based national secret algorithm acceleration device and electronic equipment, the device comprises a PCIE (Peripheral Component Interface Express) bus processing module, the PCIE bus processing module is used for completing data packaging and unpackaging work of each layer of a PCIE protocol, and the PCIE bus processing module further provides an AXI4 interface and supports AXIFULL and AXILITE protocols; the AXI bus processing module comprises an AXIFULL protocol processing module and an AXILITE protocol processing module; the storage module adopts a high-capacity full-dual-port BRAM (Border Random Access Memory) in the FPGA and is used for storing intermediate data and input and output data; the national cryptographic algorithm control module is responsible for managing and scheduling operation of three national cryptographic algorithm sub-modules SM2, SM3 and SM4 and processing data interaction between the sub-modules and the host; and the hardware acceleration unit comprises three independent hardware acceleration modules SM2, SM3 and SM4, each hardware acceleration module is responsible for a calculation task of a corresponding algorithm, and each hardware acceleration module comprises a control interface and a BRAM read-write interface for instruction and data interaction.

The invention discloses a read-only device supporting multi-channel M.2 interfaces. The read-only device adopts a main control module and integrates PCIe and SATA protocol analysis engines, and the main control module identifies protocols followed by M.2 devices connected with all the interfaces and carries out protocol processing logic switching; the main control module is further provided with a plurality of arbitration logic units used for adjusting resource distribution among the interfaces. The interface module at least comprises multiple paths of M.2 interfaces, and each path of M.2 interface is independently provided with a PCIe channel and an SATA channel to be connected with the main control module; and the security interception module is used for synchronizing protocol information followed by the M.2 equipment connected with each interface and write protection state information of each interface from the main control module, and judging and executing whether write protection is carried out on the interface or not. According to the method and the device, the problem that the existing evidence obtaining equipment lacks M.2 native support and is coordinated with the requirement of high-concurrency secure data transmission of a plurality of transmission channels is solved.

Apparatuses, methods, and systems are disclosed for selecting an authentication type in a 5G network. One apparatus includes a processor and a network interface that receives a first message requesting to register a remote unit to the mobile communication network, where the remote unit is connected to a non-3GPP access network and the remote unit does not support the NAS protocol. The processor determines an authentication request type for the remote unit, where the authentication request type is not based on the NAS protocol. The processor creates a NAS registration message on behalf of the remote unit and sends a second message to an access management function in the mobile communication network, where the second message contains the NAS registration message and the determined authentication request type.

The invention provides an SOC chip and electronic equipment, the SOC chip provided by the invention comprises a plurality of storage components, and each storage component comprises a physical layer module, a storage control module connected with the physical layer module and a storage module; the storage control module is used for transmitting a read-write operation instruction to the physical layer module, and the physical layer module is used for performing protocol processing on the read-write operation instruction to obtain a read-write control instruction and transmitting the read-write control instruction to the storage module so as to perform read-write control on the storage module; the physical layer module and the storage module are prepared through a full-custom process, and the time sequence parameter corresponding to the physical layer module is determined based on the time sequence parameter of the storage module in the full-custom process preparation. The physical layer module and the storage module are both prepared through a full-customization process, and the physical layer module can adjust the time sequence parameter corresponding to the physical layer module according to the time sequence parameter of the storage module during preparation, so that the physical layer module and the storage module can perform simulation at the same time, and the time sequence accuracy and the product reliability are improved.

The invention discloses a guarantee power supply data acquisition method and device and a computer program product, and the method comprises the steps: S1, carrying out the processing of an equipment access signal through employing a hierarchical recognition mechanism, generating a protocol fingerprint feature vector, carrying out the matching of the protocol fingerprint feature vector in a protocol library, loading a corresponding conversion rule if the matching succeeds, and carrying out the verification of the conversion rule; if not, starting a protocol learning process; s2, disassembling unknown protocol data for starting a protocol learning process into four tuples, converting the four tuples into unified intermediate representation, and starting a rule inference engine for an unknown protocol to generate and verify candidate rules through a multi-dimensional protocol conversion matrix matching rule; and S3, classifying the data converted in the step S1 or the step S2, completing protocol processing at the network edge by adopting an edge computing architecture, and allocating 5G channel resources according to the priority of power services. According to the method, a full-process optimization scheme from protocol identification and conversion to transmission is constructed, and high-reliability and high-efficiency data support is provided for a power grid.

The application provides a clock management chip, a chip management system and electronic equipment, and the chip comprises: an antenna signal processing module; a protocol processing module connected with the antenna signal processing module, used for receiving an Ethernet synchronization source clock signal, a PTP clock signal, a 1PPS clock signal and an external clock source signal, and outputting a transition clock signal according to the Ethernet synchronization source clock signal, the PTP clock signal, the 1PPS clock signal and the external clock source signal; and a clock generation module connected with the PTP protocol processing module, used for processing the clock signal and outputting a target clock signal correspondingly. The application adopts the same chip and architecture to select and process the Ethernet synchronization source clock signal and the external clock source signal, avoids the problem that there is a large delay in signal transmission caused by processing different clock source signals in different chips, reduces the error probability of signal transmission and improves the accuracy of signal transmission.

This invention relates to the field of industrial automation and control network technology, and discloses a real-time synchronization method system for LonWorks networks based on digital twin variables. Applied to LonWorks fieldbus networks, it is implemented based on a heterogeneous node system consisting of a general-purpose processing module, a LonTalk protocol processing module, and a high-speed serial communication bus. The general-purpose processing module carries a manager, the LonTalk protocol processing module maintains standard LonWorks network variables and has a built-in LonTalk protocol stack, and the high-speed serial communication bus transmits DTVP data frames. This invention achieves a significant leap in node computing power, freeing nodes from the limitations of dedicated communication chips and allowing them to directly utilize the high performance of industry-leading general-purpose microcontrollers to easily handle complex control algorithms, real-time data filtering, lightweight artificial intelligence inference, and other complex tasks.

The invention discloses a downlink data processing method and device, equipment and a storage medium. The method comprises the following steps: receiving downlink data sent by a base station, and obtaining a time slice field used for indicating a frame-level service attribute from frame header information of the downlink data; analyzing the time slice field into a mapping bitmap used for representing a terminal device set; under the condition that the bit corresponding to the terminal equipment in the mapping bitmap is determined to be set, performing forward error correction decoding on the downlink data to recover the baseband frame payload of the downlink data; performing protocol decapsulation on the baseband frame payload to obtain a protocol data unit; and in a case where it is determined that the protocol data unit corresponds to the terminal, performing upper-layer processing on the protocol data unit. According to the scheme, a frame-level service attribute sensing mechanism based on a time slice field, a terminal judgment mechanism driven by a mapping bitmap and a layered downlink data analysis and processing flow are introduced, so that efficient collaboration of downlink data in the stages of receiving, judgment, decoding and protocol processing is realized.

The present invention relates to a user equipment (UE) served by a source cell of a first network node supporting a radio access network (RAN) distributed unit (DU) function and / or Layer 2 protocol processing. The UE includes a processor and memory, and executes instructions to select from a plurality of candidate target cells controlled by the first network node based on L3 measurements and generate L1 measurements. For L1 / L2 triggered mobility (LTM), the UE determines whether the candidate cells meet preset conditions for handover and preferably periodically transmits L1 measurement reports to the first node. The preset conditions include whether single-sideband (SSB) is detected and whether a first timer associated with the L3 measurement report has not expired since a first timestamp. The UE determines whether the timer has expired since a second timestamp, and the L3 measurement report is the most recent at the time of generating the L1 measurement report.

The application discloses a kind of electric energy meter protocol data full traversal automatic test method and electric energy meter, comprising the following steps: the protocol supported by electric energy meter is modeled, and the electric energy meter data format type in protocol is defined;Establish the protocol information table of electric energy meter to be tested, and the electric energy meter protocol message is generated for each protocol in protocol information table to be tested according to electric energy meter protocol specification by master station request message generation module;According to the format corresponding to the protocol in protocol information table to be tested, generate normal test message and abnormal test message, and respectively expect normal response and abnormal response;Virtual message receiving module is generated by protocol request message generation module of master station request message generation module, and protocol request message is placed in electric energy meter communication port drive cache, and electric energy meter executes protocol processing according to protocol request message;Statistical electric energy meter protocol running result, complete all protocols of protocol information table to be tested Full traversal automatic test.The application solves the technical problem of how to accurately and quickly perform electric energy meter protocol data full traversal automatic test.