802 results about "Performance computing" patented technology

The invention provides a computing system and method for GPU computing power scheduling, and the method comprises the following steps: 1, obtaining computing task data, and carrying out the information collection of each task through receiving a to-be-processed computing task queue; according to the invention, through task information collection and deep analysis, and GPU resource omnibearing monitoring and workload prediction, deep understanding of tasks and GPU resources is realized, highly accurate computing power distribution can be carried out, resource waste is avoided, and the resource utilization rate is improved; advanced technologies such as a knowledge graph, mixed integer programming and deep reinforcement learning are fused through the intelligent scheduling model, the fusion mode is innovative in the GPU computing power scheduling field, the limitation of singleness of a traditional scheduling model is overcome, the method can better adapt to a complex and changeable computing environment, the task execution efficiency is optimized, and the task scheduling efficiency is improved. The adaptability and competitiveness of the whole system in a complex environment are remarkably improved, and an excellent solution is provided for the GPU computing power scheduling problem in the field of high-performance computing.

The invention discloses a control method for heat dissipation of a high-performance computing cluster platform, which comprises the following steps of: firstly, establishing a three-dimensional temperature distribution model of a high-performance computing cluster, acquiring data such as temperature and power consumption of each node in real time, obtaining deviation data of each node by utilizing a prediction model, and dynamically evaluating a heat dissipation risk level of each node; dividing the whole cluster into different risk areas; computing tasks are intelligently distributed based on risk levels, and high-load tasks are preferentially scheduled to a low-temperature area; and then, starting graded cooling measures for the high-risk area, continuously monitoring the cooling effect, and feeding back the result to an early warning system and a hardware maintenance module to form'prediction-regulation-feedback 'closed-loop control. The heat dissipation efficiency of the high-performance computing cluster platform is remarkably improved, the overheat fault risk is reduced while the computing performance is guaranteed, the service life of key hardware is prolonged through dynamic optimization, and intelligent cooperation of heat dissipation resources and computing tasks is achieved.

A process can include receiving, by an edge compute unit, a pre-trained machine learning model from a cloud management platform, wherein the edge compute unit is deployed to an edge location and configured to obtain one or more sensor data streams at the edge location. The edge compute unit can transmit one or more batch uploads of information associated with inference performed by the edge compute unit using the pre-trained machine learning model and the one or more sensor data streams. The edge compute unit can receive one or more updated machine learning models generated by the cloud management platform responsive to the one or more batch uploads of information, wherein the one or more updated machine learning models are based on retraining or finetuning of the pre-trained machine learning model with the one or more batch uploads of information.

The invention relates to the technical field of electromagnetic shielding compensation, and discloses an electromagnetic shielding compensation method and system for an FPC high-performance computing chip interface, and the method comprises the steps: carrying out the impedance signal collection of the FPC high-performance computing chip interface, obtaining a time domain signal and a second-order change rate curve, a time domain signal is acquired by applying an alternating current excitation signal between a signal layer and a grounding layer; performing feature extraction on the time domain signal and the second-order change rate curve to obtain a feature vector; inputting the feature vector into a support vector machine model to perform electromagnetic interference classification identification to obtain an electromagnetic interference mode type; performing weighted fusion analysis on the time domain signal to obtain an electromagnetic interference state parameter; according to the method, a layered compensation controller is constructed, the impedance parameters of the shielding layer are adjusted through a self-adaptive backstepping control algorithm, compensation control parameters are obtained, accurate adjustment of the impedance parameters of the shielding layer is achieved, and stability and effectiveness of electromagnetic shielding compensation are guaranteed.

The invention belongs to the technical field of artificial intelligence and high-performance computing, and particularly relates to a method for improving the reasoning solution and training speed of a deep operator network model. According to the method, multi-level optimization is carried out on the PI-DeepONet model, and the reasoning solving speed and the training speed of the PI-DeepONet model are improved. According to the method, the SGEMM operator is customized, and compared with the best single-precision matrix multiplication in a basic linear algebraic library of a CUDA (Compute Unified Device Architecture) computing platform, the SGEMM operator can obtain a speed-up ratio of 1.5 times at most in a common model size range of PI-DeepONet. A fusion operator is designed according to the special structure of the modified MLP used in the model, the speed-up ratio of the end-to-end reasoning speed of the model is more than two times, and the calculation time of a graphics processor can be shortened by 5.7 times at most. According to the method, data parallel is used for carrying out distributed training on the model, a communication concealment strategy is used, and the expandability is kept at 83%-85%.

The invention belongs to the field of high-performance computing, and relates to an integer parallel computing method and device based on distributed storage and computer equipment, and the method comprises the steps of collecting real-time resource indexes, dynamically identifying fault nodes, triggering task migration, and performing data verification and hard disk fault detection. The weight value of each node is calculated, the nodes are arranged according to the descending order of the weight values, and the nodes with high load capacity are selected to distribute tasks; dynamically distributing a data generation task to a computing node, executing parallel computing, and performing distributed storage on a result; obtaining an operand, converting the operand into a first-order tensor form of a basic operand, serializing tensor data, and sending the serialized tensor data to a parallel computing layer; distributing a search task to a computing node, retrieving storage data in parallel, reading effective data from a storage layer, and combining search results into a partial sum; and summarizing and then outputting. The system has dynamic resource management and fault-tolerant capabilities, and can realize efficient task allocation and load balancing.

The invention relates to the technical field of computer architecture and parallel computing, and discloses a parallel task scheduling algorithm for a heterogeneous multi-core processor, which comprises the steps of task modeling, resource mapping, dynamic load balancing, communication optimization, task scheduling decision and execution monitoring. Task allocation is adjusted in real time through dynamic load balancing, cross-core communication delay is reduced in combination with communication optimization, and an efficient task allocation sequence is generated by using an improved genetic algorithm. According to the method, the resource utilization rate and the task execution efficiency of the heterogeneous multi-core processor in a high-performance computing scene can be improved, meanwhile, the robustness and adaptability of an algorithm are enhanced, and the task allocation problem in a complex computing scene is effectively solved.

The invention discloses a low-code platform and Wasm high-performance computing integration system and method, and relates to the technical field of front-end development. In order to solve the problems that an existing low-code platform is limited in calculation performance and poor in security isolation performance, the scheme adopted by the invention comprises five modules: a description and registration module establishes a metadata structure for a Wasm module; the dynamic loading and asynchronous compiling module realizes loading as required and compiling during operation, and supports caching, version verification and hot replacement; the authority sandbox and resource isolation module constructs a security environment based on authority configuration to prevent illegal operation; the parameter binding and safety bridging module encapsulates a uniform interface to realize standardized interaction; the packaging and life cycle management module packages the module into a visual component, and supports full life cycle management. According to the method, high-performance, high-safety and visual integration of the Wasm module in a low-code platform is realized.

The invention belongs to the technical field of artificial intelligence and high-performance computing, and particularly relates to a neural network large model efficient reasoning method based on multiple GPGPUs. The method aims to solve the problems of high communication overhead, non-uniform load, low resource utilization rate, high data transmission delay and the like among multiple processors. Dividing a calculation task into a plurality of sub-graphs through static analysis and mixed granularity partitioning of a model calculation graph; distributing the sub-graphs to the optimal GPGPU based on a weighted cost function in combination with heterogeneous resource perception and a dynamic mapping strategy; a global pipeline scheduling plan is constructed by using communication topology perception, and calculation and communication overlap are maximized; data are loaded in advance through a host side hierarchical caching and asynchronous prefetching mechanism, and transmission delay is hidden; multi-stream concurrent execution and event-based lightweight synchronization are adopted on each GPGPU, so that waiting overhead is reduced. According to the method, the reasoning delay can be remarkably reduced, the throughput and the hardware utilization rate are improved, and the method has good adaptivity and expandability.

The invention discloses a quantum computer and super computer connection fusion method, which comprises the following steps of: constructing a quantum computer architecture and a super computer architecture, and realizing connection between the quantum computer architecture and the super computer architecture through a hardware layer; inputting the calculation data into a super computer, and performing task classification on the calculation data by utilizing an innovation fusion module to obtain a plurality of calculation tasks; utilizing an AI model to predict execution time and resource consumption of the plurality of calculation tasks on the quantum computer and the super computer respectively, and adjusting the distribution proportion of the plurality of calculation tasks on the quantum computer and the super computer; and transmitting the calculation data to the super computer and the quantum computer for classical calculation and quantum calculation according to the distribution proportion, and transmitting a calculation result back to a central node of the super computer to complete a calculation task. The invention relates to the field of quantum computing and high-performance computing, and solves the technical problem that the computing efficiency is low when a quantum computer and a super computer are used for computing in the prior art.

The invention provides a chip system and an access method, relates to the technical field of chips, and improves the data access performance of a high-performance computing system. According to the specific scheme, the chip system comprises a snoop filter, a plurality of processor cluster nodes and a plurality of memories, the processor cluster nodes are coupled through a bus, the snoop filter is coupled with the bus, the processor cluster nodes are in one-to-one correspondence with the memories, and the snoop filter adopts a unified directory format. The snoop filter is used for obtaining an access request initiated by the processor cluster node, and the access request comprises address information. The snoop filter is further used for determining an access mode of the access request based on the address information, wherein the access mode comprises a unified memory access mode and a non-unified memory access mode. The processor cluster node is to access the memory based on the access pattern and the access request. The embodiment of the invention is used for the process of accessing the memory by the processor cluster node.

The invention relates to the field of artificial intelligence, in particular to a deployment method and system for a large language model, and the method comprises the steps: (1) a service request end receives at least one piece of service request information, and stores the service request information in a service request message queue; (2) responding to a pre-filling stage calculation unit request and a load condition, and distributing service request information; (3) finishing the processing of the pre-filling stage to obtain at least one operation result; (4) the load balancer determines a task operation calculation unit in the stage according to the load condition of the calculation unit in the decoding stage; and (5) inputting the operation result of the pre-filling stage into the task operation calculation unit of the decoding stage, and outputting the result. The method has the advantages that the pre-filling stage and the decoding stage are deployed on a machine with high-performance computing power and a large memory respectively, load tasks are balanced, maximum hardware utilization is achieved, idle computing power is reduced, overall delay is reduced, throughput is improved, and expansibility and fault tolerance of the system are enhanced.

Memory has been playing a major role in the performance, scalability and applicability of General Compute systems, and more recently, in realizing Generative Artificial Intelligence (GenAI) and High-Performance Computing (HPC) systems that scale to thousands of GPUs, CPUs and special-purpose Accelerators. Embodiments herein disclose efficient software-defined protocol terminations and protocol translations utilizing Compute Express Link (CXL), including translations between CXL.mem and CXL.cache protocols. Also disclosed are CXL-based systems, Resource Provisioning Units (RPUs), and Memory Fabric Switches enabling dynamic memory pooling and sharing, host-to-host communication utilizing CXL.mem, CXL.cache and CXL.io, intent-based protocol translations, and optionally seamless interactions between CXL, UALink, NVLink, and / or Ethernet protocols, utilizing a broad range of semantics including IO, Cache, and Memory, optimizing memory access and reducing latency. Some embodiments also enable scalability, flexibility and security in high-performance architectures suited for data centers and next-generation computing environments.

The invention belongs to the related technical field of high-performance computing, and provides a memory architecture-oriented dual-precision general matrix multiplication optimization method and system in order to solve the problems of limited computing power and access efficiency and the like in the prior art. Decomposing the matrix into a plurality of sub-matrix blocks according to the slave core array topology; the slave core receives the sub-matrix blocks issued by the master core, divides the sub-matrix blocks into small sub-matrix blocks based on a uniform blocking rule, loads the small sub-matrix blocks to an independent buffer area of a local data memory based on a DMA double-buffer protocol, divides the small sub-matrix blocks in the buffer area into SIMD vectors according to the SIMD unit characteristics of the slave core, and sends the SIMD vectors to the slave core; vectorization calculation and caching operation are alternately switched according to an iteration period through different independent buffer areas; and after all the slave cores finish calculation, the master core collects results written back to the master memory by the slave cores to obtain a final operation result, and double breakthrough of calculation power and memory access efficiency is realized.

Memory has been playing a major role in the performance, scalability and applicability of General Compute systems, and more recently, in realizing Generative Artificial Intelligence (GenAI) and High-Performance Computing (HPC) systems that scale to thousands of GPUs, CPUs and special-purpose Accelerators. Embodiments herein disclose efficient software-defined protocol terminations and protocol translations utilizing Compute Express Link (CXL), including translations between CXL.mem and CXL.cache protocols. Also disclosed are CXL-based systems, Resource Provisioning Units (RPUs), and Memory Fabric Switches enabling dynamic memory pooling and sharing, host-to-host communication utilizing CXL.mem, CXL.cache and CXL.io, intent-based protocol translations, and optionally seamless interactions between CXL, UALink, NVLink, and / or Ethernet protocols, utilizing a broad range of semantics including IO, Cache, and Memory, optimizing memory access and reducing latency. Some embodiments also enable scalability, flexibility and security in high-performance architectures suited for data centers and next-generation computing environments.

The present disclosure herein addresses the problem of synthesizing a series of documents and extracting or summarizing meaningful information or content embedded as tacit knowledge in the series of documents. The embodiment of the present disclosure provides a system and method for tacit knowledge generation using large language model (LLM) in document synthesis. The method of the present disclosure performs intelligent document generation orchestrating a generative artificial intelligence solution workflow. In the present disclosure, tacit knowledge of subject matter experts in a knowledge base or in a series of documents is extracted. Further a content capturing the tacit knowledge is generated leveraging a large language models (LLMs) framework as the underlying architecture. The system of the present disclosure is artificial intelligence (AI) accelerated, cloud agnostic, latency defined, and security enabled.

The invention belongs to the technical field of artificial intelligence, and particularly relates to a GPU (Graphics Processing Unit) and NPU (Network Processing Unit) resource scheduling method for high-performance computing, which comprises the following steps of: waiting for a scheduling optimization module to call acquired resource condition data of GPU and NPU hardware accelerators; the task analysis module analyzes a to-be-executed AI calculation task, obtains task feature data and transmits the task feature data to the scheduling optimization module; the scheduling optimization module calculates an optimal task allocation scheme and transmits the optimal task allocation scheme to the dynamic scheduling module; the dynamic scheduling module monitors task execution conditions and resource changes in real time, dynamically adjusts a task allocation scheme according to feedback information, and feeds back the task allocation scheme to the scheduling optimization module; meanwhile, the dynamic scheduling module feeds back the change information of the resource condition data and the task execution condition to the resource monitoring module and the task analysis module respectively; according to the method, dynamic scheduling is carried out on heterogeneous hardware accelerators such as the GPU and the NPU, respective advantages are fully exerted, and the overall calculation performance is improved.

The invention discloses a direct memory access (DMA) communication device for a computing network convergence computing architecture and a working method of the DMA communication device. The DMA communication device comprises a DMA transaction processing module and a protocol conversion module; the DMA transaction processing module is used for analyzing related DMA read-write requests, realizing processing of the DMA read-write requests and receiving of response data of the DMA read requests and completing processing of interrupt requests at the same time, and the protocol conversion module is used for completing conversion of read-write requests between a DMA interface and an AXI interface and mapping of response states. The invention aims to realize efficient protocol conversion between AXI and DMA interfaces, avoid the problem of DMA read request starvation caused by resource competition and ensure the consistency of DMA data access so as to improve the performance of an accelerator in high-performance calculation and artificial intelligence application, reduce transmission delay and improve data transmission bandwidth and energy efficiency.

The invention provides a Cholesky decomposition heterogeneous parallel optimization method and system based on an SW architecture, and relates to the technical field of high-performance computing. The method comprises the following steps: performing sub-block division on a symmetric positive definite matrix based on a distributed parallel distribution scheme, and performing iteration to complete matrix decomposition; each sub-block is distributed to different processes through an MPI programming model, data exchange is carried out between the processes through asynchronous communication, and coarse-grained task-level parallel acceleration is carried out; performing two-stage parallel acceleration on four operations in Cholesky decomposition by utilizing the acceleration parallel characteristic of a master core and a slave core of the SW architecture; wherein for GEMM and SYRK operations, column vectors of a matrix are mapped to a slave core array, and columns are divided according to the number of slave cores; the calculation process is optimized through a double-buffering mechanism, vectorization operation and a loop expansion technology, and the parallel efficiency is improved; and for the TRSM operation, the TRSM operation is decomposed into a plurality of TRSV operations, the TRSV operations are allocated to the slave cores for parallel execution, and a circular reading and data broadcasting mode is adopted to reduce data dependence and realize efficient parallel calculation.

Embodiments for communicating using a switch configured to establish multiple types of communication routes. First and second upstream switch ports (USPs) communicate with first and second hosts according to first and second Compute Express Link (CXL) protocols, respectively. A downstream switch port (DSP) communicates with a device according to a third CXL protocol. The switch couples the first USP to the DSP via a first route traversing a single Virtual CXL Switch (VCS), and couples the first USP to the second USP via a second route traversing two VCSs. Optionally, the switch includes a Resource Provisioning Unit (RPU) coupling the two VCSs of the second route, terminating the first and second CXL protocols, and translating between CXL messages conforming to the first and second CXL protocols.

The invention belongs to a computing unloading strategy in the field of parallel and distributed high-performance computing, and particularly relates to a task computing unloading method based on MATD3 in vehicle-mounted edge computing, a task scheduling priority algorithm is introduced, and a new thought is provided for computing unloading of the Internet of Vehicles. The task priority is determined by considering the execution cost and the internal dependency relationship of tasks, optimization of the task unloading sequence is facilitated, the total processing delay of an application program is reduced, a multi-agent reinforcement learning method is adopted, especially a strategy based on MATD3 is adopted, multiple agents are cooperatively controlled, and the task unloading efficiency is improved. Complex factors such as competition of multiple vehicles for computing resources, task dependency, RSU limited computing resources and vehicle mobility are fully considered, the method can better adapt to the dynamic change environment of the Internet of Vehicles, the optimal unloading strategy of the vehicle tasks is determined, and therefore the unloading failure rate and energy consumption of the tasks in the system are minimized.

The invention discloses a communication method between graphics processors, a product, equipment and a medium, relates to the technical field of high-performance calculation and artificial intelligence acceleration, and is applied to a stand-alone system comprising a plurality of graphics processors and a central photoelectric hybrid switching chip constructed based on interconnection of an electric switching matrix and an optical switching matrix. The graphics processor is connected with the central photoelectric hybrid switching chip through an optical link and an electric link; the method comprises the following steps: performing data classification on to-be-transmitted data of a source graphics processor; if the to-be-transmitted data is a control flow, the source graphics processor is controlled to send the to-be-transmitted data to an electric switching matrix through an electric link, and then the to-be-transmitted data is routed to a target graphics processor in the graphics processors; and if the to-be-transmitted data is a data stream, the source graphics processor is controlled to send the to-be-transmitted data to the optical switching matrix through the optical link, and then the to-be-transmitted data is routed to the target graphics processor. Interconnection between graphics processors is optimized to improve communication efficiency between graphics processors.

The satellite-borne heterogeneous computing system comprises a CPU (central processing unit) module, an FPGA (field programmable gate array) module and an NPU (network processing unit) module, the CPU module is used for receiving instructions and telemetering polling of a satellite service computer, reading load scientific data received by the FPGA module, providing installation and operation environments for various types of universal application programs, and scheduling and controlling the NPU module; the FPGA module is used for providing external interface expansion, receiving load scientific data and sending the load scientific data to the CPU module, and is also used for providing a logic control function comprising SPI FLASH triple modular redundancy logic and barking reset; and the NPU module is used for performing high-performance calculation and providing a high-computing-power environment for the system. The system has high flexibility, reliability and universality, and can operate various computing software and neural network algorithms; the power consumption is low, and strict requirements of a satellite platform on power consumption can be met. And a plurality of systems are interconnected to form a distributed computing system, so that the performance is extremely high.

The invention relates to the technical field of high-performance computing resource management, and discloses a computing resource allocation method for a distributed supercomputing center. The method comprises the following steps: on the basis of obtaining real-time computing task and supercomputing center resource data and uniformly quantifying, integrally predicting resource requirements of future tasks; constructing a mixed integer linear programming model with the minimization of the total operation cost as a single target, wherein the total operation cost is the sum of the energy cost, the carbon emission cost, the data transmission cost and the SLA default penalty cost; solving the model by taking the time-varying electricity price, the green energy ratio, the resource capacity and the network parameters of each center as constraint conditions to generate an optimal resource allocation scheme; and then, by dynamically monitoring the resource state and the task progress, the model is triggered to resolve when the resource utilization rate is detected to be unbalanced or default risks, so that self-adaptive adjustment is realized. According to the invention, global collaborative resource allocation across super computing centers is realized, and operation economy, environmental sustainability and service reliability are considered.

The invention discloses a high-performance computing memory optimization method and system based on cache classification, and the method comprises the following steps: S1, dividing a physical memory page into different categories according to the number of cache groups mapped to a target cache, and distributing the divided categories to a target process running in the target cache; and S2, when the target process requests the physical memory page from the operating system, allocating the physical memory page of the same category to the target process based on the category corresponding relationship between the process and the physical memory page. According to the method, the problem of cache conflict among a plurality of processes under the condition of high CPU utilization rate is solved, so that the performance of the whole system is improved.

The invention relates to a calculation task execution method and device, equipment and a storage medium. According to the main technical scheme, the method comprises the steps of obtaining to-be-processed computing tasks, a preset mapping table and computing resource available information of computing nodes, performing topological sorting on the to-be-processed computing tasks according to a dependency relationship among the to-be-processed computing tasks to obtain a priority execution sequence of the to-be-processed computing tasks, and based on the priority execution sequence, a preset mapping table and the computing resource available information, determining a real-time execution sequence of the to-be-processed computing tasks, and executing the to-be-processed computing tasks through the first group of computing chips or the second group of computing chips according to the real-time execution sequence of the to-be-processed computing tasks. According to the method, high-complexity heterogeneous computing of computing chips of different types and different sources can be realized, high-performance computing and intelligent computing service scenes are supported, and compatibility of a high-performance computing related service system and a hyper-converged computing cluster is facilitated.

The invention relates to the technical field of interface impedance adjustment, and discloses an impedance matching adjustment method and device for an FPC high-performance computing chip interface. The method comprises: collecting impedance parameters of the FPC high-performance computing chip interface and establishing an impedance characteristic mathematical model; constructing a scalar differential equation group including an impedance change rate, a temperature change rate and a signal characteristic change rate, and solving the scalar differential equation group to obtain a dynamic compensation parameter matrix; adjusting and controlling the interlayer relative positions of an FPC multilayer structure, adjusting impedance gradient parameters in an interlayer transition region of the FPC multilayer structure, and obtaining initial impedance optimization data; inputting the initial impedance optimization data and historical temperature data into a recurrent neural network model to perform impedance matching parameter optimization calculation, and generating an impedance matching optimization parameter group. The invention improves the adaptability of the FPC high-performance computing chip interface to complex working conditions and improves the convergence speed of the impedance matching parameters.

The invention relates to the field of computer heat dissipation control, and discloses a high-performance computer system temperature regulation and control method which comprises the following steps: dividing a computer system into a plurality of hot areas and initializing thermodynamic parameters; collecting temperature, power consumption and process data in real time, identifying a burst process and constructing a dynamic heat capacity model; the heat capacity parameter and the heat dissipation coefficient are updated online through a recursive least square method; the multi-target weight is dynamically adjusted based on the temperature deviation degree and the heat capacity change rate, a distributed optimization model containing heat diffusion coupling constraints is established, and an optimal heat dissipation strategy is solved by adopting an improved ADMM algorithm; model prediction deviation is corrected through a double-loop control mechanism, and data updating circulation is triggered in combination with burst process marks and temperature out-of-limit events. According to the method, through a dynamic modeling, weight self-adaption and closed-loop control fusion mechanism, the temperature control precision and the system safety in a complex thermal coupling scene are remarkably improved, and meanwhile heat dissipation efficiency, noise suppression and energy efficiency balance optimization are achieved.

The invention provides an automatic SEM image analysis and process defect detection system based on a full database, and relates to the technical field of semiconductor manufacturing, the system combines self-adaptive feature extraction and density anomaly detection of a high-performance calculation unit through dynamic feature fusion (Sp1) of a multi-scale SEM image and a multi-channel acquisition device, and realizes automatic analysis of the SEM image. Precise classification of defect types and automatic identification of new defects are achieved, the feature range and the fusion weight are dynamically adjusted, traditional static detection limitation is broken through, adaptive analysis of process context is supported, the detection precision is improved to 98%, the misjudgment and missing judgment rate is reduced by 30%-50%, especially in advanced processes such as 3nm, the new defects can be rapidly identified, rules can be updated, and the method is suitable for large-scale popularization and application. The process research and development efficiency and the product reliability are remarkably improved, and the flexible and intelligent detection capability is provided for semiconductor manufacturing.