291 results about "Performance computing" patented technology

The invention belongs to the technical field of artificial intelligence and high-performance computing, and particularly relates to a neural network large model efficient reasoning method based on multiple GPGPUs. The method aims to solve the problems of high communication overhead, non-uniform load, low resource utilization rate, high data transmission delay and the like among multiple processors. Dividing a calculation task into a plurality of sub-graphs through static analysis and mixed granularity partitioning of a model calculation graph; distributing the sub-graphs to the optimal GPGPU based on a weighted cost function in combination with heterogeneous resource perception and a dynamic mapping strategy; a global pipeline scheduling plan is constructed by using communication topology perception, and calculation and communication overlap are maximized; data are loaded in advance through a host side hierarchical caching and asynchronous prefetching mechanism, and transmission delay is hidden; multi-stream concurrent execution and event-based lightweight synchronization are adopted on each GPGPU, so that waiting overhead is reduced. According to the method, the reasoning delay can be remarkably reduced, the throughput and the hardware utilization rate are improved, and the method has good adaptivity and expandability.

The invention belongs to the related technical field of high-performance computing, and provides a memory architecture-oriented dual-precision general matrix multiplication optimization method and system in order to solve the problems of limited computing power and access efficiency and the like in the prior art. Decomposing the matrix into a plurality of sub-matrix blocks according to the slave core array topology; the slave core receives the sub-matrix blocks issued by the master core, divides the sub-matrix blocks into small sub-matrix blocks based on a uniform blocking rule, loads the small sub-matrix blocks to an independent buffer area of a local data memory based on a DMA double-buffer protocol, divides the small sub-matrix blocks in the buffer area into SIMD vectors according to the SIMD unit characteristics of the slave core, and sends the SIMD vectors to the slave core; vectorization calculation and caching operation are alternately switched according to an iteration period through different independent buffer areas; and after all the slave cores finish calculation, the master core collects results written back to the master memory by the slave cores to obtain a final operation result, and double breakthrough of calculation power and memory access efficiency is realized.

The invention relates to the technical field of high-performance computing resource management, and discloses a computing resource allocation method for a distributed supercomputing center. The method comprises the following steps: on the basis of obtaining real-time computing task and supercomputing center resource data and uniformly quantifying, integrally predicting resource requirements of future tasks; constructing a mixed integer linear programming model with the minimization of the total operation cost as a single target, wherein the total operation cost is the sum of the energy cost, the carbon emission cost, the data transmission cost and the SLA default penalty cost; solving the model by taking the time-varying electricity price, the green energy ratio, the resource capacity and the network parameters of each center as constraint conditions to generate an optimal resource allocation scheme; and then, by dynamically monitoring the resource state and the task progress, the model is triggered to resolve when the resource utilization rate is detected to be unbalanced or default risks, so that self-adaptive adjustment is realized. According to the invention, global collaborative resource allocation across super computing centers is realized, and operation economy, environmental sustainability and service reliability are considered.

A container-based parallel computing system for executing high-performance computing (HPC) applications. The system leverages container technology to package the applications executed at the nodes in a cluster. To load and execute a job in the parallel computing system, containers are deployed in a cluster that include all the application resources and configuration information that the particular HPC application needs to execute. An event-driven batch scheduler may be used to dynamically allocate resources for executing multi-node jobs in the container-based parallel computing system, handling the coordination of resource allocation for the customer. The scheduler insures that jobs begin executing as fast as possible, and handles failure conditions such as partial scaling. Virtual network interfaces are attached to the containers that allow the containers to connect to and communicate with other containers in the cluster directly through the network interfaces of host machines using IP addresses provided by the virtual network interfaces.

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

This invention discloses a full lifecycle management system and method for scientific computing programs. The system includes a build environment subsystem and a production environment subsystem. The former provides computer resources for the build process of the scientific computing program throughout its lifecycle, while the latter provides computer resources for the testing and deployment processes. This invention, through a full lifecycle management method for scientific computing programs, operates on corresponding computing resources, encompassing a series of steps including querying, triggering scheduling, build execution, result distribution, and test deployment. It automatically generates the executable file of the scientific computing program and configures its runtime dependencies. Simultaneously, it automatically generates a corresponding description file recording the entire lifecycle process. Furthermore, based on version management of these description files and their sets, it achieves full lifecycle traceability and cross-platform migration and deployment of scientific computing programs in a high-performance computing environment.

The invention relates to the technical field of browser-side high-performance computing, in particular to a WebAssembly-based high-performance front-end audio and video processing method and system, and the method comprises the following steps: designing a modularized Wasm runtime container, constructing a zero-overhead memory interaction mechanism, and establishing a hardware adaptive scheduling engine; the method has the beneficial effects that dynamic loading of an audio and video algorithm is realized by designing a modularized Wasm runtime container, serialization overhead of communication between threads is eliminated by utilizing a shared memory mechanism, a hardware self-adaptive dynamic scheduling system is created, and finally three core objectives are achieved: execution efficiency close to native codes is provided in a pure browser environment; establishing a standardized processing pipeline without dependence of a third party; intelligent scheduling and elastic expansion and contraction of terminal heterogeneous computing resources are realized, and Web end infrastructure support is provided for professional audio and video applications.

The invention relates to the technical field of rail transit data processing, in particular to a rail transit data processing system adopting a high-performance computing power node board card, which is used for solving the problems that the existing rail transit data processing technology has obvious defects in a complex operation scene, the state prediction depends on a black box model, and the reliability is poor. Explicit modeling of physical constraints such as track curvature, gradient and speed limit is lacked, and real anomaly and model misalignment are difficult to distinguish; structured features and compressed time sequence data are fused through the rail traffic physical credible prediction module, the train operation stage is intelligently recognized, adaptive deep learning, time sequence Bayesian or reinforcement learning sub-models are dynamically called, high-precision state prediction is achieved, meanwhile, physical constraints such as the track curvature, the gradient and the speed limit are combined, and the reliability and reliability of the system are improved. And the causal consistency verification based on the mechanics principle is executed, so that the physical mismatch abnormity is effectively discriminated, and the prediction credibility, the abnormity identification accuracy and the operation and maintenance decision intelligent level are remarkably improved.

The invention discloses a decentralized high-performance multicast method and system based on Gossip and RDMA, and relates to the field of computer network communication. The method has better reliability, realizes zero-loss transmission of data packets through message de-duplication, timeout retransmission, ACK / NACK convergence and a dynamic topology adaptation mechanism, ensures data consistency, and solves the problem of insufficient reliability of traditional UDP multicast; the method has the advantages that the real-time performance is high, the delay is low, the throughput is high, the zero copy and kernel bypass characteristics of the RDMA and the batch processing mechanism of the MPMC are combined, the average delay is lower than 10 microseconds, the throughput in a large data packet scene reaches 374GB / s, and the low-delay requirements of high-frequency transaction, high-performance calculation and the like are met; the method has high expansibility, is based on a decentralized architecture of an improved Gossip protocol, does not need core node maintenance topology, supports dynamic joining or quitting of nodes, can adapt to large-scale cluster expansion, and solves the expansibility bottleneck of centralized multicast.

A data processing architecture controls data processing arbitration in a high performance computing system that includes one or more premises. Individual premises can include one or more server computers executing an instance of a local file system and including one or more temporary data storage devices. Individual instances of the local file system can access files stored in objects of a primary data store. Individual objects of the primary data store can be accessed using a common identifier indicating a storage location of the individual objects in the primary data store.

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and / or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

The invention provides a storage and calculation integrated structure and a chip, and belongs to the technical field of integrated circuits, and the storage and calculation integrated structure comprises at least one near storage core grain which is used for providing large-capacity storage; the in-memory computing unit is used for providing computing processing, and the near-memory core grains provide cache space for data and / or instructions processed by the in-memory computing unit; the at least one logic processing core particle is used for loading the data and / or instructions stored in the near memory core particle into the in-memory computing unit, and updating and storing the data and / or instructions processed by the in-memory computing unit into the near memory core particle; and the logic processing core particle is integrated with the near memory core particle and the in-memory computing unit through hybrid bonding and / or TSV (Through Silicon Via). The storage and calculation integrated structure is applied to high-performance calculation, the high-performance calculation requirement and the large-capacity storage requirement can be met at the same time, the high-performance calculation of the system is maximized, and support is provided for the development of the calculation power technology from the hardware structure.

The invention discloses an awareness perception quantum gravitational nerve acceleration unified computing platform and method based on formalized verification, and belongs to the field of high-performance computing, medical AI and quantum information processing. A quantum gravitational coupling neural processing unit (QGCNPU); a consciousness information integral calculation core (phi ICC); formalizing a receipt chain verifier (FRCV); and the mirror reflection symmetry correction module (MRSCM) is used for eliminating the continuous projection mistake and the discrete Boolean mistake through topological equivalence verification of a local observer and a global GodCam visual angle. The system adopts an FPGA + ASIC + quantum processor three-layer heterogeneous architecture, and supports real-time pathological modeling (precision gt; gt) of neurodegenerative diseases such as Alzheimer's disease, Parkinson's disease and ALS; 99.7%), drug target discovery (acceleration by 50 times) and consciousness state monitoring (time resolution lt; and meanwhile, the mathematical proving performance and the clinical auditing performance of the calculation process are ensured, and the requirements of the global 152 billion dollar neural science and technology market and the 89 billion dollar quantum calculation industry are met.

The invention provides a sparse matrix multiplication acceleration method based on a tensor processor, which relates to the field of high-performance computing, and comprises the following steps: carrying out block processing on a sparse matrix to obtain sparse matrix blocks matched with the register granularity of the tensor processor; performing block processing on the dense matrix to obtain dense matrix blocks; generating a matrix multiplication task set based on the sparse matrix block and the dense matrix block; and distributing the task set to a plurality of threads, controlling the plurality of threads to respectively call the tensor processors to execute matrix multiplication operation, and aggregating calculation results of the threads to obtain an output matrix. Compared with the prior art, the sparse matrix blocks are processed into the sparse matrix blocks matched with the register granularity of the tensor processor, the index coding and decoding overhead, the reconstruction overhead and the communication overhead of the sparse matrix are reduced, and therefore the operation performance of sparse matrix multiplication based on the tensor processor is improved. The system has the same beneficial effects.

The invention relates to the technical field of electric signal data analysis, in particular to a high-performance computing equipment power state analysis method and system based on modularization. The method comprises the following steps: in a modular assembly of a high-performance computing equipment power supply, collecting contact resistance change data of an equipment power supply connector through a distributed sensor network, and calculating a resistance change rate; carrying out partial discharge monitoring on a cable of an equipment power supply, and recording discharge capacity trend data; taking the resistance change rate and the discharge capacity trend data as equipment electric energy characteristic parameters; according to the invention, the accuracy, comprehensiveness, practicability and reliability of the power supply system are remarkably improved by accurately monitoring electric energy parameters, early warning and positioning mechanical faults, evaluating electromagnetic thermal coupling interference, comprehensively analyzing the power supply state and outputting a report.

The embodiment of the invention provides a multi-node parallel acceleration method, device and equipment based on a high-performance computing platform and an RoCE network and a medium, and relates to the technical field of cluster computing, and the method comprises the following steps: constructing a communication stack based on the RoCE network, and realizing an interconnection transmission network between nodes from a sending end to a receiving end; a computing task and a communication transmission task of the high-performance computing platform are executed through a CPU core binding technology of the high-performance computing platform; based on the transparent large page function, processing a memory allocation request initiated by an application program of an operating system and a request of the application program of the operating system for accessing a memory through a virtual address; before a main computing task of the high-performance computing platform starts, pre-processing is executed through multiple threads, open type multi-processing threads are started, the main computing task is executed through the multiple open type multi-processing threads, and a next round of pre-processing task is started in parallel. According to the scheme, parallel acceleration of multiple nodes in cluster calculation is realized.

The application discloses a kind of multi-node server network topology and energy consumption perception's task scheduling method, belong to data center and high performance computing technical field.It includes: constructing the weighted directed graph topology model including server node and switch node, the dynamic energy consumption weight function of link is defined;Establish the three-dimensional energy consumption and thermal interference evaluation model of node, introduce space thermal interference factor;Analysis the characteristics of task to be scheduled;Based on energy consumption potential field screening candidate node;Build the global energy consumption cost function including computing energy consumption, network transmission energy consumption and thermal coupling penalty energy consumption;According to the principle of minimum total energy consumption, select target node to execute scheduling and update topology state.The application solves the problem of splitting computing and network energy consumption, ignoring the space coupling effect of heat dissipation in the prior art by the fusion of network topology perception and multi-dimensional energy consumption model, and realizes the optimization of global energy consumption of data center.

This invention belongs to the field of flight control computer hardware architecture technology, specifically relating to a heterogeneous flight control core circuit and system. This invention integrates a microcontroller unit and an artificial intelligence coprocessor unit on the same printed circuit board, achieving data and command interaction through isolated high-speed interconnect channels. The microcontroller unit constitutes the safety control and real-time decision-making domain, used to execute safety-critical and hard real-time tasks, and to implement operational management and fault isolation for the artificial intelligence coprocessor unit; the artificial intelligence coprocessor unit constitutes the intelligent sensing and computing domain, used to execute computationally intensive and non-real-time critical tasks. This architecture achieves decoupling and collaboration between the safety domain and the computing domain at the hardware level, ensuring both high functional safety and determinism in flight control, while fully releasing the high-performance computing power required for intelligent sensing, thus meeting the dual requirements of advanced aircraft for highly reliable flight control and intelligent function expansion.

The invention discloses an AES encryption and decryption hardware implementation method based on an RISCV vector encryption and decryption expansion architecture, and belongs to the technical field of data encryption, and the method comprises the steps that an RISCV instruction set carries out vector expansion on AES encryption and decryption, in the AES encryption process, an initial round corresponds to a vaesz.vs instruction, a middle round corresponds to a vaesem.[ vv, vs] instruction, a final round corresponds to a vaesef.[ vv, vs] instruction, in the AES decryption process, the initial round corresponds to the vaesz.vs instruction, and in the AES decryption process, the middle round corresponds to the vaesef.[ vv, vs] instruction. The middle round corresponds to a vaesdm. [vv, vs] instruction, and the final round corresponds to a vaesdf. [vv, vs] instruction, so that the area of a chip can be reduced, the cost is reduced, the flexibility, modularization and extensible architecture design of hardware and software are enhanced, different platforms from embedded computing to high-performance computing can be easily adapted, and a solid foundation is provided for evolution and customization of a future cryptographic algorithm; and the encryption processor architecture is promoted to develop towards a more efficient, more open and more customizable direction.

1. The name of the design product: intelligent server. 2. The use of the design product: the design product is used in high-performance computing, intelligent analysis and security industry applications. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view 1.

The application relates to the field of high-performance computing, and provides an HPC job power consumption prediction method and system based on power consumption curves and script information. The method comprises the following steps: obtaining a first similarity value based on historical job power consumption curve data; obtaining a second similarity value based on historical job script information data; assigning weights to the first similarity value and the second similarity value according to requirements, calculating a weighted sum, obtaining a comprehensive similarity value, and constructing a similarity adjacency matrix in this way; dividing HPC jobs into different categories according to the similarity adjacency matrix on the principle of maximizing a module degree index; training different neural network models based on historical data in different categories after the division, obtaining trained neural network models; matching a historical job category similar to a target HPC job, and using the neural network model of the historical job category to predict script information data of the target HPC job to obtain a prediction result.

This invention discloses a method and apparatus for network traffic load balancing scheduling in a multi-node high-performance computing cluster, comprising three parts: network load detection, load estimation, and balancing decision. ArCa implements all parts on the host machine, requiring no modifications to the multi-node high-performance computing cluster network. Hosts send probe packets to each other to obtain the mapping relationship between paths and 5-tuples, as well as the path load. This information forms a network load table, on which ArCa estimates the short-term network load. Through estimation, the host makes a traffic plan decision and selects a path to send messages with the help of a skip flow algorithm. Each module is a separately running process that exchanges information through inter-process communication (such as MMAP), thereby improving the overall concurrency of the mechanism and enhancing its reaction speed and decision-making efficiency.

The invention provides a distributed isomerism-based polymer chain automatic construction and stable conformation generation method, belongs to the technical field of computational chemistry and high-performance calculation, and aims to solve the problems that the efficiency is low and the stability is poor due to the fact that polymer chain segment stable conformation calculation depends on conventional experience inference and experimental means verification. The method comprises the following steps: obtaining task information from a message queue, and scheduling tasks according to node affinity; analyzing a monomer PSMILES and a topology rule, and identifying an anchor atom and a leaving group; calculating an initial conformation of the monomer based on a specified force field type, and calculating atomic charge distribution; carrying out registration according to the anchor points, combining redundant atoms, and splicing the redundant atoms into an initial chain segment with a specified length; automatically generating an input file, and verifying constraint conditions; obtaining a stable chain segment conformation; calculating rigid body transformation from a monomer to a chain; and verifying a division result, completing task callback, and uploading an output to a distributed storage platform.

Compute-centric message passing interface (C2MPI) provides a hardware-agnostic message passing interface for heterogeneous computing systems. Hardware-agnostic programming with high performance portability is envisioned to be a bedrock for realizing adoption of emerging accelerator technologies in heterogeneous computing systems, such as high-performance computing (HPC) systems, data center computing systems, and edge computing systems. The adoption of emerging accelerators is key to achieving greater scale and performance in heterogeneous computing systems. Accordingly, embodiments described herein provide a flexible hardware-agnostic environment that allows application developers to develop high-performance applications without knowledge of the underlying hardware.

Systems and methods for supporting heterogeneous and asymmetric dual rail fabric configurations in a high performance computing environment. A method can provide, comprising at one or more computers each including one or more microprocessors, a plurality hosts, each of the plurality of hosts comprising at least one dual port adapter, a private fabric, the private fabric comprising two or more switches, and a public fabric, the public fabric comprising a cloud fabric. A workload can be provisioned at a host of the plurality of hosts. A placement policy can be assigned to the provisioned workload. Then, network traffic between peer nodes of the provisioned workload can be assigned to one or more of the private fabric and the public fabric in accordance with the placement policy.

The present invention relates to a computing and archiving research environment that uses multi-data integration between different information or data with high requirements for data storage and high performance computing. The invention provides a platform for easy storage, analysis and sharing of different scientific data by providing different service combinations such as high performance computing (HPC), scientific clouds and data archiving.

A gateway log analysis and abnormal access co-processing method comprises the steps that multi-dimensional log analysis and visualization processing are conducted on a gateway log, and the dimensions comprise a client IP, access time and access service; based on the gateway access log, performing statistics and correlation analysis on the access request of the user by adopting a machine learning method so as to extract user attributes, and dynamically adjusting the access permission of the corresponding user according to the user attributes; based on the multi-dimensional analysis result and the user attribute, whether the access is abnormal access is judged, and when the access is judged to be abnormal access, blocking or limiting measures are automatically executed. According to the method, blocking or other limiting measures can be automatically taken for abnormal access in a high-performance computing environment, resource waste is avoided, normal operation of services is guaranteed, and the safety and stability of a system are improved.

The invention discloses a job scheduling method and system in the technical field of high-performance computing cluster resource management, and aims to solve the problems that in the prior art, if multiple different granularity scheduling requirements need to be met, multiple sets of clusters need to be deployed, each cluster selects one scheduling strategy for deployment, different cluster resources cannot communicate with one another, and the scheduling efficiency is high. And independent maintenance is needed. The method comprises the following steps: acquiring a resource use state of each node, and constructing a global resource view according to the resource use state of each node; obtaining a job queue state, and determining a working strategy of each node according to the global resource view and the job queue state; obtaining an operation state and a current strategy of each node; according to the method, the same cluster can support two resource allocation granularities at the same time, meanwhile, the working strategy of each node can be determined and switched according to the global resource view and the job queue state, and allocation of node resources is optimized.