159 results about "Mask" patented technology

Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

A system and method for masking a boot sequence by running different code on each processor of a multiprocessor system are provided. With the system and method, one of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. The masking code executed by each of the non-boot processors may be different from each other and may be randomly selected from a plurality of masking code sequences stored in a masking code storage device. Each execution of masking code on each of the non-boot processors may generate a different electromagnetic and/or thermal signature such that none of the processors appear to be unique from an external monitoring perspective.

Apparatus and method for performing hierarchial type mask encoding and data transformation includes locating a data source, loading the data source into a temporary storage, encoding heuristics for buffer transformation, and delivery of data for transformation and scalar type encoding, reduction, compression, iteration, type extension and versioning if required.

The invention discloses a mask method and a mask device for an SM4 algorithm. The mask method comprises the following steps: acquiring an inputted masked plain text, a random mask and round keys; carrying out a first round operation of a round function on the masked plain text, the random mask and a first round key in the round keys, to obtain a first round ciphertext and a first round mask; carrying out a second round operation of the round function on the first round ciphertext, the first round mask and a second round key in the round keys, to obtain a second round ciphertext and a second round mask, so as to realize N rounds of operation of the round function in turn; and carrying out an XOR operation an N round ciphertext and an N round mask outputted from the N round operation, wherein the operation result is taken as an output of the SM4 algorithm. Namely, except for the first round operation in the N rounds of operation of the round function, masks required for each round operation are all obtained by the output of the last round operation next to the current round operation, and therefore a demask on an intermediate value of the N rounds of operation is not required by adopting the technical solution disclosed by the invention, so that a resistance to an energy attack is realized.

Embodiments relate to branch prediction preloading. A method for branch prediction preloading includes fetching a plurality of instructions in an instruction stream, and decoding a branch prediction preload instruction in the instruction stream. The method also includes determining, by a processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction, and determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction. The method further includes identifying a mask field in the branch prediction preload instruction, and determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field. Based on executing the branch prediction preload instruction, a branch target buffer is preloaded with the address of the predicted branch instruction, the branch instruction length, and the predicted target address associated with the predicted branch instruction.

The present invention discloses a method and a system for link list encoding. The link list coding method includes steps below: S102. A reference link list is compared with a current link list; S104. It is necessary to add/delete bit mask code, select an encoding method according to the comparison above and utilizes the selected encoding method to encode added/deleted bit mask code in the current or reference link list. The present invention greatly reduces quantity of element comparison between the current link list and the reference link list, improving encoding efficiency and enhances module reusability in a proposal of deletion at first and then addition by making functions of calculating added/deleted bit mask code, etc. independent.

The invention discloses a semantic comprehension model training method and device, computer equipment and a storage medium. The method comprises the steps of obtaining a total word sequence corresponding to a training text from a training set; randomly selecting a preset number of continuous word vectors from the total word sequence, replacing the continuous word vectors with a mask sequence to obtain an input word sequence, and taking the preset number of continuous word vectors as a test output word sequence; inputting the input word sequence into an encoder-attention-decoder model for training to obtain a prediction output word sequence; according to the difference between the prediction output word sequence and the test output word sequence, adjusting model parameters of the encoder-attention-decoder model to reduce the difference; and returning to input the input word sequence into the encoder-attention-decoder model for training to obtain a prediction output word sequence, continuing training, and stopping training until a preset training stop condition is met to obtain a semantic understanding model. According to the invention, the understanding accuracy of the computer to the natural language is improved.

The invention relates to a mask exposure offset detection method, a mask exposure offset detection device, a computer and a storage medium. The method comprises the following steps: acquiring first position parameters of two sides of a first register guide, and acquiring second position parameters of two second register guides corresponding to the first register guide, wherein the first register guide is located between the two second register guides; and calculating the offset according to the two first position parameters and the two second position parameters. The two first position parameters and the two second position parameters are obtained to calculate the offset, so the detection accuracy and the detection efficiency of the mask exposure offset are effectively improved.

An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

The invention discloses a comprehensive protection method for resisting side channel and fault attacks, which comprises the following steps of: 1) for a target algorithm to be protected, constructingan algorithm which is the same as the target algorithm as a redundancy algorithm of the target algorithm; respectively constructing the same d-order threshold protection scheme for the target algorithm and the redundant algorithm thereof, wherein the same d-order threshold protection scheme is used for protecting the d-order side channel attack; 2) carrying out exclusive OR on the output of the target algorithm and the output of the redundant algorithm, then carrying out multiplication mask operation on the output of the target algorithm and a random number, and protecting the multiplication operation by adopting a threshold implementation technology; 3) carrying out exclusive OR on the processing result of the step 2) and the d-order threshold implementation structure of the target algorithm or the d-order threshold implementation structure of the redundant algorithm to obtain a result, and taking the result as a final output result of the target algorithm. The method can resist faultsensitivity attacks not based on ciphertext, differential fault attacks based on ciphertext and side channel attacks.

Embodiments of this disclosure enhance the error detection performance of parallel polar encoding by cross-concatenating parity bits between segments of information bits transmitted over different sets of sub-channels. In one embodiment, a first segment of information bits is transmitted over a first set of sub-channels, and at least a second segment of information bits, and a masked parity bit, are transmitted over a second set of sub-channels. A value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits. The bitwise combination may be a bitwise AND, a bitwise OR, or a bitwise XOR of the respective parity bits.

The present invention relates to a method secured against side channel attacks performing an arithmetic operation of a cryptographic algorithm mixing Boolean and arithmetic operations, wherein said method is performed by a cryptographic device comprising a processing system having at least one hardware processor, and said operation has a first value (x) and a second value (y) as operands, comprising:—obtaining (S1) a first masked value (x′), a second masked value (y′), a first Boolean mask (r_x), a second Boolean mask (r_y), said first masked value (x′) resulting from masking said first value (x) by said first Boolean mask (r_x) by performing a Boolean exclusive OR (XOR) operation between said first value (x) and said first Boolean mask (r_x), and said second masked value (y′) resulting from masking said second value (y) by said second Boolean mask (r_y) by performing a Boolean exclusive OR (XOR) operation between said second value (y) and said second Boolean mask (r_y),—performing (S2) in any order a plurality of computing steps combining values among said first masked value (x′), said second masked value (y′), said first Boolean mask (r_x) and said second Boolean mask (r_y) to obtain a boolean masked result equal to the result of the arithmetic operation having said first value (x) and said second value (y) as operands, masked by a third boolean mask (r_x xor r_y) resulting from performing said Boolean exclusive OR (XOR) operation between said first Boolean mask (r_x) and said second Boolean mask (r_y) ((x+y) xor (r_x xor r_y)), wherein said computing steps perform Boolean exclusive OR (XOR) operations or arithmetic operations between said values without disclosing any information relative to the first and second values and, wherein said computing steps are executed by the hardware processor by performing a constant number of elementary operations whatever the bit-size of said first and second values,—outputting (S3) said boolean masked result of the arithmetic operation between said first value (x) and said second value (y).

The invention relates to the technical field of artificial intelligence, and discloses a soft mask-based text error correction model training method and device, a soft mask-based text error correctionmodel recognition method and device, computer equipment and a computer readable storage medium. The method comprises the steps of obtaining a to-be-modified text, and converting the to-be-modified text into word vector information of each word; training a preset soft mask language model according to the word vector information of each word to obtain a corresponding loss function; updating model parameters of the preset soft mask language model based on a loss function, and determining whether the preset soft mask language model is in a convergence state or not; if it is determined that the preset soft mask language model is in the convergence state, generating a corresponding text error correction model, and processing words are through soft masks, so that under the condition that a largenumber of training expectations are not needed, the training duration of the model is shortened, data is fitted, and the accuracy of the model is improved.

An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby generating a shifted operand. The register is coupled to the shift post processor to transfer a shift carry operand stored in the register to the shift post processor, and coupled to the shifter to store the shifted operand after any transfer of the shift carry operand. The shift post processor is coupled to the shifter and the register to process the shifted operand to generate an output based on at least a control signal and a mask field. The shift post processor comprises a decoder to decode the offset parameter into the mask field, the mask field having a plurality of mask bits, each of the mask bits corresponding to a bit position of the shifted operand.

An apparatus (100, 200) and method (160, 270) relate generally to generation and checking of a quaternary pseudo random binary sequence ("QPRBS"). In an apparatus (100), there is a pseudo random binary sequence ("PRBS") generator (10) configured to receive a seed (111 ) of a PRBS (14) to be generated. A mask generator (110) is configured to generate a mask output (115) corresponding to the PRBS (14). The PRBS generator (10) and the mask generator (110) are both configured for sequential operation with respect to one another. A masking circuit (117) is configured to receive the mask output (115) and the PRBS (14) to bitwise mask the PRBS (14) with the mask output (115) to generate the QPRBS (105).

The invention belongs to the technical field of image processing units, and particularly relates to a mask operation method of an explicit independent mask register in a GPU (Graphics Processing Unit), which comprises the following steps: S1, each GPU hardware thread can access respective eight 128-bit wide independent mask registers, and the eight 128-bit wide independent mask registers are recorded as m0-m7; according to the mask operation instruction of the explicit independent mask register in the GPU, each hardware thread in the GPU can access respective eight 128-bit wide independent mask registers, and four groups of mask operation instruction users can use the mask operation instruction to realize reduction operation, extension operation, logic operation and data movement among universal vector registers of the mask register respectively; the instruction can realize the generation of a branch mask in condition control, and meanwhile, the mask value is solved, so that the instruction transmitting process in the programmable core is optimized, invalid operand reading and pipeline operation execution are avoided, and the programmable power consumption is reduced.