296 results about "Mask" patented technology

The invention relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata, and calculating to generate a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model, and outputting an initial adjacent matrix; calling a feedback suppression mask matrix generated based on a historical operator utility state, and executing bitwise logic AND operation with the initial adjacent matrix to generate a corrected effective topological matrix; the matrix is analyzed, a logic operator function pointer is dynamically indexed in an instruction cache, and a directed acyclic execution linked list is constructed; according to the method, redundant logic nodes in AI prediction are definitely eliminated through a bit operation mask mechanism based on historical feedback, and deterministic convergence of processing delay and optimal matching of computing power resources are achieved.

The invention provides a data processing method and device, electronic equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring to-be-processed data and a sparseness threshold set of a data processing model; inputting the to-be-processed data into the data processing model, and performing multi-round iterative processing on the to-be-processed data through the data processing model to obtain a first model output matrix; wherein during at least one round of iterative processing, a mask matrix is determined based on a first activation feature vector output by the activation layer and a sparsity threshold value, and the mask matrix is used for performing sparse calculation during the current step of iterative processing and multiple steps of iterative processing after the current step; and determining a data processing result of the to-be-processed data based on the first model output matrix. According to the invention, the calculation efficiency of the data processing model can be improved.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating an output sequence that includes a respective token selected from a vocabulary of tokens at each of multiple output positions. In one aspect, one of the methods includes obtaining an initial output sequence, the initial output sequence comprising a mask token at each of at least a subset of the multiple output positions; repeatedly performing the following at each of multiple update iterations: obtaining an intermediate representation of the output sequence; generate a diffusion model output that comprises, for each of the multiple output positions, a respective score for each token in at least a subset of the vocabulary of tokens; determining, for each output position in the output sequence that is occupied by a mask token, a masked probability; selecting a subset of the multiple output positions; and generating an updated intermediate representation.

Systems and methods related to efficient compression instruction handling in a processing pipeline are disclosed herein. A processing pipeline may accept a mask vector from a first register, the mask vector including a set of set bits, and may accept a payload from a second register. The processing pipeline may determine a set of prefix sums for a set of portions of the mask vector by applying the portions to a set of adders in parallel to add the set bits independently for each of the portions. The processing pipeline may determine a set of indexes for the set bits, with respect to the mask vector, in parallel, using the set of prefix sums and the set of portions of the mask vector. The processing pipeline may store a set of identified values from the payload, as identified by the set of indexes, in at least one destination register.

The invention discloses an automatic code defect repairing method based on a code attribute graph and a large model, which comprises the following steps: collecting a code sample, analyzing a source code, generating the code attribute graph fusing an abstract syntax tree, a control flow graph and a data flow graph, and then carrying out dynamic pruning according to node importance calculated based on node degrees, PageRank and data propagation dependency, so as to obtain a large model; key nodes are reserved to improve the graph learning efficiency; extracting features of the optimized graph through GAT, introducing multi-scale coding, and generating a graph embedding vector; in combination with node importance, high-value Tokens are screened, semantic embedding of structure perception is carried out, and more accurate text representation is obtained; generating a comprehensive feature by fusing the image and the text vector, and then inserting a mask at a position with weak dependence or high risk; performing fine tuning optimization on the mask position; and inputting the comprehensive features and the mask source codes into a pre-training language model to generate patches, performing multi-task evaluation and reordering, and selecting an optimal patch to complete repair.

The embodiment of the invention provides a processor core, a processor and a method for the processor. The processor core includes a processing pipeline configured to rename and execute a first instruction including at least one of a first architectural register and a second architectural register, and includes: a first type of physical register configured to be mapped by the first architectural register and configured to store a first type of data; the first type of physical register is configured to be mapped by the first architecture register and configured to store data of a first type, the second type of physical register is configured to be mapped by the second architecture register and configured to store data of a second type, the first architecture register comprises a vector architecture register, the data of the first type stored by the first type of physical register comprises vector data, and the second architecture register comprises a mask architecture register; the second type of data stored in the second type of physical register comprises mask data. The processor core may mitigate processing pipeline stagnation and increase less area.

The invention relates to the technical field of artificial intelligence, and relates to a large language model reasoning optimization method, system and device for resource-constrained equipment, and a medium. The method comprises the following steps: establishing a resource budget, acquiring video memory parameters of equipment, including a total available video memory and a current available video memory, and setting a memory total budget of a reasoning session; evaluating memory requirements, including static calculation and dynamic calculation; calculating a total memory demand, and if the total memory demand is greater than the total memory budget, starting an iterative optimization sub-process; and loading the configuration meeting the budget, and executing speculation decoding through the optimized attention mask, which comprises the following steps of: generating a candidate lexical element sequence in parallel based on a mask structure, verifying the candidate sequence in batches and accepting or rejecting lexical elements, and updating a confirmed sequence and key value cache. Through a collaborative optimization strategy, the reasoning speed, memory occupation and generation quality are intelligently balanced, so that efficient and stable large-model speculation decoding reasoning is realized on equipment with limited memory.

The invention relates to the technical field of artificial intelligence, in particular to an operation method and an arithmetic unit based on a Point data format.The method comprises the steps that sign bits, exponential expansion bits, mantissa bits and exponential bits of the Point data format are obtained, all the positions of the Point data format are preprocessed, a bit width distribution priority rule is defined, and a bit width distribution priority rule is obtained; multiplying the two mantissa bits obtained by decoding to obtain a mantissa product and a mask sequence; determining a prepositive zero number of the mantissa product according to the mask sequence, and performing unified logic shift on the mantissa product; the method comprises the following steps: carrying out shift on a mantissa part, carrying out rounding operation on the shifted mantissa part, converting a mantissa product into a fixed-point number format according to a sign bit, an exponential expansion bit and an exponential bit, carrying out additive operation based on the fixed-point number, and outputting an accumulation result. The circuit area and power consumption are reduced, complex time sequence control is not needed, and logic resource consumption is reduced.

The invention provides a verification code verification method and device, equipment, a medium and a program product, and aims to solve the problem that an automatic script in the related technology cannot realize automatic testing of verification of a verification code of a rotary sliding block. The method comprises the steps of performing separation processing on a rotating main body and a target pattern in a verification code image to obtain a main body binary mask corresponding to the rotating main body and a target binary mask corresponding to the target pattern; based on the main body binary mask and the target binary mask, a target angle difference between the rotating main body and the target pattern is calculated, and the target angle difference is used for indicating the rotating main body to rotate to a rotating angle matched with the target pattern; generating a rotation track based on the target angle difference by using a slow motion function, wherein the rotation track comprises random disturbance and a random pause point; and controlling the rotating main body to rotate based on the rotating track to obtain a verification result. According to the invention, automatic testing of verification of the rotary sliding block verification code can be realized.

A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.

According to one embodiment, a method for performing a modular decomposition according to a decomposition parameter is described, comprising: representing the number as a sum of a first input number portion and a second input number portion modulo the modulo, calculating a reduced first input number portion by subtracting one from the first input number portion if it is not zero, calculating a division result of the first portion by integer division of the reduced first input number portion by the decomposition parameter, calculating a division result of the second portion by integer division of the second input number portion by the decomposition parameter, calculating a candidate value for the low-bit component, and, if the candidate value for the low-bit component is greater than or equal to the decomposition parameter,Determining the high-bit component by adding one to the sum of the division result of the first part and the division result of the second part.

The invention provides a multi-modal large model modal missing data complementing method, and relates to the technical field of data processing, the method comprises the following steps: 1, carrying out missing value detection and coding processing on multi-modal input data, analyzing the correlation between internal characteristics of the data, generating structured characteristic representation through characteristic recombination, and carrying out data processing on the structured characteristic representation; generating a feature calibration parameter by combining the correlation between the local features, and obtaining a numeric feature vector and a mask matrix of each mode; step 2, inputting the numeric feature vector and the mask matrix into a feature fusion model, analyzing a context dependency relationship in a mode and between modes, and performing rotation correction on an ellipse feature by calculating a principal axis parameter of a feature distribution ellipse to generate a preliminarily corrected fusion feature representation; according to the method, through feature distribution ellipse correction and global context retrieval, the accuracy and intelligence of multi-modal missing data complementation are improved.

The invention relates to the technical field of electric digital data processing, and discloses a data processing system for message management, which comprises a look-ahead buffer unit for maintaining a sliding window with variable window size parameters and pre-reading a message sequence; the mapping logic circuit is used for converting the resource identifier into a resource request mask; the state register is used for storing a global occupancy bitmap for representing resource occupancy; the scheduling controller is used for distributing messages according to bit operation results, counting bitmap setting quantity based on the population counting instruction to generate a resource saturation index, and then adjusting window size parameters in a negative feedback mode. The resource contention entropy value is directly sensed by utilizing a hardware instruction, nanosecond-level self-adaptive breathing control of a scheduling window is realized, and the service life of the scheduling window is prolonged. The problem of physical computing power collapse caused by bitmap scanning jitter in a high-concurrency scene is solved.

The invention discloses a side channel analysis method and device, equipment, a storage medium and a program product, and the method comprises the steps: obtaining a side channel segment related to polynomial multiplication of a secret key in mask-protected Kyber algorithm side channel data, and inputting the side channel segment into a Hamming weight classification model, the Hamming weight prediction value of the polynomial multiplication operation output result is obtained, and the Hamming weight classification model is obtained by adopting public stage data training of mask-protected Kyber algorithm side channel data; generating a candidate value set of different mask shares related to the same key coefficient according to the Hamming weight predicted value; screening out a target key coefficient from the candidate value set; and under the condition that the target key coefficient is successfully matched with the real key, determining that the side channel vulnerability that the key is stolen exists in the Kyber algorithm protected by the mask.

The invention relates to the technical field of processor hardware design, and discloses an ultra-wide RISC-V long vector processor, which comprises a 64-bit scalar RISC-V core and a plurality of vector clusters, wherein each vector cluster comprises an instruction dispatcher and an instruction scheduler, the instruction dispatcher receives vector instructions sent from the scalar core and distributes the instructions to idle processing channels, and the instruction scheduler controls the execution sequence of the instructions in time; each channel is connected with the mask unit, the sliding unit and the vector read-write unit through the full-interconnection crossbar switch, and the full-interconnection crossbar switch and the mask unit carry out conditional execution on elements in a vector instruction based on the mask register. According to the method, the long vector can be quickly and efficiently calculated, the expandability problem of a full interconnection structure is solved by adopting a special layered pipeline interconnection structure, and then long vector support can be carried out on an extended vector processor architecture.

The invention discloses a data layout optimization method and device applied to NPU code compilation and a medium. The method comprises the steps that an intermediate representation IR input by an upper layer is split into an operation type OP and an operand, and the operand input by the upper layer is divided into logic data and a logic mask; converting the logic data of the upper layer into data vector representation of the abstraction layer, and converting the logic mask of the upper layer into mask vector representation of the abstraction layer; obtaining a corresponding bottom hardware instruction capability according to an operation type OP input by an upper layer, and performing legalization operation on the operation type OP; and performing legalization processing on the converted abstract data vector type representation and mask vector representation according to the target hardware capability, performing instruction mapping on the processed abstract instruction according to the underlying hardware pair operation type OP, and generating a target LLVM instruction compatible with the underlying hardware. Register layout abstraction and conversion can be carried out on the NPU code under mixed precision input, and the utilization efficiency of the NPU bottom layer register is improved.

The invention discloses a matrix multiplier, a chip, electronic equipment, a data processing method, a computer readable storage medium and a computer program product, and belongs to the field of artificial intelligence. The matrix multiplier comprises a multiplier array, a data preprocessing module and an accumulator; the multiplier array is configured to perform multiplication operation on an input first matrix and a second matrix; the data preprocessing module is configured to preprocess the third matrix to obtain a mask matrix; the accumulator is configured to add the multiplication result of the first matrix and the second matrix and the mask matrix; wherein the first matrix is an M * K matrix, the second matrix is a K * N matrix, the third matrix is an M * N matrix, and M, N and K are all integers greater than or equal to 1. According to the method, the mask process is fused into the matrix multiplication operation, so that the matrix multiplication operation and the mask adding operation can be synchronously carried out, and the calculation rate of the Attention (attention) operation is effectively improved.

The embodiment of the invention provides a program conversion method and a compiling device, and relates to the technical field of computers, in the method, an IR file of a GPU program is obtained to serve as a to-be-converted file, for a function parameter of any function in the to-be-converted file, the function parameter is converted into a function parameter matched with a CPU, and the converted parameter is obtained. And determining the IR statement having data dependence with the converted parameter as a statement to be adapted. And for any statement to be adapted, adjusting the statement to be adapted based on the parameter type of the converted parameter and the thread execution mask of the CPU. And compiling the adjusted to-be-converted file to obtain an executable file adaptive to the CPU. The GPU programs written by different high-level languages can be converted into the IR file, so that the conversion is carried out from the dimension of the IR file, and the support for different high-level languages can be realized. Therefore, the limitation is lower.

The invention relates to the field of source code vulnerability detection technologies and the like, and discloses a code semantic alignment method based on an EMA Teaser-Student structure, which effectively realizes that anonymized codes still have the same representation capability as original codes on the premise of not exposing sensitive information, so that the accuracy and the robustness of downstream tasks such as vulnerability detection and the like are remarkably improved, and the reliability and the reliability of the code semantic alignment method are improved. Comprising the following steps: constructing a teacher model and a student model which have the same structure but independent parameters, and uniformly adopt a dual-module architecture of an encoder module and a Transform backbone network; original code samples are extracted from the open source code library or / and the vulnerability data set, and then anonymization operation is executed on the original code samples; the student model processes an anonymized code sample obtained after anonymization operation, and two types of output semantic representations of Mask frame-level embedding and global embedding are generated; the teacher model processes an original code sample and generates two types of output semantic representations of frame-level embedding and global embedding of an original semantic representation.

The invention relates to a mask generation method and device, computer equipment, a readable storage medium and a program product. The method comprises the following steps: after obtaining first matrix data, loading the first matrix data to a first memory in response to a target access instruction to adjust a data arrangement mode of the first matrix data to obtain second matrix data; determining a multiplication result matrix of the second matrix data, and statically distributing the multiplication result matrix to a second memory corresponding to the corresponding calculation thread; and determining a mask register according to the thread identifier and the mask boundary of the calculation thread. In the process of loading the first matrix data to the first memory, the complex high-dimensional tensor first matrix data is adjusted into a regularly linearly arranged two-dimensional matrix, so that optimization and recombination of data layout are realized, a large number of access instructions across calculation units are prevented from being generated during data access in the mask calculation process, and the data access efficiency is improved. The utilization efficiency of the memory broadband is improved, and the overall calculation performance of the chip is improved.

The invention provides an RISC-V vector data loading instruction processing method and a processor, and relates to the technical field of processors. When a vector loading instruction is transmitted, memory access address calculation and memory access can be started in advance only by making a source operand ready, and waiting for an old value of a target vector register is not needed, so that transmission blocking caused by dependence of the old value is avoided; by temporarily storing loaded data in a vector data buffer area, memory access operation and subsequent merging write back are decoupled, and memory access delay and old value ready waiting time are overlapped; and when the instruction becomes the oldest to-be-written-back instruction and an old value is ready, the merging unit merges new and old data element by element according to the mask and vector configuration to ensure correct implementation of RISC-V vector extension complex semantics. On the premise of not influencing the function correctness, the memory access delay is effectively hidden, the instruction level parallelism is improved, and the processing efficiency of the vector loading instruction is remarkably improved.

The invention provides a chromosome instance segmentation method and system based on banding coding assistance, and the method comprises the steps: extracting chromosome key points through a multi-scale neural network, and obtaining a skeleton according with a topological structure through key point screening and curve fitting; a plurality of decoupling schemes are enumerated by calculating skeleton cross information, chromosome banding codes of all the schemes are matched with a standard coding library, and the optimal scheme is selected with the minimum editing distance; the optimal decoupling scheme and the multi-scale features are fused, the chromosome segmentation precision is improved through a segmentation model based on a cross attention mechanism, and high-quality instance masks and classification labels are output. The method can significantly improve the precision and robustness of chromosome instance segmentation, and can be widely applied to the medical diagnosis fields of genetic abnormality detection, blood disease detection and the like.

The invention discloses a low-overhead anti-power analysis AES (advanced encryption standard) algorithm mask protection method. According to the method, two shares of a plaintext and a secret key are received in a clock period 0, ten rounds of round functions are executed from the clock period 0 to the clock period 30, each round needs three clock periods, and two shares of a ciphertext are output in a clock period 31; in the implementation of a round function and key expansion, the calculation of an S box (not including input linear mapping) needs three clock periods; in the third clock period after S box calculation is completed, a round of residual operation (wherein the residual operation of a round function comprises a multiplication module of the S box, S box output linear mapping, row shifting, column confusion and round key addition, and the residual operation of key expansion comprises key word XOR generation of a next round of round key) and the next round of S box input linear mapping calculation are completed at the same time. According to the mask, the side channel security capability of first-order power consumption analysis resistance can be provided for the AES algorithm, and the requirements on random numbers and chip area are remarkably reduced.

The disclosure relates to decomposition of masked values in a cryptographically secure digital signing system. Example embodiments include a method of decomposing mod 44 an N bit Boolean share input (b′B,k), where N>12, the method comprising: i) reducing (302-305) a number of bits in the Boolean share input (b′B,k) by adding a lower 11:0 bits of the input (b′B,k) to an upper portion of the input left shifted by 2 bits to provide a first intermediate result (t1B,13) having M bits; ii) reducing (306-309) a number of bits of the first intermediate result (t1B,13) by adding a lower 6:0 portion of the intermediate result to an upper portion left shifted by 2 bits and subtracted from a multiple of 44 to provide a second intermediate result (t3B,8); and iii) adjusting (310-316) the second intermediate result (t3B,8) by adding and / or subtracting 44 to provide an output (w1B,k′) having a value within an interval of 0:43, the output (w1B,k′) being a mod 44 representation of the input (b′B,k).

The embodiment of the invention discloses a multi-task processing model training method and device, a storage medium and electronic equipment, and the method comprises the steps: creating an initial multi-task processing model, initializing a shared basic mask score tensor and an exclusive residual mask score tensor, generating a task effective weight for each computer processing task based on the shared basic mask score tensor and the exclusive residual mask score tensor so as to perform forward propagation processing on each computer processing task; determining the task loss of the computer processing task according to a computer processing task prediction result so as to determine gradient information; determining a composite dynamic importance score based on gradient information and a model connection weight parameter, and adjusting a shared basic mask score tensor and an exclusive residual mask score tensor; and determining model composite total loss based on the task loss, the shared basic mask score tensor, the task exclusive residual mask score tensor and the composite dynamic importance score, and performing model parameter adjustment to obtain a multi-task processing model.

The invention provides a big language model training method and device, a data processing method and device, equipment, a storage medium and a program product. The method comprises the following steps: acquiring a sequence data sample, wherein the sequence data sample comprises a plurality of data units; performing attention calculation on the sequence data sample through a to-be-trained model to obtain a first attention intensity matrix; determining a time scheduling factor corresponding to the training time step, and determining a space scaling factor corresponding to each data unit; determining a mask matrix based on the time scheduling factor and the spatial scaling factor; adjusting the first attention intensity matrix based on the mask matrix to obtain a second attention intensity matrix, and determining an attention feature sample of the sequence data sample based on the second attention intensity matrix; and determining a loss value based on the attention feature sample, and updating parameters of the to-be-trained model based on the loss value to obtain a model obtained by training of the training time step. Through the method, the performance of the large language model can be improved.

The application provides an optimization method applied to X86 vector instruction translation, which is used for eliminating redundant instructions generated in the X86 vector instruction translation process, and the method comprises the following steps: obtaining the to-be-optimized code containing multiple instructions after translation processing, and performing the following steps: a mask optimization step: deleting redundant mask register setting instructions in the to-be-optimized code according to preset mask optimization rules to obtain mask optimization code; a vsetvli optimization step: deleting all csrr instructions and redundant vsetvli instructions in the mask optimization code according to preset instruction optimization rules to obtain target optimization code. The technical scheme of the application solves the problem of redundant instructions generated in the X86 vector instruction translation process through mask optimization and vsetvli optimization.

A string operation method, string operation device, and storage medium are disclosed. The method comprises: obtaining a unit operation width corresponding to the type of string operation; obtaining a processing data width for the target data to be operated; obtaining a number of repeated operations of the string operation on the target data; determining mask information based on the unit operation width, the processing data width, and the number of repeated operations; and writing the operation portion to a target address based on the mask information. This method effectively improves the execution speed of string operation instructions, reduces the number of micro-operations during the execution of string operation instructions, and increases the utilization of processor hardware resources.

The invention relates to a storage method and device for a weight matrix. The invention provides a weight matrix storage method, which comprises the following steps that: a high-bit weight matrix and a low-bit weight matrix which are subjected to generalized sparse processing are obtained from a large language model, the positions of elements in the high-bit weight matrix and the low-bit weight matrix are in one-to-one correspondence, and the positions of elements in the high-bit weight matrix and the positions of elements in the low-bit weight matrix are in one-to-one correspondence; the positions of the valid data elements in the high bit weight matrix and the positions of the valid data elements in the low bit weight matrix have complementarity; generating a mask identifier list according to the positions of the valid data elements in the high bit weight matrix; combining the high-bit weight matrix and the low-bit weight matrix into a combined weight matrix according to complementarity; and storing the merge weight matrix and the mask identifier list.

A system and method utilizes masked language models in order to provide data-type detection, such as (but not limited to) prediction of columnar headings. Two masked language models are pre-trained on example columnar text. One model predicts missing data at the entity level (e.g., masked entity names that may be made up of whole words), while the other predicts missing data at the character level (e.g., masked individual characters). The table with missing column headings is fed into both models, and the output is contextual word embeddings and contextual character embeddings. These results are merged, and then fed into a neural network classifier to then predict the column names.