15 results about "Cpu architecture" patented technology

The application discloses a method for executing data writing by using an autonomous yielding mechanism in a multi-CPU architecture, which is suitable for a solid state disk storage device. The method divides a main buffer area into multiple sub-buffer areas, each of which corresponds to at least one CPU, independently processes data writing and maintains a writing state; a global data consistency mark table and a local mark table are established to track the writing progress of each sub-buffer area, forming a double-layer consistency management. Each CPU sequentially writes data according to the corresponding sub-buffer area, and autonomously judges whether to interrupt, shorten or abandon the current writing section based on local observation information, temporarily yields the writing permission to other CPUs, temporarily retains and tracks the written data, continues writing when the subsequent CPU is completed or the system allows, and synchronously updates the mark table after any writing or yielding is completed, so as to maintain data consistency and overall efficiency.

The application relates to the field of automation arrangement, in particular to a cross-platform deployment automation arrangement system and method based on a Xinhua environment, which comprises a recognition module for recognizing the CPU architecture and the operating system of each server; a server evaluation module comprising an information collection unit, a first evaluation unit and a second evaluation unit; the information collection unit is used for acquiring the working information of each server in real time; the first evaluation unit is used for constructing a single performance score set according to the working information; and the second evaluation unit is used for calculating a comprehensive score according to the single performance score set. Compared with common simple weighted average or static threshold method and other deployment decision methods, the core advantage of the application lies in that the mutual dependence relationship among server resources is accurately simulated by introducing a dynamic coupling rule, so that the decision pitfalls such as "high-performance CPU with low memory" caused by the independence of the assumed indexes in the traditional method are solved.

The embodiment of the specification discloses a video monitoring adaptation interface and an adaptation method thereof, wherein the video monitoring adaptation interface adopts a layered architecture design of a hardware adaptation layer, a core service layer and a unified interface layer. The hardware adaptation layer respectively performs adaptation conversion according to CPU architecture and OS type of a video monitoring system and a communication protocol of a video acquisition device, and realizes unified adaptation to different hardware platforms, operating systems and video devices; the core service layer provides reliable video service processing capability; and the unified interface layer converts internal services into standardized interfaces. The application realizes 'one development, multiple deployment', reduces adaptation cost between various video monitoring systems and external systems, and improves compatibility and maintainability of a ship video monitoring system.

The application discloses a vehicle remote compliance test method, device, equipment and medium, and relates to the technical field of Internet of Vehicles safety, and the method comprises the following steps: reverse analyzing the CPU architecture of a target vehicle terminal to determine a to-be-tested program, and transmitting a compliance test tool into the target vehicle terminal; injecting the to-be-tested program into the compliance test tool, and then starting the compliance test tool to generate a test log; acquiring a request log sent by a server in the compliance test tool, and sending the test log to the server based on the request log, so that the server generates a test report based on the test log. Through the above scheme, the test efficiency is improved without closing the daemon process, without performing simulation, and only by transmitting the to-be-tested program into the compliance test tool, the test log can be generated, and then the test report is generated by using the test log.

A system and method for enhancing the performance of a Central Processing Unit (CPU) for artificial intelligence (AI) workloads. An orchestration engine logically partitions physical CPU cores into a plurality of “micro-containers,” which are isolated execution sandboxes. A workload profiler analyzes incoming AI tasks and provides performance metrics to an autoscaler. The autoscaler dynamically adjusts the number of active micro-containers on each core to optimize performance based on real-time hardware counter data, such as instructions-per-cycle or cache-miss rates. This architecture allows general-purpose CPUs to achieve performance comparable to specialized GPUs for parallel processing tasks, while reducing cost and power consumption.

The embodiment of the application provides a cross-architecture micro-service scheduling management system based on a large model, comprising: a cross-CPU architecture probe deployed on each computing node, used for collecting multi-element data of the computing node, the multi-element data comprising static instruction set features and dynamic runtime performance data; an instruction set perception layer, used for receiving and processing the multi-element data, and generating a performance portrait corresponding to the multi-element data through a large model; an intelligent monitoring layer, used for dynamically generating architecture-specific monitoring indicators based on the performance portrait and an architecture knowledge graph; a scheduling optimization layer, used for generating a service scheduling scheme according to the architecture-specific monitoring indicators and a preset multi-target dynamic balancing algorithm; and a drift adaptation layer, used for, when receiving a down drift instruction, driving a mirror real-time adaptation engine through a large model, and calling a mirror adaptation rule to perform service instance migration across the CPU architectures; the embodiment realizes maximum exertion of service performance and efficient utilization of cluster resources.

The application discloses a virtual machine vcpu thread special-purpose scheduler based on a linux kernel and KVM, and the main body is VMSCH, characterized in that: the VMSCH is a virtual machine vcpu scheduler, the VMSCH priority is between an RT scheduling strategy and a CFS scheduling strategy, the priority is 99, and the RT priority is adjusted from 1-99 to 1-98, the VMSCH only manages the scheduling of vcpu threads and does not manage other threads. In the application, the duty cycle of vcpu exclusive pcpu can be dynamically configured, and it is unnecessary to configure at booting, so that the flexibility of the scheme of isolating pcpu for vcpu use by using isolate is avoided, pcpu resource waste caused by bandwidth limitation and idle state of the RT scheduling strategy is avoided, and the application has CPU architecture independence, and after implementation, any CPU architecture, such as X86, ARM and Loongson, can be naturally supported, so that the application has extremely wide application range.

The present application belongs to the technical field of sparse matrix decomposition, and relates to a block method of performance-aware block sparse LU decomposition for a GPU platform, comprising the following steps: S1, constructing a performance function of a GPU computing kernel based on statistical data; S2, based on the performance function, designing a decision method for deciding whether to block a sparse matrix at a specified position; and S3, decomposing the overall block problem of a large-scale sparse matrix into multiple sub-problems decided in sequence, solving each sub-problem one by one based on a greedy heuristic strategy and using the decision method, and obtaining a final specific block scheme. Compared with existing methods, the method of the present application is more excellent in performance in the numerical decomposition stage, and is not only suitable for a heterogeneous platform of multi-core CPU and GPU, but also suitable for a pure CPU architecture.

Disclosed is a platform-agnostic 5G Distributed Unit (DU) Physical Layer (PHY) application deployable on general-purpose processors (GPPs) across multiple CPU architectures. The disclosed system decouples DU software from specific hardware platforms by utilizing SIMD abstraction and substitution libraries that enable portable vectorized signal processing. The PHY application may be deployed on both x86-based and Arm-based processors from a single source codebase. In-memory signal processing techniques minimize latency by managing data through pointers and performing operations in registers. The architecture supports containerized deployment and enables operators to select hardware components tailored to their requirements while maintaining functional equivalence across platforms. The disclosed approach may provide energy efficiency benefits through flexible processor selection.

The application provides a pipeline CPU architecture drawing method and a terminal device, the method is applied to the terminal device, and the method comprises the following steps: acquiring a module selection instruction input by a user through the terminal device, determining a CPU initial framework in a working area according to the module selection instruction; acquiring an instruction set selection instruction input by the user through the terminal device, determining the CPU instruction set in the working area according to the instruction set selection instruction; acquiring a combination instruction input by the user through the terminal device, combining a target instruction in the CPU instruction set with the CPU initial framework according to the combination instruction, and generating a module component in the working area according to a combination result; acquiring a completion instruction input by the user through the terminal device, and generating a CPU architecture diagram according to the module component and the CPU initial framework. The pipeline CPU architecture drawing method is softwareized, and the visibility and convenience of drawing are improved.

The application discloses a kind of digital twin emergency plan simulation system and method based on Feiteng CPU, belong to the field of emergency plan, including Feiteng CPU, i3D three-dimensional interactive application engine based on Feiteng CPU and simulation operation unit based on i3D three-dimensional interactive application engine, the simulation operation unit is based on Feiteng CPU architecture under operation, and i3D three-dimensional interactive application engine is used on the Feiteng CPU hardware server.It can be synchronized to twin system in the accident information, dispatch information, emergency measures and the like during accident emergency, can be kept running while synchronously maintaining emergency simulation system, and the complete reproduction, simulation of accident is carried out using twin system.

The application relates to a cross-production CPU architecture application compatibility dynamic adaptation method and system, which comprises the following steps: S1: acquiring a unified portrait object; S2: based on the unified portrait object, using a strategy learning model to generate an adaptation plan; S3: in the intermediate representation stage, the system preferentially loads an IR (Intermediate Representation) of an application; if not, a binary promotion tool chain is used to recover a control flow and a data flow from a native instruction set, to generate a verifiable IR, and a code large model is introduced to generate a multi-version candidate IR segment, and finally a verified IR package is formed; S4: combining a vector width, an execution port and a cache parameter of a target processor, an optimal compilation configuration is obtained through a limited search; and S5: according to the optimal compilation configuration, a compilation construction drawing is provided for final code generation and adaptation implementation, hot and cold paths are dynamically distinguished, and a compilation mode most suitable for the two is adopted. The application effectively improves the application compatibility dynamic adaptation efficiency and reliability.

This invention relates to a master-slave switching method for a dual-CPU architecture. The method includes: establishing two unidirectional GPIO lines and one bidirectional data transmission line between the two CPUs, and setting two configuration files; customizing unidirectional signal rules, message exchange rules, and communication message protocols; and after power-on, each CPU checks its STATUS status. loc Perform initialization; and according to the one-way signal rules and STATUS loc It interacts with the CPU on the other side via GPIO signals and sets state Y based on the signal transmission and reception status. GPIO ; and according to the communication message protocol and STATUS loc It exchanges communication messages with the CPU on the other side and sets the STATUS status based on the message exchange status. in Z COMM ; and based on STATUS loc STATUS in Z COMM and Y GPIO Configure master-slave switching. This invention can reduce the risk of misjudgment or loss of control.

The application discloses an arithmetic operation unit of independent carry register, and belongs to the technical field of computer processor design. A 64-base column structure is adopted, 8 bits of each column are equal to 6 data bits plus 2 carry bits, and 8 columns are simultaneously operated through a single 64-bit adder. The carry is stored in the independent register with the high 2 bits in the column, the carry register in the column embeds the carry in the data column, and the serial carry chain is eliminated. The parallel adder array uses 8 6-bit adders to work simultaneously, and there is no cascading dependence. A carry delay propagation circuit supports a configurable threshold, and the carry is temporarily not carried out during the operation process, and is processed in batches when needed. Compared with the traditional serial carry chain, the delay of the application is reduced by 8 times, the complexity is reduced from O(64) to O(8), the number of transistors is reduced by 77%, from 2300 to 532, the power consumption is reduced by 87.5%, the gate circuit flip is reduced from 64 levels to 8 levels, and parallel operation is supported throughout the process. The application is realized by using Verilog HDL, can be adapted to FPGA and ASIC, can integrate the existing CPU architecture, does not need to change the instruction set, the compiler is automatically optimized, and the program does not need to be adjusted.

This invention discloses a completely independent and original decimal abacus architecture computer system with reconstructed underlying logic. It aims to break through the architectural constraints of traditional binary computers and solve technical problems such as the monopoly of existing computer CPU architecture, high-end manufacturing processes, uncontrollable information security, large conversion losses, and insufficient computational accuracy. The system adopts a three-layer logical framework with a full-link design, using abacus rules as the computational core, binary as the information carrier, and decimal as the information core. It completely reconstructs the CPU core, simplifies chip manufacturing, and is compatible with the existing software ecosystem. The core design follows the principle of "binary as the base, decimal as the core, and abacus as the bridge." Binary is responsible for underlying temporary calculations and data transmission, while decimal uniformly manages the definition, storage, editing, and application of all final information. It can comprehensively cover applications in personal computing, professional design, artificial intelligence, supercomputing, and military applications, achieving a leapfrog improvement in computational efficiency, data accuracy, and architectural controllability, providing core technical support for the independent and controllable development of the national computer industry.