43 results about "Multicore architecture" patented technology

The invention relates to an SP application optimization method and device based on a multi-core NUMA architecture. The method comprises the following steps of: in a compiling stage, performing compiling optimization based on a multi-core NUMA (Non Uniform Memory Access) architecture, and performing memory management by adopting a memory allocator perceived by the NUMA; in the initialization stage, an MPI process is bound to a specific NUMA node, an OpenMP thread in the MPI process is bound to a physical core of the node, and a memory area in charge of the MPI process is initialized in parallel through the thread so as to achieve data locality; in the execution stage, a NEON instruction is adopted to carry out vectorization optimization on the step of calculating the residual vector local sum. By adopting the method, the memory access delay across the NUMA nodes can be remarkably reduced through multi-level collaborative optimization, and the instruction execution efficiency and the floating point operation throughput rate are improved, so that the execution performance and the parallel expandability of an SP reference program on a multi-core NUMA architecture server are effectively improved.

The invention relates to the technical field of standby power supply automatic switching, and provides an intelligent standby power supply automatic switching device suitable for multiple incoming lines of a distribution network and a control method thereof.The intelligent standby power supply automatic switching device comprises a digital processing module, an optical communication interface, a multi-incoming-line adaptive logic module, an intelligent standby power supply switching function module and a constant value and wave recording module; the optical communication interface transmits acquired switch position signals and maintenance pressing plate state signals to the digital processing module through optical fibers. The digital processing module adopts a multi-core CPU + FPGA architecture and is integrated with a time-frequency synchronization module, automatically generates spare power switching logic and transmits the spare power switching logic to the intelligent spare power switching function module; the intelligent spare power switching function module comprises a plurality of spare power switching modes. The method has the advantages that multiple incoming lines and complex topology are supported, N supply-N standby and other scenes of the distribution network are met, each power supply can be set on different buses according to a fixed value and can be set as an incoming line or outgoing line attribute, expansibility is high, and different requirements of current and long-term power supply attributes are met.

The application discloses a kind of semi-precision sparse matrix multiplication multicore parallel method and device for vector processor.There are three kinds of multicore parallel modes according to the dimension of matrix and the number of computing core, suitable for a variety of computing scenarios, make full use of the multicore architecture of vector processor.At the same time, it reduces the calculation redundancy under part of matrix dimension specification, improves the parallelism of sparse matrix multiplication calculation, helps to play the computing performance of vector processor.Each multicore parallel mode is to parallel multiple computing cores in the dimension of weight matrix and dense input matrix, and to realize sparse matrix multiplication in different dimensions.The theoretical calculation efficiency of sparse matrix multiplication calculation in each multicore parallel mode is obtained based on the dimension specification of two matrices.Then the multicore parallel mode with the maximum theoretical calculation efficiency is selected for sparse matrix multiplication calculation.This can automatically adapt the optimal mode to perform calculation, with high versatility and improved calculation efficiency.

The application discloses a kind of relay protection device bare core program log recording method and system.The relay protection device chip used in the method and system is multicore AMP architecture chip, wherein CPU core is divided into bare core and system core operation, and there is shared memory between bare core and system core.For the log recording of non-interrupt program, the log content is converted into ASCII code using bare core printf interface, and then placed into shared memory and output by serial printing.For the log recording of interrupt program, logmsg interface is used to only place log content into queue for saving, and the data in queue is converted into ASCII code in a special information processing task, and then placed into shared memory and output by serial printing.System core log storage thread reads LOG information in shared memory, and then writes log in the form of text into power-fail-safe file system Tpsfs.The method and system of the application can fully meet the requirements of relay protection device in different execution delay requirements to complete log recording, and improve the efficiency of log recording.

The invention discloses a universal neural network-oriented multi-core CNN acceleration processor, which comprises a plurality of acceleration cores, and is characterized in that each acceleration core is integrated with an instruction component, a scalar execution component, a vector matrix execution component, a multi-level cache component, an interrupt control component and a clock control component; the method is based on an RISC style instruction set, supports concurrent execution of a scalar instruction, a vector instruction and a matrix instruction, is used for accelerating reasoning calculation of a neural network, and is suitable for end-side equipment and an embedded scene; wherein the vector matrix execution component supports single-instruction multi-cycle execution, and the matrix operation unit processes 512 multiplication operations and 512 addition operations in each cycle so as to complete matrix multiply-accumulate operation. Through the multi-core architecture design and the efficient storage system, while high universality is kept, the neural network reasoning calculation performance is improved, the problem that flexibility and efficiency of a traditional accelerator are difficult to consider at the same time is solved, and an ideal hardware acceleration solution is provided for AI application in an edge calculation scene.

The invention discloses a directory-type distributed data structure implementation method and system, belongs to the technical field of data storage and concurrent processing, and aims to solve the technical problems of poor expandability and low performance of a traditional data structure under a non-cache consistency / partial cache consistency multi-core architecture. Comprising the following steps: dividing a multi-core architecture into a plurality of consistent islands, connecting the islands through a high-speed packet-loss-free network, and performing cross-island communication between cores through two communication primitives; a distributed hash table DHT is constructed, each server node maintains a plurality of hash buckets, the hash buckets adopt a linked list to solve conflicts, and a target server node and the hash buckets are positioned through a hash function; a server node is selected as a synchronizer, the synchronizer is used for distributing or recycling operation key values for a client side, the client side achieves data structure operation of stacks, queues and double-end queues through combination of two short messages and one DHT primitive, and linearization points of all the operations only depend on the moment when the synchronizer returns the key values.

The invention discloses a multi-task modular hierarchical regulation and control system based on a multi-core CPU architecture, which relates to the technical field of power generation control, and comprises a domestic multi-core CPU hardware basic module adopting a Feiteng or Peng architecture, a triple modular redundancy design and a 24-bit AD signal acquisition module based on a domestic operating system; the multi-task hierarchical scheduling core module is used for five-level priority division, a core binding and dynamic migration strategy and an improved round-robin algorithm; the modular function adaptation interface module supports hot plug, parameter self-matching and dual-path redundancy switching; the running state monitoring and feedback module is used for evaluating the health state in a weighted fusion manner; and an open development support module, dual-mode configuration and an encapsulation algorithm support third-party development and version management. According to the method, DCS autonomous controllability and efficient and balanced multi-task scheduling are realized, the operation monitoring and operation and maintenance intelligent level is improved, and safe and efficient operation of a unit is guaranteed.

The invention discloses a design method of an AI compiler of a multi-core end side AI chip, and belongs to the field of AI chip scheduling systems. According to the method, a multi-core storage allocation strategy, a synchronization mechanism and code generation optimization Pass are set in the compiling process, and efficient scheduling and modular management of the multi-core parallel computing tasks are achieved. The method is based on a multi-stage intermediate representation framework popular in the industry, corresponding functions are easy to develop, a multi-core storage distribution and synchronization mechanism can be defined in a specific Pass, modular management is achieved, the stability and expansibility of a compiler can be improved while the flexibility of a multi-core framework is guaranteed, and the method is suitable for popularization and application. Therefore, the performance and the development efficiency of the end-side AI chip in a complex application scene are improved.

Embodiments of the present application relate to a CPU scheduling method and a computing device. The method comprises: obtaining characteristic data of a to-be-scheduled thread in a process when running on each CPU core; calculating a comprehensive score of each CPU core based on the characteristic data and a weight corresponding to each dimension characteristic in the characteristic data; scheduling the to-be-scheduled thread to a selected CPU core based on the comprehensive score of each CPU core; when the to-be-scheduled thread runs on the selected CPU core, re-collecting the characteristic data, and adjusting the weight corresponding to the change of the characteristic data; updating the comprehensive score of each CPU core based on the adjusted weight, and scheduling the to-be-scheduled thread to a target CPU core based on the updated comprehensive score. In this way, the overall performance of the system can be improved. In this way, the memory access efficiency and overall throughput of application running under a multi-core NUMA architecture can be significantly improved, thereby improving the overall performance of the system.

An example method of implementing an application for a system on a chip (SOC) having an array of data processing engines (DPEs) includes determining a graph representation of the application, the graph representation including nodes representing application kernels and edges representing communication between the kernels; mapping the kernels onto DPEs of the array of DPEs and mapping data structures of the kernels onto memories in the array of DPEs based on the graph; routing communication channels between the DPEs and circuits of the application configured in programmable logic of the SOC; and generating implementation data for programming the SOC to implement the application based on results of the mapping and routing.

This application relates to the field of communication technology, specifically to a base station virtualization method, apparatus, computer device, and storage medium. The base station virtualization method includes: installing a target chip and its driver on a target device; wherein the target chip is a multi-core architecture, including at least an APE kernel and an NPU kernel, the APE kernel being a MaPU structure, and the NPU kernel deploying a container engine; starting the target chip based on the driver, calling the container engine to build and deploy multiple containers, and packaging and storing the applications and services required by each service layer in the base station to be virtualized into different containers; configuring the interaction between each container and each base station service layer in the base station to be virtualized based on a pre-configured containerized architecture; running the service processes corresponding to each application in each container to obtain the containerized target virtualized base station. This provides a base station virtualization method with superior performance, higher flexibility, higher efficiency, and lower cost.

This application discloses a hierarchical memory pool management method under a multi-core NUMA architecture, relating to the field of computer memory management technology. The method includes: creating a three-level memory pool architecture consisting of a Per-Core private pool module, a node shared pool module, and a global memory pool module, and generating metadata for memory blocks. When releasing a small block of memory, the metadata is read. If the current core and the core identifier in the metadata are inconsistent, direct writing to the Per-Core private pool module corresponding to the core identifier is prohibited, and the memory block to be released is transferred to the corresponding node shared pool module according to the node identifier. The node shared pool module assigns it to the small free resource block of the node shared pool module corresponding to the node identifier, and when a request for replenishing a small resource block of the same size is received, it prioritizes allocation from the small free resource block. This application improves the concurrency performance, access locality, and resource reuse efficiency of memory pool management under a multi-core NUMA architecture.

The invention discloses a method for quickly upgrading embedded equipment based on firmware partition. The method comprises the following steps: after the embedded equipment is powered on, reading firmware data in Flash and partitioning the firmware data; the PC reads the firmware file to be upgraded and divides and packs the firmware file; the PC sends the partitioned data packet to the embedded device; the embedded device compares the received partition data with the original corresponding partition data in the Flash in real time while receiving the data packet; a multi-core architecture of embedded equipment is utilized to distribute tasks to different cores for parallel execution, and after processing of all partitions is completed, a PC machine is notified that updating is completed through a UDP (User Datagram Protocol). According to the method, the firmware updating efficiency of the embedded equipment is greatly improved, the firmware updating time is shortened by utilizing the partition erasing characteristic of Flash and the multi-core parallel processing capacity of the embedded equipment, and good feedback is obtained in actual engineering application.

The invention relates to the technical field of embedded system development and verification, and discloses a joint simulation system and method for a heterogeneous multi-core processor. The simulation module is configured to execute processor multi-core architecture simulation, multi-core parallel simulation, memory system layered modeling, peripheral and interface simulation and debugging and performance analysis; the programmable logic subsystem simulation module is configured to provide a multi-precision modeling framework and a dynamic reconstruction mechanism, the multi-precision modeling framework comprises a behavior-level model, a register transfer-level model and a hardware-in-the-loop simulation model, and the dynamic reconstruction mechanism supports model hot plugging and parameter adjustment during operation; and the interaction module is configured to execute data interaction, synchronization and joint debugging of the processor subsystem simulation module and the programmable logic subsystem simulation module. The method is suitable for software and hardware collaborative development and verification of the heterogeneous computing platform.

The invention provides a starting method and device of a multi-core heterogeneous operating system and electronic equipment, and belongs to the technical field of computers. The method comprises the steps that a starting configuration file is obtained, the starting configuration file comprises configuration information corresponding to M different types of system mirror images, and M is a positive integer; wherein the M different types of system mirror images comprise a system mirror image corresponding to the Hypervisor; for any system mirror image, distributing mutually isolated storage areas for the system mirror image according to the configuration information corresponding to the system mirror image; loading the M different types of system mirror images to respective corresponding storage areas; and waking up the processor cores corresponding to the M different types of system mirror images according to a preset starting mode so as to start the corresponding system mirror images. Therefore, the parallel processing capability of the multi-core architecture processor can be fully exerted, and the response efficiency is improved.

The invention provides a time sequence simulation method and device for a distributed multi-core architecture. Each computing node of the architecture comprises a ready queue, a storage unit and a computing unit. The method comprises the following steps: inserting all tasks executed in a DAG into a ready queue of a computing node to which the tasks belong; inserting a scheduling event of a task in the non-empty ready queue into the GEQ; sequentially popping up a scheduling event with the earliest event time from the GEQ as a current event; simulating the current task through the computing node to which the current task belongs until the GEQ is empty; wherein the current task is a task scheduled by the current event. According to the method, the scheduling events of the tasks in the non-empty ready queue are inserted into the GEQ, the scheduling events in the GEQ are subjected to simulation processing in sequence from morning to evening according to the event time, the task division scheme and data transmission can be quickly simulated and verified under the condition that codes are not actually modified and run, the real performance bottleneck can be accurately positioned, and the task division efficiency is improved. And carrying out fine-grained optimization and deep analysis.

The application discloses a kind of multilayer convolutional brain-like chips based on full pulse HMAX model, chip uses layer type configurable multi-core architecture, overall by global controller, several cascaded pulse convolution kernel, interlayer shared learning engine and output pulse decoder four parts are formed.The global controller is mainly responsible for the transmission, interaction and control of processor internal and external data.Pulse convolution processing kernel is the core module of processor, it is connected in turn, and the pulse data output by the previous processing kernel is received by the next processing kernel.When a certain network layer is in learning state, the network layer will call interlayer shared learning engine module to complete on-chip learning.Output pulse decoder decodes AER data output, thereby realizing classification function, and the result is output externally.The application can realize efficient on-chip learning and inference of full pulse HMAX model, and solves the problems of low recognition rate, insufficient performance and poor energy efficiency of existing edge brain-like chips.

The invention relates to the technical field of network security, can be applied to the field of science and technology finance / digital medical treatment, and discloses a packet loss optimization method and device for a network intrusion detection system, equipment and a medium. The method comprises the following steps: calling a packet loss statistics interface, collecting and updating packet loss associated data in real time according to a preset frequency, and dynamically capturing a packet loss state; when packet loss is detected, CPU affinity configuration is adjusted, and the management threads are bound to the first core, the working threads are bound to the remaining cores, and the number of the remaining cores is matched with the number of the remaining cores; closing automatic soft interrupt processing, and distributing a network to receive a queue interrupt request to each core according to the CPU multi-core architecture; collecting each core load through a monitoring tool, and identifying a high load core exceeding a threshold value; optimizing CPU affinity configuration and / or interrupt distribution according to the kernel mode and user mode occupancy rate; and according to the optimized load and packet loss state, judging that optimization succeeds or hardware bottleneck exists. The method improves the utilization rate of system resources, reduces packet loss, and guarantees the integrity of intrusion detection.

The invention provides a relay protection load balancing method based on a multi-core architecture, which relates to the technical field of relay protector control, and comprises the following steps: judging the load of each core module according to the daily task being executed by each core module and the weight and execution time of the daily task in a queue to obtain the load conditions of all core modules; then, the emergency tasks caused by equipment abnormity are allocated to the lowest core module according to the weights of the emergency tasks, and then the emergency tasks are sorted in the core modules according to the running time of the emergency tasks, so that smooth completion of the emergency tasks is ensured, and load balancing of the multiple core modules is realized; and meanwhile, the relay protector can make a decision for abnormal equipment within specified time, and the safety of the equipment is guaranteed.

Providing dataflow based guidance for buffer allocation in a multicore circuit architecture includes converting, using computer hardware, an application specified in a high-level programming language into an intermediate representation. Buffers of dataflows of the intermediate representation are detected. Determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation. Buffer constraints are generated. The buffer constraints specify whether the buffers are independent and dictate a mapping of the buffers in the multicore circuit architecture.

The application provides a relay protection load balancing method based on a multi-core architecture, and relates to the technical field of relay protector control.The application judges the load of each core module according to the daily task being executed by each core module and the weight and execution time of the daily task in the queue, obtains the load conditions of all core modules, then distributes the emergency task caused by the abnormal equipment to the lowest core module according to the weight of the emergency task, and finally sorts the emergency task in the core module according to the running time of the emergency task, so as to ensure the smooth completion of the emergency task, realize the load balancing of the multi-core module, and enable the relay protector to make a decision for the abnormal equipment within a specified time, thereby ensuring the safety of the equipment.

A computer system having a multi-kernel architecture comprising multiple operating system microkernels is described. The computer system comprises multiple processing cores, a memory comprising multiple private memory regions and a shared memory region, and multiple compute nodes each comprising one or more processing cores and further comprising one of the multiple operating system microkernels and an associated user space for non-kernel operations, wherein only the operating system microkernels run at the highest privilege level of the one or more processing cores of the compute nodes. Each of the multiple compute nodes has an associated private memory region from the multiple private memory regions for use by the operating system microkernel of the each of the multiple compute nodes, and for non-kernel operations, each of the multiple compute nodes accesses the shared memory region. Associated methods and computer systems are also described.

The invention relates to a dynamic loading and unloading method based on a multi-core AMP architecture DSP operating system. The dynamic loading and unloading method comprises the steps that a dynamic mirror image is transmitted to the operated multi-core AMP architecture DSP operating system; transmitting the dynamic mirror image to a file system of the operating system through a network service of the operated DSP operating system, and analyzing and loading the dynamic mirror image by a single core; executing the loaded dynamic module function by multiple cores; a code segment and a global data segment in the generated dynamic module are shared by multiple cores, each core of a private data segment is private, and relocation of a dynamic symbol is completed; at the moment, function interfaces in the dynamic module can be called and executed on each core; uninstalling the dynamic module by a single core; the process of unloading the dynamic module is an inverse process of the loading process, and releasing and recycling of the allocated resources are completed. The problems that cores of an AMP framework adopted by a DSP operating system are mutually independent and access to shared peripherals and shared memories is mutually associated are solved, the dynamic mirror image is loaded by a single core and can be accessed by multiple cores, and flexible deployment of the dynamic application mirror image is improved.

The invention relates to the technical field of task interaction, in particular to a multi-queue task efficient interaction method and system of a multi-core architecture, and the method comprises the steps: configuring a local direct access storage space for each CPU core; the CPU core issues a task instruction to the hardware acceleration unit; the hardware acceleration unit executes a task receiving or sending process according to the instruction type; the task is carried between a queue and a storage space, and state information is written back to a fixed address of the storage space; the CPU core completes interaction through the state information; through local storage and hardware centralized management, batch carrying and lock-free queue operation are realized, multi-core competition and access delay are effectively reduced, and task interaction efficiency is remarkably improved.

The invention discloses a data governance system with metadata as a skeleton, and relates to the technical field of data governance, and the system comprises a metadata collection and processing module which is used for collecting multi-source equipment data streams in real time; the adaptive trusted chain module is used for performing security feature extraction on the standardized metadata object, evaluating a current security state through a reinforcement learning model, and dynamically generating a verification rule; the meta-model management module is used for analyzing credible metadata in the credible metadata chain, extracting key feature information and constructing a metadata blood relationship graph through a graph database technology; and the intelligent governance response module is used for analyzing the blood relationship information in the enhanced metadata blood relationship map and evaluating the current governance demand of the data entity. According to the invention, efficient data processing and hardware collaboration are realized, the metadata acquisition and processing processes are parallelized and vectorized by deeply utilizing the multi-core architecture and the vector instruction set of the autonomous controllable processor, the data throughput is greatly improved, and the operation delay is reduced.

The invention discloses an extreme environment path planning method and system based on an RISCV multi-core architecture, and relates to the technical field of path planning, and the method comprises the steps: carrying out the operation in a simulation environment based on an existing path planning algorithm, and obtaining key calculation features; performing comparison in different complexity scenes based on the key calculation features to obtain quantization results of the key calculation features; optimizing a standard RISCV instruction set by taking reduction of invalid instruction execution and core operation delay as a target based on the quantification result to obtain an optimized instruction set; constructing a final hybrid interconnection topological structure of a master core-slave core star type and a local mesh by taking reduction of redundant data transmission and cross-core synchronization overhead as a target based on a quantization result; and obtaining a target task, calling and executing a corresponding optimization instruction set on the final hybrid interconnection topological structure, and completing the path planning of the extreme environment. On the basis of improving the robot path planning efficiency, the power consumption is obviously reduced.

The application provides a video coding method and device. The video coding method comprises: splitting a to-be-coded image to obtain a plurality of sub-images; obtaining a plurality of sub-image description information, wherein the plurality of sub-image description information corresponds to the plurality of sub-images, and the sub-image description information is used for describing the size and position of the corresponding sub-image; respectively coding the plurality of sub-images to obtain a plurality of sub-image compressed bit streams; and merging and transcribing the plurality of sub-image compressed bit streams to obtain a full-image compressed bit stream, wherein the full-image compressed bit stream comprises the plurality of sub-image description information. The application can be suitable for use in a multi-core architecture system, and can make the system-level complexity low and the compatibility stronger.

The invention relates to the technical field of computers, in particular to an inter-core message hardware acceleration method and system based on a multi-core architecture. The method comprises the steps of building a hardware architecture, opening up a multi-core enqueued message cache space, and configuring an access base address and a space size of a message queue; judging the trigger enqueue and batch enqueue conditions of the register, and sending a message enqueue request; switching the path of the message among the enqueue cache, the dequeue cache and the DDR cache; sending a dequeue request to a dequeue request cache unit, writing a message into a target memory address, and then obtaining the message from the address; the system comprises a software and hardware initialization configuration module, a message enqueue processing module, a layered cache dynamic scheduling module and a message dequeue processing module. Through queue management, hierarchical cache scheduling and order-preserving read-write control, the problem of lock competition of inter-core communication of the multi-core architecture is effectively solved, low-delay and high-capacity transmission of inter-core messages is realized, and the CPU occupancy rate is reduced.

This invention discloses a Winograd convolution optimization method and system suitable for ARMv8 multi-core architecture, belonging to the field of deep learning technology. The method includes: determining the tile block value T. blk Input channel block value C blk and output channel block value K blk And based on the tile block value T blk The input data is divided into tile blocks; the global domain transformation of the filter is completed through a nested loop, and the results of the global domain transformation are stored in the FilterOut array according to the data layout of the first matrix multiplication; the tile block values ​​T are then used to divide the input data into tile blocks. blk By traversing the tile blocks and performing intra-block input transformation, coupled matrix multiplication, and output transformation on each tile block, the Winograd convolution optimization result is obtained. This invention can significantly improve the computational efficiency of the Winograd algorithm.

A multi-core decoder (31) for decoding low-density parity-check (LDPC) codewords. The multi-core decoder includes a group of cores (10) capable of each simultaneously decoding a different LDPC codeword. The group includes memory (20) shared between the cores (10) in which predefined Nc configurations are stored. Each predefined configuration includes a binary parity matrix corresponding to an LDPC code. Each core is suitable for being dynamically configured with any one of the Nc predefined configurations stored in the shared memory (20) to decode an LDPC codeword using a selected Nc configuration.