120 results about "Multicore architecture" patented technology

A method and apparatus for resource management in a multicore processor is disclosed. A system management controller (130) provides omnipresent scheduling, synchronisation, load balancing, and power and memory management services to each processing resource (150) within in a multicore processor (10), via a plurality of system management clients (120) implemented in hardware or software. The controller (130) allocates the tasks executing in each processing resource (150) by means of interrupt control signals, which interact directly with the system management clients (120), enabling processing resources (150) to autonomously create, execute and distribute tasks around a parallel system architecture whilst monitoring and policing the use of shared system resources (140).

According to a first aspect of the present invention, there is provided a method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators indicative of one or more parameters relating to the function and/or identity of a thread or threads comparing at least some of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

The present invention is directed towards systems and methods for determining failure in and controlling access to a shared resource in a multi-core system. In some embodiments of a multi-core system, individual cores may share the same resource. Additionally, the resource may occasionally fail or need to be reset, and the period during which the resource is being reset may be non-instantaneous. In an embodiment without coordination between the cores, one core experiencing a failure may reset the resource. During the period in which the resource is resetting, another core may interpret the reset as a failure and reset the resource. As more cores interpret the resets as failures, they will trigger resets, quickly resulting in the resource being constantly reset and unavailable. Thus, in some embodiments, a coordination system may be utilized to determine failure of a shared resource and control resets and access to the shared resource.

The computational efficiency of Finite Element Methods (FEM) on parallel architectures is typically severely limited by sparse iterative solvers. Standard iterative solvers are based on sequential steps of global algebraic operations, which limit their parallel efficiency, and prior art techniques exploit sophisticated programming techniques tailored to specific CPU architectures to improve performance. The inventors present a FEM Multigrid Gaussian Belief Propagation (FMGaBP) technique that eliminates global algebraic operations and sparse data-structures based upon reformulating the variational FEM into a probabilistic inference problem based upon graphical models. Further, the inventors present new formulations for FMGaBP, which further enhance its computation and communication complexities where the parallel features of FMGaBP are leveraged to multicore architectures.

The invention relates to a monocular vision ranging method based on edge point information in an image and belongs to the unmanned aerial vehicle navigation and positioning technical field. The method includes the following steps that: two frames of images are selected from an image sequence captured by a downward-looking monocular camera fixedly connected with an unmanned aerial vehicle so as be adopted to construct an initial map and an initial depth graph, a first frame is adopted as a first key frame in the map, and a camera coordinate system corresponding to the first frame is adopted as a world coordinate system, and initialization is completed; and three threads, namely, a motion estimation thread, a map construction thread and a depth graph estimation thread are carried out parallelly, wherein the motion estimation thread aligns known map and depth graph information with a current frame so as to obtain a ranging result, and optimizes the existing map information according to the ranging result, and the map construction thread and the depth graph estimation thread operate simultaneously so as to maintain the map and depth graph information. According to the method of the invention, the multi-core architecture of a modern processor is fully utilized, and the edge point information in the image can be effectively utilized, and based on corner point information, the efficiency of the algorithm is improved. The method has higher adaptability.

The invention relates to a method for realizing a virtual execution environment of a central processing unit (CPU)/graphics processing unit (GPU) heterogeneous platform, which belongs to the technical field of telecommunication. In the method, programs can be run on an X86CPU and NVIDIA GPU hybrid architecture by a dynamic binary translation technique; static information and dynamic information of the programs are acquired by the dynamic binary translation technique; program execution nested loops, a dependency relationship among the loops and data streams of inlet and outlet hot blocks are searched through the information; and the execution is implemented by two steps of: 1, acquiring information, optimizing the hot blocks and storing the hot blocks into files; 2, and generating a hybridprogram comprising a serial instruction and a parallel instruction and executing the program comprising the hybrid instructions. The method has the advantages that: the traditional serial programs can be run a CPU/GPU heterogeneous multi-core architecture by the dynamic binary translation technique, without modifying program source codes; and the execution of the programs can be accelerated by the GPU.

A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.

Computer-implemented methods, carrier media, and systems for detecting defects on a wafer based on multi-core architecture are provided. One computer-implemented method for detecting defects on a wafer includes acquiring output for the wafer generated by an inspection system. Dies are formed on the wafer, and multiple cores are formed in the dies. The method also includes detecting defects on the wafer by comparing the output for a first of the multiple cores to the output for a second of the multiple cores. The first and second of the multiple cores are formed in the same die, different dies, or the same die and different dies.

A system and method for indexing documents in a data storage system includes generating a single document hash table in storage memory for a single document using an index construction in a multithreaded and scalable configuration wherein multiple threads are each assigned work to reduce synchronization between threads. The single document hash table includes partitioning the single document and indexing strings of partitioned portions of the single document to create a minor hash table for each document sub-part; generating a document level hash table from the minor hash tables; updating a stream level hash table for the strings which maps every string to a global identifier; and generating a term reordered array from the document level hash table.

The invention provides an Xen virtual machine scheduling control method in multi-core environment. The method comprises the following steps: (I) carrying out scheduling initialization; (II) carrying out initialization of scheduling information statistics, namely monitoring the virtual CPU (central processing unit) in a management domain 0, and sending the monitoring result to a VMM (virtual machine monitor) in real time; (III) creating a virtual machine, allocating the virtual CPU, storing the virtual CPU to a red black tree of a corresponding CPU group according to the priority level and a credit value, and starting all timers set in the initialization stage; and (IV) scheduling the virtual machine. According to the invention, the time slice executed by a logic CPU in the group can be dynamically adjusted, the time consumed by the scheduling method in the execution process is effectively reduced, relatively short response time for the IO (input/output) task is realized, and the method adapts to any type with relatively high requirement on time.

A multicore processor provides for local power control at each of the cores which is used to lower the maximum operating frequency of cores by any amount above of the maximum operating frequency of the slowest core. This power savings is then used to increase the maximum operating frequency of the frequency balanced cores within a power constraint.

Software Managed Manycore (SMM) architectures with scratch pad memory for reach core are a promising solution for scaling memory. In these architectures the code and data of the tasks mapped to the cores is explicitly managed by the compiler and often require inter-procedural information and analysis. But, a call graph of the program does not have enough information, and the Global CFG has too much information. Most new techniques informally define and use GCCFG (Global Call Control Flow Graph)—a whole program representation that succinctly captures the control-flow and function call information—to perform inter-procedural analysis. Constructing GCCFGs for several cases in common applications. The present disclosure provides unique graph transformations to formally and correctly construct GCCFGs for optimal compiler management of manycore systems.

The invention discloses a multicore architecture supporting dynamic binary translation, aiming to solve the problems of Cache access conflict, main memory conflict and the like during dynamic binary translation. The multicore architecture comprises a plurality of processor cores, a plurality of primary Caches, a plurality of translation cache units, a secondary Cache and a main memory controller,wherein the primary Caches and the translation cache units are private for each processor core; the secondary Cache and the main memory controller are shared by all the processor cores; each translation cache unit comprises a communication control unit, a cache management unit and a data memory unit; the communication control unit comprises a multi-channel selector, a communication control unit controller, a transmission bus and three registers; the cache management unit comprises a page replacement component and a cache management control component; and the data memory unit comprises a source architecture binary code cache area, a target architecture binary code cache area and a page mapping table. The multicore architecture has the following technical effects: the data access latency isreduced, the translation throughput is high and the Cache access conflict is less.

The present invention is a software architecture that provides high versatility and performance. This architecture is composed of two dimensions: the first one belongs in the application level, and the second in the multicore dimension. The application dimension is related to the different applications based in the conceptual model of abstractions exposed in this patent. The multicore dimension is related to the applications dimension instantiated several times in the same computer (multiple processors) or in several computers. All the cores within the multicore dimension are related in order to share information and integrate all the architecture's applications. The multicore architecture avoids bottlenecks in the simultaneous execution of multiple applications on the same computer by means of a large virtual core composed of small interconnected cores. The conceptual model of abstractions is composed of various drivers, abstraction layers and a unique core that provides support by playing a referee role between different extensions of an application.

The invention relates to the field of hierarchical structure design of storages and aims to provide a method for realizing replacement policies of a shared second-level cache under a multi-core architecture. The method comprises the following steps: dividing a cache group, carrying out a close replacement policy, and carrying out different replacement policies on different programs according to different access modes of programs on cores under the multi-core architecture. The invention has the advantages that in a multi-core environment, aiming at the problems existing in the least recently used replacement policy, cache blocks in the cache group are grouped, and different replacement policies are respectively used for the groups, thereby reducing the cache deletion, greatly reducing the storage cost and the complexity of circuits and enhancing the performance of the system. In a multi-core environment, different replacement policies are more adapted to different programs or threads, and therefore, the invention proposes that different cache replacement policies are performed in different divided groups.

The invention discloses a heterogeneous multi-core parallel processing device and method for heterogeneous multi-source big data. The processing device and method are realized by the adoption of a ZYNQ-7000SoC chip of the Xilinx company. The device comprises an FPGA-based heterogeneous multi-source big data parallel collection module and a heterogeneous multi-core data parallel processing module,wherein the parallel collection module caches collected data of different equipment into an off-chip DDR with different offset addresses and sizes through an on-chip HP port in a DMA mode, and meanwhile a design state machine mounts the off-chip DDR on an on-chip AXI bus; and multiple MicroBlaze cores are set up in the parallel processing module, and the MicroBlaze cores and an ARM core form a heterogeneous multi-core architecture, wherein different MicroBlaze cores are responsible for processing different equipment data, the ARM core completes performance monitoring on the MicroBlaze cores, and different data processing algorithms are dynamically scheduled to run on the MicroBlaze cores to guarantee load balance of the cores. Through the processing device and method, efficient parallel processing of big data of different equipment on a manufacturing site can be realized, and an intelligent manufacturing superior decision can be effectively supported.

The invention relates to a low-expense block synchronous method supporting a multi-core assisting thread, which belongs to the technical field of multi-core computers. The method reduces data missing in the execution of a calculation thread, reduces the pollution to a shared cache, improves the execution performance of the calculation thread and achieves heteronuclear synergic irregular data push by introducing a mechanism of pre-acting and low-expense block synchronization and cycle control for a prefetch assisting thread aiming at the problem of irregular data missing in multi-core application on the basis of a multi-core structure for the sharing cache. The method can be widely applied to optimizing a multi-core compiler and the database performance in the future.