170 results about "Core system" patented technology

The invention discloses a multi-kernel system real-time task scheduling method, system and device based on scene differentiation and a storage medium, and the method comprises the following steps: carrying out the dependency analysis of a task set, and obtaining a task dependency directed graph between tasks; based on the task dependency digraph, determining a regulation and control energy level index corresponding to each task; converting the task dependency directed graph into a task situation graph; determining a scheduling sequence table of the tasks based on the task situation chart and the regulation and control energy level indexes; and allocating real-time tasks to the multi-kernel system based on the scheduling sequence table. The method can be widely applied to the technical field of task scheduling.

The invention discloses a multi-machine multi-card distributed training optimization system and method oriented to a credential heterogeneous environment, and relates to the technical field of distributed training. In order to solve the defects existing in distributed training in a credential and credential heterogeneous environment, the system comprises an application layer for receiving a training task; the core system layer comprises a self-adaptive task scheduling module, a hybrid communication topological optimization module and a dynamic check point and elastic recovery control module, and the scheduling module generates a performance portrait and an optimal scheme based on a training task and adjusts the scheme according to a node fault; the optimization module executes the scheme, firstly detects node topology, constructs a hierarchical path, loads and initializes an optimal communication rear end for target equipment, and synchronizes the path to the target equipment; the control module periodically stores a complete training context and realizes reliable recovery of a training process; the credential hardware abstraction layer is used for providing a uniform interface for realizing underlying resource access and data acquisition; and the hardware resource layer comprises heterogeneous computing nodes and an RoCE network switch.

The invention discloses a core particle system architecture, which comprises a system management core particle, a functional core particle, an interconnection core particle and an IO core particle, the system management core particle is used for monitoring the working state of each functional core particle; the system management core particle is used for receiving externally input tasks and distributing the tasks to the functional core particles according to the working states of the functional core particles; the functional core particles are used for executing tasks distributed by the system management core particles; the interconnection core particles are used for realizing communication between the system management core particles and the functional core particles and among the functional core particles; and the IO core particle is used for realizing communication between the system management core particle and the outside. The core particle system architecture provided by the invention is comprehensive in function, high in flexibility, strong in reliability, good in compatibility and capable of effectively fusing wide core particle resources, and has a wide application prospect in a high-performance electronic system.

According to an embodiment, a method for scheduling preemption in a multi-core system is proposed. The method includes generating a plurality of task requests, each task request corresponding to a job to be executed by an auxiliary processor and having a respective priority level; storing the plurality of task requests in the shared memory; selecting a first task request from the plurality of task requests stored in the shared memory with a highest priority level; communicating the first task request to the auxiliary processor; suspending an execution of a current task in response to receiving the interrupt signal; retrieving the respective priority level of the first task request; adding the first task request and its respective priority level to an execution queue; and executing a task from the execution queue having a highest priority.

The invention discloses a management and maintenance method and system for a heterogeneous multi-core processor of a spaceborne computer, and relates to the technical field of space scientificity, and the method comprises the following steps: configuring a global addressing controller through a main core in a power-on initialization stage, and executing address access authority distribution of a heterogeneous multi-core processor core; on the basis of combination of a sub-core storage partition strategy and a heartbeat monitoring reset mechanism, a master core periodically detects the state of a slave core and executes reset operation, and lightweight fault-tolerant management of a heterogeneous multi-core processor is achieved to guarantee continuous operation of a multi-core system under local faults; according to the method, radiation-induced storage errors are corrected based on a master core read-back refreshing strategy, slave core access behaviors are restrained through an address space locking mechanism, a master-slave collaborative reliability maintenance system is formed to ensure on-orbit stable operation of the spaceborne computer, and continuous and stable operation of the heterogeneous multi-core processor of the spaceborne computer in a complex space environment can be ensured.

Systems and techniques for selectable slice mapping in shared cache levels are described. In one example, a processor includes a cache system having a shared cache level of a hierarchy of cache levels and slice hashing circuitry associated with the shared cache level. The shared cache level includes multiple slices accessible by threads running on multiple processor cores. The slice hashing circuitry assigns memory addresses used by a particular thread to a subset of the multiple slices closest to the processor core on which the thread runs. The assignment of the slice subset is based on the latency requirements or the data usage of the thread in at least one implementation. The described techniques improve tail latencies for multiple core systems and alleviate the need for additional interconnections for shared cache levels.

The embodiment of the invention provides a system on chip, a computer system, a data sharing method and a data sharing device, and belongs to the technical field of computers. The system on chip comprises a processor core cluster comprising a plurality of processor I P cores, a tight coupling memory comprising a plurality of memory units, an interconnection module used for establishing a first connection channel between the processor I P cores and the interconnection module for each processor I P core, and a second connection channel for establishing a second connection channel between the processor I P cores and the interconnection module for each processor I P core, and determining a target storage unit corresponding to each processor IP core in the plurality of storage units according to a pre-configured target mapping relationship, and establishing a second connection channel between the interconnection module and the target storage unit, so that the processor IP core accesses target data of the target storage unit according to the first connection channel and the second connection channel. Compared with a traditional integration mode, according to the embodiment of the invention, the tight coupling memory is no longer private for the processor I P core, so that the implementation difficulty of multi-core data sharing in the multi-core system is reduced.

This application provides a method, apparatus, device, and storage medium for inter-core interaction in a multi-core system, relating to, but not limited to, the field of computer technology. The method includes: a first core determining an interaction channel group corresponding to a destination core based on a destination core for first interaction data to be transmitted; the destination core being one of at least one second core, with each second core corresponding to a specific interaction channel group; selecting a first interaction channel from a plurality of second interaction channels in the interaction channel group based on the interaction type of the first interaction data; and sending the first interaction data to the first interaction channel, so that the destination core obtains the first interaction data by listening to the interaction channel group. The apparatus, device, and storage medium are applied to the above interaction method. Embodiments of this application can simplify inter-core interaction operations and thus improve the execution efficiency of threads between multiple cores.

The application discloses a transaction batch processing method, a server, a computer device and a storage medium, and relates to the technical field of transaction batch processing. The method comprises the following steps: receiving a transaction request, and recording the date of the transaction request according to a natural date during batch processing; if the batch processing is performed before 0 o'clock, performing a first refresh on a core system before 0 o'clock; performing a second refresh on the core system at 0 o'clock, so as to synchronize transaction data between the first refresh time and the second refresh time; recording the date of the transaction request after the second refresh according to the natural date; wherein the natural date is Greenwich Mean Time and cannot be changed. The accuracy of the date record of the transaction of the bank core system can be improved, the situation that the transaction date queried by a customer is inconsistent with the transaction date recorded by the bank system can be avoided, customer complaints can be reduced, and the experience and satisfaction of the customer are improved.

Methods and systems for providing computer implemented services are disclosed. To provide the services, information from a variety of systems may be aggregated. Prior to aggregation, the sources of the information may perform processes for enhancing the provided information. The processes may include removing information that is unlikely to benefit the computer implemented services, and identifying hidden information that is not explicitly noted but that is likely to benefit the computer implemented services. The processes may distribute the workload for preprocessing the aggregated information to reduce the likelihood of bottlenecks or other limits on throughput rate of the computer implemented services from occurring.

The invention discloses a memory access management method for a heterogeneous multi-core system oriented to a deep neural network, belonging to the storage system structure field of a computer system. The invention utilizes CPU-GPU heterogeneous multi-core system to accelerate DNN model training, and designs a memory access controller according to its memory access characteristics. In the DNN training process, the final cache shared by multiple cores is unloaded, preretrieved and released, and the fine-grained data transmission process significantly improves the utilization rate of the final cache. In addition, the memory access controller also designed a delay hiding mechanism, by overlapping the access process of a large number of intermediate data in the feature extraction layer and the calculation process, reducing the calculation performance loss caused by the miss of the final level cache and the need to wait for the memory access response of DRAM during the model calculation process, and optimizing the training efficiency.

The embodiment of the present application provides a joint debugging test method, device, storage medium and electronic device, the method comprising: obtaining the current natural date and current business date of the core system; obtaining the current natural date year-month table corresponding to the current natural date in the peripheral system, and the current business date year-month table corresponding to the current business date, the current natural date year-month table recording the transaction data generated when the transaction was conducted on the current natural day; obtaining the transaction data from the current natural date year-month table, and migrating the transaction data to the current business date year-month table; receiving the data file sent by the core system after the transaction data is recorded, and recording the transaction data in the current business date year-month table according to the information in the file, to complete the joint debugging test. The embodiment of the present application can ensure that the peripheral system processes the transaction data in the current business date year-month table normally when recording the transaction data, and the transaction data is not lost.

The present disclosure provides a routing table updating method and system based on a many-core system, an electronic device and a readable medium. The method comprises: in the case that a routing table updating condition is met, determining routing transmission information between a first processing core and a second processing core according to a current physical position of the first processing core and a current physical position of the second processing core; and updating a routing table corresponding to the first processing core according to the routing transmission information. The second processing core is a processing core receiving a data packet of the first processing core. The routing table updating condition comprises at least one of the following: the routing table corresponding to the first processing core is empty, and the physical position of the first processing core and / or the second processing core is changed. This method can flexibly set routing transmission information, thereby facilitating dynamic adjustment of routing and being flexibly applicable to complex application scenarios in which the physical position of a processing core can be dynamically changed.

The invention relates to a task congestion processing method and device, a control system, a vehicle, a storage medium, a program product and a chip system, and the method comprises the steps that a first processor obtains information generated when a second processor executes a task from a shared memory; the first processor judges whether the task operated by the second processor is congested or not based on the information; and the first processor outputs prompt information of congestion of the second processor under the condition that the tasks operated by the second processor are congested. The method is used for automatically detecting the running state of the multi-core system.

The invention discloses a heterogeneous multi-core system, a vehicle-mounted application operation method, computer equipment and a computer readable storage medium, the heterogeneous multi-core system comprises a plurality of processors, at least one processor is provided with a high computing power system, and at least another processor is provided with a low computing power system. A mathematics arithmetic unit service module is deployed on the high computing power system, mathematics arithmetic unit services are published through a service oriented architecture (SOA), and the mathematics arithmetic unit services comprise a basic mathematics arithmetic service and an enhanced mathematics arithmetic service; and the low computing power system subscribes to the mathematics arithmetic unit service through a service oriented architecture (SOA). Through the computing power deployment, if the application deployed in the low computing power system has a high computing requirement, a plurality of applications do not need to be specially added and deployed on the high computing power system, so that the development workload is greatly reduced; and there is no need to deploy applications and construct inter-core communication protocols in high and low computing power systems, thereby simplifying the software architecture.

The present disclosure provides a task mapping method, comprising: determining multiple layers of second matrices based on a first matrix, wherein each layer of the second matrix is ​​divided into at least one second sub-matrix; wherein the elements in the second matrix of the N+1th layer correspond one-to-one to multiple second sub-matrices of the Nth layer, and the second sub-matrix of the 1st layer is a sub-matrix of the first matrix; determining the operation instructions corresponding to each second sub-matrix; mapping at least one second sub-matrix in each layer of the second matrix and the operation instructions corresponding to the second sub-matrix to multiple processing cores in a many-core system, wherein each processing core corresponds to a second sub-matrix and a corresponding operation instruction, so that the processing core calculates the transpose of its corresponding second sub-matrix according to its corresponding operation instruction and stores the calculation result; wherein N is a positive integer. The present disclosure also provides a task processing method, a processing core, and an electronic device.

The invention discloses an AI virtual employee system based on multi-modal deep learning and an implementation method. The system comprises a multi-modal fusion processing module, which is used for carrying out cross-modal fusion processing on multi-modal input data input by a user by adopting a multi-head attention mechanism of a Transform architecture; the role customization engine constructs AI employee roles according to specific post requirements of the user; the knowledge graph construction module is used for constructing structured knowledge representation of professional knowledge of the construction industry; the task understanding and planning module is used for analyzing user requirements and making an execution plan for an AI employee role according to the fused multi-modal data and the structured knowledge representation of the professional knowledge of the construction industry; the main execution controller is used for the AI employee role to coordinate each function module to complete a specific task according to the execution plan; the enterprise system integration interface is used for carrying out data interaction and function calling with an enterprise core system; and the result output module is used for outputting an execution result of the execution plan.

This invention provides a parallel replay method and system, relating to the field of Internet technology, comprising: acquiring all gateway log files and synchronizing them to a replay system database; parsing the gateway log files according to a specified date using multiple threads to obtain original transaction information and registering it to the replay system database; segmenting all transactions corresponding to the gateway log files by time and replaying them in chronological order; acquiring the original transaction data and sending request messages to the new core system through the replay system to obtain new response messages and response results; configuring a transaction parameter table, assembling comparison expressions based on the transaction parameter table, and comparing the response messages returned by the old and new core systems; configuring and maintaining statistical SQL, executing the statistical SQL in both the old and new core systems, and comparing the statistical results. This invention enables the system to accommodate two core business models through technical means and also allows for the verification of the new core system's functionality through parallel replay, reducing the workload of manual testing.

The invention relates to the technical field of computers, and provides a multi-core system starting task processing method and device, equipment and a storage medium, and the method comprises the steps: obtaining a processing instruction for a multi-core system starting task; in response to a processing instruction, performing topology analysis on the starting task to obtain a task type of the starting task; based on the task type, determining a target processing core for the starting task; the target processing core comprises a first processing core and a second processing core, and the performance of the first processing core is higher than that of the second processing core; based on the target processing core, processing the starting task to obtain a processing result for the starting task; the processing result is used for starting the multi-core system. According to the method, the starting tasks are allocated to different processing cores for parallel processing, so that the problems of low efficiency and low multi-core resource utilization rate caused by serial processing of a plurality of processing cores in related technologies can be solved, and the starting time of the multi-core system is effectively shortened.

The application provides a task execution time stamp recording method for simulating data communication of a multi-core system, which comprises the following steps: when an operation state control unit busy signal is valid, a clock timing unit records a current task ID, records a task interval clock timer count value, and stops and clears the task interval clock timer count; a task execution clock timer count is started; when a task execution state signal changes, a task execution clock timer count value is recorded and cleared, and the count value of each state is sent to a time stamp information arrangement unit; when the task execution state jumps from a write-back state to an idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started, and a relative task ID is updated to the current task ID. The application realizes recording of multiple time stamps, and according to the recorded relative time stamp information, the order of task execution of a task in each core and the occupation time of each state can be recovered, thereby assisting in simulating a multi-core system data communication process.

A method for rapid data exchange between real-time and time-sharing systems. Different cores on a single processor work together to share hardware resources equally, improving overall system performance and efficiency. This not only meets real-time requirements and a large number of application computing requirements, but also reduces investment costs. A simple shared memory and signal notification mechanism is used between multi-core systems to increase data transmission bandwidth and efficiency, while also taking into account real-time and large data volume requirements. Real-time data processing and high-bandwidth data transmission are met. Through address bus communication, FPGAs can process large amounts of data in parallel and in real time, accelerating the data transmission process. The number of memory copies from kernel mode to user mode is reduced, eliminating unnecessary duplication during data transmission, thereby improving performance and reducing resource usage. A high-speed, large-capacity, real-time data interaction method is designed for the entire process, from data reception to processor processing, operating from the same memory area from start to finish.

The application discloses a method and system for real-time synchronization and efficient query of insurance policies. The method comprises the following steps: real-time monitoring of changes in policy-related tables in the core database through the CDC capability built-in DTS to generate an event stream containing operation semantics; sending the event stream to Kafka, and then reading and writing the event stream into a MySQL queue table by a Kafka consumer; performing timed deduplication and merging on the events in the MySQL queue table, giving priority to the deletion operation, and synchronizing the merged policy data to an Elasticsearch index; and providing multi-condition combination query and multi-dimensional aggregation statistical services based on the Elasticsearch index. The technical solution realizes real-time synchronization of policy data without affecting the stability of the core system, and provides high-performance multi-condition query and multi-dimensional aggregation statistical capabilities to meet the requirements of the front-end sales tools for query performance and response speed.

The present disclosure discloses a method, device and related product for performing an operation task on a multi-core system. The device can be included in a combined processing device as a processing device, and the combined processing device can further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected with the computing device and the processing device respectively, for storing data of the computing device and the processing device. The scheme of the present disclosure provides a method for performing an operation task on a multi-core system, which can effectively reduce data access and improve processing efficiency.

Provided in the present disclosure is a method for storing a coherence directory. A multi-core system comprises N processing cores, N being an integer greater than 1. The method comprises: acquiring access information of a plurality of data blocks, wherein the access information comprises address information of each data block and accessor information of the data block; and on the basis of the access information of the plurality of data blocks, generating one storage entry of a coherence directory, wherein the storage entry comprises: a plurality of address fields, which correspond to the plurality of data blocks on a one-to-one basis and are used for carrying the address information of the plurality of data blocks, and an accessor information field, which is used for representing accessor information of the plurality of data blocks. Further provided in the present disclosure are a multi-core system, an electronic device, a computer-readable medium and a computer program product.

This invention discloses a log collection method, apparatus, device, and medium for a multi-core system. The method is executed by the master core and multiple slave cores in a multi-core system, including: writing log strings into a buffer in the shared memory of the slave cores and generating log descriptors; writing the log descriptors into a lock-free circular queue; monitoring the state count value of the lock-free circular queue in real time by the master core, and obtaining a target log descriptor when the lock-free circular queue is determined to be non-empty; determining a target buffer in the shared memory of the slave cores and transferring the log strings in the target buffer to the master core memory; and determining that the log upload conditions are met based on a timer or master core memory usage, determining at least one target master core memory block in the master core memory and uploading the log strings in the target master core memory block. This technical solution can improve log writing efficiency and log upload real-time performance in high-concurrency scenarios of multi-core systems.

The invention discloses a multi-core system and a debugging management device and method of the multi-core system, and is applied to the technical field of circuits, and the multi-core system comprises a scheduler which is connected with each processor and is used for carrying out enabling control on a tracking debugging function of each processor based on trigger information and sending received tracking debugging information to a filter; based on the trigger information, selecting various filtering rules currently started by the filter; and the filter is connected with the scheduler and used for filtering the received tracking debugging information based on the currently started filtering rules so as to discard the tracking debugging information which does not pass through the filtering rules in the tracking debugging information and output the tracking debugging information which passes through the filtering rules in the tracking debugging information. By means of the scheme, debugging management of the multi-core system can be effectively achieved, loss of key trace information is avoided, flexibility is high, and rapid transmission and processing of the trace information can be achieved.

Embodiments of the present application provide a multi-core system display method, a multi-core system, an electronic device and a storage medium. In some embodiments, the multi-core system display method can include the following steps: in response to the first core system being started, drawing first image data to a first sub-layer of a first display layer, and drawing mask data to a second sub-layer of the first display layer; in response to establishing a heartbeat connection with the second core system, determining whether the video transmission chip receives second image data output by the second core system; in response to the video transmission chip receiving the second image data, drawing the second image data forwarded by the video transmission chip to a second display layer, and removing the mask data in the second sub-layer; and outputting display data according to the first display layer and the second display layer.

The invention relates to the technical field of computers, and particularly provides a data scheduling method and device in a many-core system, and the method comprises a task redundancy assessment scheduling unit which carries out task redundancy assessment, and the task redundancy assessment scheduling unit comprises an assessment unit, a network configuration unit and a competition data scheduling unit; the host sends the layout coordinates of the network-on-chip operators of the application program, the parameter sizes of the operators and the dependency relationship of the operators to the evaluation unit; the network configuration unit configures a network-on-chip according to the operator layout coordinates and sends corresponding operator instructions and execution data to corresponding network nodes, and meanwhile, the evaluation unit evaluates according to the parameter quantity of each operator; and the competition data scheduling unit judges the path redundancy of each branch and controls the operator data priority of the data competition node. Compared with the prior art, the execution progress of subsequent operators can be guaranteed, and then the execution efficiency of the application program is improved.

The invention discloses a shared debugging terminal implementation method and a shared debugging terminal implementation system for an asymmetric multi-processing system. The shared debugging terminal implementation method and the shared debugging terminal implementation system have the following beneficial effects: (1) a plurality of cores share a single physical serial port through a shared memory area and a central routing agent; (2) each sub-region in the shared memory region comprises a core identifier region, so that a core identifier can be automatically added to each piece of debugging information to ensure that the source of the debugging information is clear, and the debugging efficiency is improved; (3) the method does not depend on a complex network protocol stack, so that the method can work reliably even at the initial stage of system starting or when the system crashes, and the debugging reliability is improved; (4) the resource occupation is less, and the debugging requirement of the multi-core system can be met by only needing one physical serial port and other types of interfaces; and (5) the method also has a failover mechanism, and when the main routing agent fails, the main routing agent can be automatically switched to the standby agent, namely, the main routing agent is automatically switched to the new central routing agent, so that the normal work of a debugging function is better ensured.