274 results about "Core system" patented technology

The invention discloses a method and device for executing an operation task on a multi-core system and a related product. The device may be included as a processing device in a combined processing device, which may further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete computing operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the processing device and used for storing data of the computing device and the processing device. According to the scheme, the method for executing the operation task on the multi-core system is provided, data memory access can be effectively reduced, and the processing efficiency is improved.

The invention discloses a memory partition-based dynamic instruction conversion memory access conflict optimization method, which comprises the following steps of: allocating memory sub-regions for each computing core according to a load condition in an ARM (Advanced RISC Machines) many-core system to establish a first mapping relation table; when the executable file is loaded and executed in a dynamic instruction conversion mode, obtaining a second mapping relation table between the thread and the calculation core, and obtaining a thread and a memory address corresponding to a to-be-converted instruction of a memory access instruction class, obtaining a converted first ARM virtual address and a related first address space according to the first mapping relation table and the second mapping relation table, and determining an adjustment mode of the converted instruction according to the relation between the first ARM virtual address and the first address space to complete instruction conversion. The memory access conflict in the dynamic conversion process from the x86 instruction to the ARM instruction on an ARM many-core system is effectively reduced, and the execution performance of a program after dynamic instruction conversion is improved.

The invention discloses a multi-core-particle layout optimization method and device based on a multi-objective optimization algorithm. The method comprises the following steps: respectively constructing objective optimization functions and constraint conditions of core particle temperature, inter-core-particle transmission delay, total area and inter-core-particle communication power consumption; based on the constraint conditions, performing iterative solution on the target optimization functions by using an NSWOA algorithm to respectively obtain Pareto leading edge surfaces of the target optimization functions; determining a compromise solution by using an MHA algorithm based on the Pareto leading edge surface; and determining the placement positions of the core particles according to the compromise solution, adjusting the directions according to the pin functions and the connection requirements between the functional modules, and obtaining the result of the minimum total wiring length according to the shortest total interconnection line length, thereby obtaining the optimal layout of the multiple core particles. According to the method, the performance and the integration degree of a multi-core system in 2.5 D packaging can be effectively improved by optimizing the multi-core layout.

The invention aims to provide a communication method of a multi-core system and the multi-core system, and relates to the technical field of computers. The method applied to the Mailbox hardware module in the multi-core system comprises the following steps: receiving an operation configuration instruction of a processor core to the Mailbox hardware module; under the condition that an interrupt trigger signal of the processor core corresponding to the source address is received, sending an interrupt request signal to the processor core corresponding to the destination address according to a communication channel expected to be used so as to transmit the data to be sent until a first preset condition is met, and sending a source interrupt signal to the processor core corresponding to the source address; the first preset condition is that the communication channels of the mailbox source registers recording the source addresses are all used, and the destination addresses recorded by the mailbox target registers of the communication channels are all transmitted. Therefore, the communication concurrency and throughput of the multi-core system can be improved. And meanwhile, the communication reliability of the multi-core system can be improved.

The embodiment of the invention discloses a data processing method of a multi-core system, a cluster, a cache and a system, the method is applied to a target processor cluster of the multi-core system, and the method comprises the following steps: obtaining a target atomic instruction which is used for carrying out modification operation on data of a target address to be accessed, the target address is an address in the last level of cache LLC of the multi-core system; a first exclusive read request and a first exclusive write request corresponding to a target atomic instruction are sent to LLC to modify data of a target address, the first exclusive read request comprises the target address, and the first exclusive write request comprises the target address and modified data. According to the technical scheme, the exclusive read-write request corresponding to the target atomic instruction can be sent to the LLC, the data of the target address can be modified, the situation that the LLC cannot execute the target atomic instruction due to the limitation of the data type or the data width is avoided, and hardware synchronization between different cores in the multi-core system is guaranteed.

The invention belongs to the field of computer operating systems, and aims to provide a computing resource allocation method, system and equipment for a multi-core system and a medium. According to the method, the computing resources with the specified size are divided to serve as the reserved computing resources, the specified computing resource occupancy rate of each service in the multi-core system is calculated, and when the specified computing resource occupancy rate of any service is larger than the computing resource occupancy rate threshold value, certain computing resources are allocated to the service in the reserved computing resources. And normal operation of the business is facilitated. Based on the method and the device, each service can occupy the reserved computing resources according to the own specified computing resource occupancy rate, so that the jitter of other services caused by overhigh sudden specified computing resource occupancy rate of one service can be prevented, and the problem of mutual interference among the computing resources of the services is further avoided; and the stability of the multi-core system is improved.

The invention discloses a multi-kernel system real-time task scheduling method, system and device based on scene differentiation and a storage medium, and the method comprises the following steps: carrying out the dependency analysis of a task set, and obtaining a task dependency directed graph between tasks; based on the task dependency digraph, determining a regulation and control energy level index corresponding to each task; converting the task dependency directed graph into a task situation graph; determining a scheduling sequence table of the tasks based on the task situation chart and the regulation and control energy level indexes; and allocating real-time tasks to the multi-kernel system based on the scheduling sequence table. The method can be widely applied to the technical field of task scheduling.

The invention discloses a multi-machine multi-card distributed training optimization system and method oriented to a credential heterogeneous environment, and relates to the technical field of distributed training. In order to solve the defects existing in distributed training in a credential and credential heterogeneous environment, the system comprises an application layer for receiving a training task; the core system layer comprises a self-adaptive task scheduling module, a hybrid communication topological optimization module and a dynamic check point and elastic recovery control module, and the scheduling module generates a performance portrait and an optimal scheme based on a training task and adjusts the scheme according to a node fault; the optimization module executes the scheme, firstly detects node topology, constructs a hierarchical path, loads and initializes an optimal communication rear end for target equipment, and synchronizes the path to the target equipment; the control module periodically stores a complete training context and realizes reliable recovery of a training process; the credential hardware abstraction layer is used for providing a uniform interface for realizing underlying resource access and data acquisition; and the hardware resource layer comprises heterogeneous computing nodes and an RoCE network switch.

The invention discloses a core particle system architecture, which comprises a system management core particle, a functional core particle, an interconnection core particle and an IO core particle, the system management core particle is used for monitoring the working state of each functional core particle; the system management core particle is used for receiving externally input tasks and distributing the tasks to the functional core particles according to the working states of the functional core particles; the functional core particles are used for executing tasks distributed by the system management core particles; the interconnection core particles are used for realizing communication between the system management core particles and the functional core particles and among the functional core particles; and the IO core particle is used for realizing communication between the system management core particle and the outside. The core particle system architecture provided by the invention is comprehensive in function, high in flexibility, strong in reliability, good in compatibility and capable of effectively fusing wide core particle resources, and has a wide application prospect in a high-performance electronic system.

The invention provides a neural network training method and device, electronic equipment and a storage medium, the method is applied to a first processing component, at least one network layer of a neural network is deployed on each processing component, and the method comprises the following steps: in a forward propagation process, processing first training data input into the first processing component in a current sub-batch, the first result data is output, a first activation value of the first processing part in the current sub-batch is stored in a first storage space of the first processing part or a second storage space of the second processing part, the first processing part is in communication connection with the second processing part, and the second processing part is not the first processing part; and in the back propagation process, training the neural network according to the first gradient data input into the first processing part in the current sub-batch and the first activation value read from the first storage space or the second storage space. According to the embodiment of the invention, the storage balance among the processing components in the many-core system can be realized.

The invention discloses an ARM (Advanced RISC Machines) many-core-oriented x86 instruction conversion data synchronization optimization method, which comprises the following steps of: when a multi-thread executable file is executed in a dynamic instruction conversion mode, constructing a data synchronization optimization module in an ARM many-core system, inserting a synchronization instruction by a program flow analysis unit according to a program flow analysis result, and executing the multi-thread executable file according to the synchronization instruction. A data synchronization window manager inserts a synchronization instruction for a function and a related shared data instruction according to data synchronization related function execution time, and a synchronization instruction combination optimization unit combines the inserted synchronization instruction to realize data synchronization and optimization of an ARM instruction sequence obtained by conversion. According to the method, the performance and the efficiency of data synchronization of the x86 program in the ARM many-core system are improved, the synchronization overhead is reduced, the correctness of program execution and the data consistency are ensured, and an innovative solution is provided for efficient operation of a cross-architecture program.

Embodiments of the present disclosure provide a random verification method and apparatus, an electronic device, and a computer readable storage medium. The method comprises: randomly generating a stimulus unit for random verification, wherein the stimulus unit comprises at least one request instruction; storing the request instruction in a preset storage queue, and recording a storage location identifier of the request instruction in the storage queue; on the basis of the storage location identifier, determining whether there is a port capable of receiving the request instruction; when there is a port capable of receiving the request instruction, sending the request instruction to the port capable of receiving the request instruction; when all request instructions of the stimulus unit are sent and reply information is received, performing comparative detection on the sent request instructions and the reply information; and on the basis of the comparative detection result, verifying whether data interaction of a multi-core system is normal.

According to an embodiment, a method for scheduling preemption in a multi-core system is proposed. The method includes generating a plurality of task requests, each task request corresponding to a job to be executed by an auxiliary processor and having a respective priority level; storing the plurality of task requests in the shared memory; selecting a first task request from the plurality of task requests stored in the shared memory with a highest priority level; communicating the first task request to the auxiliary processor; suspending an execution of a current task in response to receiving the interrupt signal; retrieving the respective priority level of the first task request; adding the first task request and its respective priority level to an execution queue; and executing a task from the execution queue having a highest priority.

The invention discloses a management and maintenance method and system for a heterogeneous multi-core processor of a spaceborne computer, and relates to the technical field of space scientificity, and the method comprises the following steps: configuring a global addressing controller through a main core in a power-on initialization stage, and executing address access authority distribution of a heterogeneous multi-core processor core; on the basis of combination of a sub-core storage partition strategy and a heartbeat monitoring reset mechanism, a master core periodically detects the state of a slave core and executes reset operation, and lightweight fault-tolerant management of a heterogeneous multi-core processor is achieved to guarantee continuous operation of a multi-core system under local faults; according to the method, radiation-induced storage errors are corrected based on a master core read-back refreshing strategy, slave core access behaviors are restrained through an address space locking mechanism, a master-slave collaborative reliability maintenance system is formed to ensure on-orbit stable operation of the spaceborne computer, and continuous and stable operation of the heterogeneous multi-core processor of the spaceborne computer in a complex space environment can be ensured.

Embodiments of the present application disclose a geometry processing method and apparatus, a device, a storage medium, and a program product. The method is applied to a multi-GPU core system. The method comprises: on the basis of the number of tasks and a task size, configuring a plurality of GPU cores as one or more core groups; and by means of a core in one core group, executing a geometry processing task corresponding to the core group in parallel, wherein one core group comprises one or more cores, and one core group executes one geometry processing task.

The invention discloses an instruction stream feature recognition-based instruction conversion memory access conflict optimization method, which comprises the following steps of: in a process of pre-executing an executable file in an ARM (Advanced RISC Machines) many-core system in a dynamic instruction conversion manner, determining shared memories among processes by adopting instruction stream analysis to form a first shared memory list, and on the basis, determining the memory access conflict among the processes; the executable file is loaded and executed again, the memory access type to-be-converted instruction with the memory address located in the first shared memory list is converted into an instruction sequence composed of a locking instruction sequence, a second ARM instruction sequence and an unlocking instruction sequence, and meanwhile conversion execution of the executable file is completed based on a cache consistency protocol. The memory access conflict of the x86 program on the ARM many-core system is obviously reduced, and powerful support is provided for realizing high-performance dynamic instruction conversion.

The invention provides a resource allocation method and device, electronic equipment and a storage medium, the method is applied to a many-core system, the many-core system comprises a plurality of processing cores, each processing core comprises multiple types of hardware resources, and the method comprises the following steps: constructing a resource map according to the hardware resources of the many-core system; according to the execution process of a target task, the target task is divided into a plurality of task stages based on the resource demand change, and the resource demand of each task stage for different types of hardware resources is different; according to the resource demand quantity of each task stage, the resource map corresponding to the hardware resources is divided, the resource group allocated to each task stage is determined, and the resource group comprises multiple types of hardware resources, so that different types of resource allocation can be performed according to the resource demand quantity of different task stages, and the resource allocation efficiency is improved. Resource allocation is more flexible, and the resource utilization rate is improved.

The invention provides a multi-core system security enhancement method and system based on a watchdog, the method and the system are applied to a multi-core system, the multi-core system comprises a plurality of processors, a watchdog timer correspondingly configured for each processor and a cloud platform, and the plurality of processors are paired pairwise to serve as a detection group; the method comprises the following steps: for each detection group, when a first processor executes a dog feeding operation of a watchdog timer, performing state monitoring on a second processor to obtain a monitoring result; the first processor judges whether the second processor breaks down or not according to the monitoring result; if the second processor breaks down, the first processor obtains fault information corresponding to the second processor and sends the fault information to the cloud platform; and the cloud platform repairs the second processor according to the fault information. According to the scheme, the safety and reliability of the multi-core system can be improved.

The invention relates to the technical field of multiple cores, in particular to a multi-core system and a dynamic cache coherency method.In the system, a mode adjuster collects the access condition of each core in a multi-core processor to a private cache region under a first cache coherency protocol; an applicable second cache consistency protocol is determined, and an adjustment instruction is sent to the consistency controller; the consistency controller mainly comprises a plurality of control sub-modules for different cache consistency protocols, and is designed in a modularized and reconfigurable manner, so that protocol switching is facilitated, and common logic is reasonably reused to reduce the actual overhead of hardware logic; and the consistency controller is used for starting the control sub-module corresponding to the second cache consistency protocol indicated by the adjustment instruction, so that the plurality of cores realize cache consistency among the plurality of cores through the control sub-module started by the consistency controller, thereby dynamically adjusting the cache consistency protocol, solving the limitation of a static consistency protocol, and improving the cache consistency of the plurality of cores. And the cache consistency performance and efficiency of the multi-core system are improved.

The invention belongs to the technical field of heterogeneous multi-core system application, and particularly relates to an energy consumption sensing task scheduling method under reliability constraint. Comprising the following steps: constructing a heterogeneous multi-core system model which comprises a task model, an energy consumption model and a reliability model; based on the heterogeneous multi-core system model, determining execution priorities of tasks; performing first-stage task copying on the task to ensure that the reliability value of each sub-task is higher than the reliability requirement of the system, and obtaining an initial task copy number; if the actual reliability value of the system is smaller than the reliability requirement of the system, performing second-stage task copying on the task to obtain a final task copy number; all task copies are distributed to corresponding processor cores according to execution priorities of tasks, and then the processor cores are switched from an idle mode to a sleep mode according to DPM technology use conditions so as to reduce power consumption; according to the method, the joint optimization scheduling of reliability and low power consumption of the heterogeneous multi-core system is realized, and the method has a wide application prospect in the heterogeneous multi-core system.

The invention provides a data access method and device, electronic equipment and a computer readable storage medium, the method is applied to a first processing core in a plurality of processing cores of a many-core system, and a target neural network is deployed in the plurality of processing cores of the many-core system. The method comprises the following steps: acquiring an association relationship between a virtual storage address in a virtualization domain of a hierarchical shared storage architecture of a software ecosystem for deploying a target neural network and a physical storage address in a processing core of a many-core system; in response to the received first data access request, a first virtual address is obtained, and the first virtual address represents a virtual storage address to be accessed by the first data access request; determining a physical storage address corresponding to the first virtual address as a first physical address based on the association relationship; and executing an access operation of the first data access request on the first physical address. According to the embodiment of the invention, the many-core system can be quickly integrated into the current AI software ecological system.

Systems and techniques for selectable slice mapping in shared cache levels are described. In one example, a processor includes a cache system having a shared cache level of a hierarchy of cache levels and slice hashing circuitry associated with the shared cache level. The shared cache level includes multiple slices accessible by threads running on multiple processor cores. The slice hashing circuitry assigns memory addresses used by a particular thread to a subset of the multiple slices closest to the processor core on which the thread runs. The assignment of the slice subset is based on the latency requirements or the data usage of the thread in at least one implementation. The described techniques improve tail latencies for multiple core systems and alleviate the need for additional interconnections for shared cache levels.

The present invention relates to the field of computer storage system structures. Disclosed is a heterogeneous multi-core system memory access management method for a deep neural network (DNN). According to the present invention, a CPU-GPU heterogeneous multi-core system is used to accelerate training of a DNN model, and a memory access controller is designed on the basis of the memory access characteristics of the CPU-GPU heterogeneous multi-core system; the last level cache shared by multiple cores is unloaded, prefetched, and released in the DNN training process; the data transmission process is fine-grained; and the utilization rate of the last level cache is significantly increased. In addition, a latency hiding mechanism is also designed for the memory access controller, and the access process and the calculation process of a large amount of intermediate data of a feature extraction layer are overlapped, so that the calculation performance loss caused by the last level cache miss and waiting of a DRAM memory access response in the model calculation process is reduced, improving the training efficiency.

The invention discloses a parallel compiler compiling method and system supporting multiple operating systems, which can fully utilize the advantages of a multi-processor or multi-core system and process a plurality of compiling tasks at the same time by acquiring a parallel compiling file, thereby greatly shortening the compiling time. The parallel compiling can significantly improve the compiling speed of large files, especially for complex software projects, the development cycle can be accelerated, and the development efficiency can be improved. A main function node is transformed, AST tree nodes corresponding to operating system interfaces are generated in combination with parallel compiling parameters, and then the AST tree nodes are inserted into an AST tree for node transformation operation, so that compiled files can run on a plurality of operating systems. According to the method, the barrier between different operating systems is broken, a developer does not need to independently write and maintain codes of different versions for each operating system, and the development and maintenance cost is reduced. The method allows adjustment according to different parallel compilation parameters to adapt to various compilation requirements.

The invention discloses a protection control device virtualization automatic modeling and verification method and system, and belongs to the technical field of power system relay protection, and the method comprises the following steps: creating a system management process as a resident process for providing a core system management function, comprising a multi-device process management and guard module and a virtual device creation and management module, a static configuration model file is loaded, and the static configuration model file serves as an external configuration model, describes the capacity of an actual physical device and is used for creating a corresponding virtual device process; the method comprises the following steps: virtualizing a relay protection device into an independent virtual device process, and realizing a plurality of board cards contained in the relay protection device into a plurality of threads of the virtual device process; and injecting dynamic data for assisting in verifying and testing the dynamic characteristics and service functions of the virtual device process.

The present invention is related to a method and a computer program code for handling requests in a multi-core system. In a first step, a request for a globally shared resource is received (S1) from a task belonging to a processing core. In case a FIFO queue associated with the globally shared resource is empty, the request is satisfied (S2). In case the FIFO queue associated with the globally shared resource is not empty, the request is queued (S4) in the FIFO queue. When the queued request reaches the head of the FIFO queue, the task is treated (S6) as eligible to enter the respective critical section. The invention is further directed towards a multi-core system using such a method.

The invention discloses a service processing method, device and equipment for multiple processing cores, relates to the technical field of electronics, and is used for improving the speculation accuracy in a multi-core system so as to improve the service processing performance. The method comprises the steps that a first processing core obtains first operation information, wherein the first operation information is obtained when the first processing core operates a first service; the first processing core receives second operation information from the second processing core, wherein the second operation information is obtained when the second processing core operates a second service; and when it is determined that the first service and the second service are at least partially identical according to the first operation information and the second operation information, the first processing core operates the first service according to the second operation information. The second operation information is the operation information obtained by the actual operation of the second processing core, and the first service and the second service are partially the same, so that the first processing core operates the first service according to the second operation information, and the speculation accuracy and speculation efficiency can be greatly improved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a DDR3 self-test circuit based on an FPGA in a core particle system and a method of the DDR3 self-test circuit. Comprising a power supply module, a reset module, a clock module, an FPGA chip, a JTAG downloading module, a PC upper computer and a DDR3 memory. The FPGA chip is respectively connected with the power supply module, the reset module, the clock module, the JTAG downloading module and the DDR3 memory, and the PC upper computer is connected with the JTAG downloading module; wherein the FPGA chip comprises a BIST circuit, a hardware analyzer ILA and a memory interface generator MIG; wherein the BIST circuit is connected with the hardware analyzer ILA and the memory interface generator MIG; the BIST circuit comprises a BIST controller, an address generator, a vector generator, a control signal generator, a comparator and a selector MUX; switching of various test algorithms can be realized through the dynamic test circuit module, so that the flexibility is improved, the test efficiency is improved, and the test cost is reduced.

The embodiment of the invention provides a system on chip, a computer system, a data sharing method and a data sharing device, and belongs to the technical field of computers. The system on chip comprises a processor core cluster comprising a plurality of processor I P cores, a tight coupling memory comprising a plurality of memory units, an interconnection module used for establishing a first connection channel between the processor I P cores and the interconnection module for each processor I P core, and a second connection channel for establishing a second connection channel between the processor I P cores and the interconnection module for each processor I P core, and determining a target storage unit corresponding to each processor IP core in the plurality of storage units according to a pre-configured target mapping relationship, and establishing a second connection channel between the interconnection module and the target storage unit, so that the processor IP core accesses target data of the target storage unit according to the first connection channel and the second connection channel. Compared with a traditional integration mode, according to the embodiment of the invention, the tight coupling memory is no longer private for the processor I P core, so that the implementation difficulty of multi-core data sharing in the multi-core system is reduced.