120 results about "Multicore systems" patented technology

The invention aims to provide a communication method of a multi-core system and the multi-core system, and relates to the technical field of computers. The method applied to the Mailbox hardware module in the multi-core system comprises the following steps: receiving an operation configuration instruction of a processor core to the Mailbox hardware module; under the condition that an interrupt trigger signal of the processor core corresponding to the source address is received, sending an interrupt request signal to the processor core corresponding to the destination address according to a communication channel expected to be used so as to transmit the data to be sent until a first preset condition is met, and sending a source interrupt signal to the processor core corresponding to the source address; the first preset condition is that the communication channels of the mailbox source registers recording the source addresses are all used, and the destination addresses recorded by the mailbox target registers of the communication channels are all transmitted. Therefore, the communication concurrency and throughput of the multi-core system can be improved. And meanwhile, the communication reliability of the multi-core system can be improved.

The embodiment of the invention discloses a data processing method of a multi-core system, a cluster, a cache and a system, the method is applied to a target processor cluster of the multi-core system, and the method comprises the following steps: obtaining a target atomic instruction which is used for carrying out modification operation on data of a target address to be accessed, the target address is an address in the last level of cache LLC of the multi-core system; a first exclusive read request and a first exclusive write request corresponding to a target atomic instruction are sent to LLC to modify data of a target address, the first exclusive read request comprises the target address, and the first exclusive write request comprises the target address and modified data. According to the technical scheme, the exclusive read-write request corresponding to the target atomic instruction can be sent to the LLC, the data of the target address can be modified, the situation that the LLC cannot execute the target atomic instruction due to the limitation of the data type or the data width is avoided, and hardware synchronization between different cores in the multi-core system is guaranteed.

The invention belongs to the field of computer operating systems, and aims to provide a computing resource allocation method, system and equipment for a multi-core system and a medium. According to the method, the computing resources with the specified size are divided to serve as the reserved computing resources, the specified computing resource occupancy rate of each service in the multi-core system is calculated, and when the specified computing resource occupancy rate of any service is larger than the computing resource occupancy rate threshold value, certain computing resources are allocated to the service in the reserved computing resources. And normal operation of the business is facilitated. Based on the method and the device, each service can occupy the reserved computing resources according to the own specified computing resource occupancy rate, so that the jitter of other services caused by overhigh sudden specified computing resource occupancy rate of one service can be prevented, and the problem of mutual interference among the computing resources of the services is further avoided; and the stability of the multi-core system is improved.

The invention discloses a multi-core scheduling system and method based on interrupt affinity and a storage medium. The technical problem that data locality guarantee and load balancing are difficult to consider at the same time is solved by constructing a self-adaptive optimization closed loop of perception-decision-execution-feedback, and the method comprises the steps that a routing interruption configuration mechanism provides a basis for dynamic adjustment; an interrupt guide task placement mechanism ensures that an interrupt service program and an associated task are executed in the same CPU core, and the cache hit rate is increased; the execution overhead of an interrupt service program is brought into core load statistics through task context switching and a'task + ISR 'two-dimensional precise load evaluation mechanism triggered by ISR inlet / outlet double nodes, and real load awareness is achieved; a load-driven dynamic interrupt routing mechanism is combined with dual control of a hysteresis threshold and cooling time, so that a ping-pong effect is avoided. According to the method, dynamic load balancing is realized on the premise of keeping data locality, and the real-time response performance and throughput of the multi-core system are remarkably improved.

According to an embodiment, a method for scheduling preemption in a multi-core system is proposed. The method includes generating a plurality of task requests, each task request corresponding to a job to be executed by an auxiliary processor and having a respective priority level; storing the plurality of task requests in the shared memory; selecting a first task request from the plurality of task requests stored in the shared memory with a highest priority level; communicating the first task request to the auxiliary processor; suspending an execution of a current task in response to receiving the interrupt signal; retrieving the respective priority level of the first task request; adding the first task request and its respective priority level to an execution queue; and executing a task from the execution queue having a highest priority.

A device can provide a unified and scalable multiprocessor communication framework that enables communication between multiple processor cores in a multicore device. For example, the device may be configured to perform data payload management using a Smart Message Queue (SMQ) and / or shared memory. Additionally or alternatively, the communication framework may enable the processors to communicate with each other and / or peripherals of the device while abstracting details of various communication protocols, hardware interfaces, and / or the like. For example, the communication framework may provide a common interface for applications, enabling a first application associated with a processor to establish a connection to any processor and / or peripheral without knowing details of a communication protocol for each connection.

The invention discloses a management and maintenance method and system for a heterogeneous multi-core processor of a spaceborne computer, and relates to the technical field of space scientificity, and the method comprises the following steps: configuring a global addressing controller through a main core in a power-on initialization stage, and executing address access authority distribution of a heterogeneous multi-core processor core; on the basis of combination of a sub-core storage partition strategy and a heartbeat monitoring reset mechanism, a master core periodically detects the state of a slave core and executes reset operation, and lightweight fault-tolerant management of a heterogeneous multi-core processor is achieved to guarantee continuous operation of a multi-core system under local faults; according to the method, radiation-induced storage errors are corrected based on a master core read-back refreshing strategy, slave core access behaviors are restrained through an address space locking mechanism, a master-slave collaborative reliability maintenance system is formed to ensure on-orbit stable operation of the spaceborne computer, and continuous and stable operation of the heterogeneous multi-core processor of the spaceborne computer in a complex space environment can be ensured.

Embodiments of the present application disclose a geometry processing method and apparatus, a device, a storage medium, and a program product. The method is applied to a multi-GPU core system. The method comprises: on the basis of the number of tasks and a task size, configuring a plurality of GPU cores as one or more core groups; and by means of a core in one core group, executing a geometry processing task corresponding to the core group in parallel, wherein one core group comprises one or more cores, and one core group executes one geometry processing task.

The invention provides a multi-core system security enhancement method and system based on a watchdog, the method and the system are applied to a multi-core system, the multi-core system comprises a plurality of processors, a watchdog timer correspondingly configured for each processor and a cloud platform, and the plurality of processors are paired pairwise to serve as a detection group; the method comprises the following steps: for each detection group, when a first processor executes a dog feeding operation of a watchdog timer, performing state monitoring on a second processor to obtain a monitoring result; the first processor judges whether the second processor breaks down or not according to the monitoring result; if the second processor breaks down, the first processor obtains fault information corresponding to the second processor and sends the fault information to the cloud platform; and the cloud platform repairs the second processor according to the fault information. According to the scheme, the safety and reliability of the multi-core system can be improved.

Systems and techniques for selectable slice mapping in shared cache levels are described. In one example, a processor includes a cache system having a shared cache level of a hierarchy of cache levels and slice hashing circuitry associated with the shared cache level. The shared cache level includes multiple slices accessible by threads running on multiple processor cores. The slice hashing circuitry assigns memory addresses used by a particular thread to a subset of the multiple slices closest to the processor core on which the thread runs. The assignment of the slice subset is based on the latency requirements or the data usage of the thread in at least one implementation. The described techniques improve tail latencies for multiple core systems and alleviate the need for additional interconnections for shared cache levels.

The present invention is related to a method and a computer program code for handling requests in a multi-core system. In a first step, a request for a globally shared resource is received (S1) from a task belonging to a processing core. In case a FIFO queue associated with the globally shared resource is empty, the request is satisfied (S2). In case the FIFO queue associated with the globally shared resource is not empty, the request is queued (S4) in the FIFO queue. When the queued request reaches the head of the FIFO queue, the task is treated (S6) as eligible to enter the respective critical section. The invention is further directed towards a multi-core system using such a method.

The invention discloses a service processing method, device and equipment for multiple processing cores, relates to the technical field of electronics, and is used for improving the speculation accuracy in a multi-core system so as to improve the service processing performance. The method comprises the steps that a first processing core obtains first operation information, wherein the first operation information is obtained when the first processing core operates a first service; the first processing core receives second operation information from the second processing core, wherein the second operation information is obtained when the second processing core operates a second service; and when it is determined that the first service and the second service are at least partially identical according to the first operation information and the second operation information, the first processing core operates the first service according to the second operation information. The second operation information is the operation information obtained by the actual operation of the second processing core, and the first service and the second service are partially the same, so that the first processing core operates the first service according to the second operation information, and the speculation accuracy and speculation efficiency can be greatly improved.

The embodiment of the invention provides a system on chip, a computer system, a data sharing method and a data sharing device, and belongs to the technical field of computers. The system on chip comprises a processor core cluster comprising a plurality of processor I P cores, a tight coupling memory comprising a plurality of memory units, an interconnection module used for establishing a first connection channel between the processor I P cores and the interconnection module for each processor I P core, and a second connection channel for establishing a second connection channel between the processor I P cores and the interconnection module for each processor I P core, and determining a target storage unit corresponding to each processor IP core in the plurality of storage units according to a pre-configured target mapping relationship, and establishing a second connection channel between the interconnection module and the target storage unit, so that the processor IP core accesses target data of the target storage unit according to the first connection channel and the second connection channel. Compared with a traditional integration mode, according to the embodiment of the invention, the tight coupling memory is no longer private for the processor I P core, so that the implementation difficulty of multi-core data sharing in the multi-core system is reduced.

The invention provides a multi-core cache consistency maintenance method and device, electronic equipment and a storage medium, and is applied to a multi-core system comprising a plurality of nodes, the nodes comprise at least two cores, each core comprises a first-level cache, and the plurality of cores of the same node share a second-level cache comprising a directory for recording cache line states; the method comprises the steps that a request core sends a first request to a first target core; the request core and the first target core are the same or different cores in the same node; when the first-level cache of the first target core is hit and the cache line state meets the target request requirement, the request core is responded, and the original state of the cache line is maintained; when the first-level cache of the first target core is not hit or the first-level cache is hit but the cache line state does not meet the request requirement, the request core sends a second request to other cores of the same node or a second-level cache of the node; and according to a request result, responding to a request core, and adjusting cache line states in a first-level cache and a second-level cache in the node.

The present disclosure relates to the technical field of data processing, and relates to a data synchronization method, a distributed system, a computer readable storage medium and an electronic device. The data synchronization method is applied to a subsystem in a distributed system, the subsystem comprising a plurality of sub-processes and a shared memory between the plurality of sub-processes, and the data synchronization method comprises: in response to a data synchronization request, a first sub-process determining a data processing strategy according to a request type; and the first sub-process performing data synchronization on the shared memory according to the data processing strategy; wherein the first sub-process monitors a read state of old data corresponding to the data synchronization based on a timing mechanism, so as to perform invalidation processing on the old data according to the read state. The data synchronization method of the present disclosure avoids resource competition between multi-core systems, realizes data consistency of each core in the multi-core system, and guarantees the performance of the distributed system.

This application provides a method, apparatus, device, and storage medium for inter-core interaction in a multi-core system, relating to, but not limited to, the field of computer technology. The method includes: a first core determining an interaction channel group corresponding to a destination core based on a destination core for first interaction data to be transmitted; the destination core being one of at least one second core, with each second core corresponding to a specific interaction channel group; selecting a first interaction channel from a plurality of second interaction channels in the interaction channel group based on the interaction type of the first interaction data; and sending the first interaction data to the first interaction channel, so that the destination core obtains the first interaction data by listening to the interaction channel group. The apparatus, device, and storage medium are applied to the above interaction method. Embodiments of this application can simplify inter-core interaction operations and thus improve the execution efficiency of threads between multiple cores.

The invention provides a matrix multiplication calculation optimization method and device and electronic equipment. The method is applied to a multi-core system and comprises the following steps: acquiring left matrix data and right matrix data multiplied by a target matrix, and determining basic information of a network-on-chip; dividing the right matrix data into a plurality of right matrix data blocks, and storing the plurality of right matrix data blocks to the DRAM; performing feature extraction on the plurality of right matrix data blocks to obtain feature information of the plurality of right matrix data blocks, and performing feature extraction on the basic information to obtain feature information of the network-on-chip; based on the feature information of the plurality of right matrix data blocks and the feature information of the network-on-chip, determining a plurality of optimal target calculation cores from the plurality of cores; and performing parallel matrix multiplication calculation based on the plurality of target calculation cores according to the left matrix data and the plurality of right matrix data blocks to obtain a calculation result. According to the method, the parallel computing efficiency and performance of matrix multiplication can be effectively improved by dynamically distributing the computing tasks.

The invention relates to a task congestion processing method and device, a control system, a vehicle, a storage medium, a program product and a chip system, and the method comprises the steps that a first processor obtains information generated when a second processor executes a task from a shared memory; the first processor judges whether the task operated by the second processor is congested or not based on the information; and the first processor outputs prompt information of congestion of the second processor under the condition that the tasks operated by the second processor are congested. The method is used for automatically detecting the running state of the multi-core system.

The invention discloses a heterogeneous multi-core system, a vehicle-mounted application operation method, computer equipment and a computer readable storage medium, the heterogeneous multi-core system comprises a plurality of processors, at least one processor is provided with a high computing power system, and at least another processor is provided with a low computing power system. A mathematics arithmetic unit service module is deployed on the high computing power system, mathematics arithmetic unit services are published through a service oriented architecture (SOA), and the mathematics arithmetic unit services comprise a basic mathematics arithmetic service and an enhanced mathematics arithmetic service; and the low computing power system subscribes to the mathematics arithmetic unit service through a service oriented architecture (SOA). Through the computing power deployment, if the application deployed in the low computing power system has a high computing requirement, a plurality of applications do not need to be specially added and deployed on the high computing power system, so that the development workload is greatly reduced; and there is no need to deploy applications and construct inter-core communication protocols in high and low computing power systems, thereby simplifying the software architecture.

The present application provides a method, an apparatus, and a multi-core system for maintaining cache coherence. The method includes: obtaining a write pointer and an eviction pointer of a directory, where the directory includes cache line sharing information; configuring an emergency threshold and a normal threshold, and the emergency threshold is less than the normal threshold; if the sum of the write pointer and the emergency threshold is greater than the eviction pointer, setting it as a high priority and preferentially performing directory eviction; if the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, setting it as a low priority and performing directory eviction; where the directory includes the sharing information of the cache line, and directory eviction means evicting the sharing information of the least recently used cache line in the directory; repeating the above steps until the sum of the write pointer and the normal threshold is less than the eviction pointer. The present application maximally ensures that there is available space in the directory to store new data, is applicable to small systems, can also ensure directory coverage, and improves query efficiency and reduces query power consumption.

The invention discloses a dynamic self-adaptive MSMC shared storage management method and device, and the method comprises the steps: pre-configuring a static partition of an MSMC shared storage region, and dividing a physical storage region into a plurality of partitions with fixed sizes through a partition reconfiguration module; initializing parameters of the dynamic monitoring module, and starting the dynamic monitoring module to periodically acquire real-time data of each partition; and circularly executing the sub-steps of data acquisition and anomaly detection, scheduling strategy calculation, partition reconfiguration and arbitration weight updating. Through hardware-level dynamic monitoring, priority perception scheduling and a microsecond-level reconfiguration mechanism, the utilization rate of storage resources is remarkably improved, high-priority tasks are guaranteed in real time, multi-core bandwidth allocation is optimized, and the dynamic adaptability of the system is enhanced; the contradiction between resource allocation fixity and task load dynamics in a traditional static partitioning scheme is fundamentally solved, and a breakthrough solution is provided for efficient parallel processing of a multi-core DSP system in a high-real-time scene.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

The present application relates to the technical field of memory management, and discloses a memory management method for a multi-core system, a multi-core system, a device, and a medium. The method comprises: a master core unit marking initial memory management priorities of the master core unit and slave core units as a second level, the memory management priorities further comprising: a first level higher than the second level and a third level lower than the second level; determining a system operating condition; on the basis of the system operating condition and the second level, updating and determining current memory management priorities of the master core unit and the slave core units; and on the basis of a memory scheduling and allocation request sent by an applicant, the system operating condition, the type of the applicant, and a current memory management priority of the applicant, a memory manager performing memory scheduling and allocation processing, and allocating an idle memory unit to the applicant, so that the applicant executes a task in a task queue, the applicant being the master core unit or one of the slave core units. The present application can improve system memory utilization rate and ensure efficient and correct operation of the multi-core system.

A heterogeneous multi-core system to execute a real-time system of an automobile includes a plurality of system-on-chips in electronic communication with one another. Each system-on-chip includes a plurality of central processing units (CPUs) arranged into a plurality of logical domains. The heterogeneous multi-core system also includes a plurality of dispatched tasks that execute based on an execution pipeline and each perform a particular set of tasks for one of the logical domains. The plurality of dispatched tasks includes at least one offset dispatched task that executes at an offset time and a reference dispatched task that is located upstream of the execution stage of the offset dispatched task on the execution pipeline. The reference dispatched task communicates data to the offset dispatched task and the offset time represents a period of time measured relative to the reference dispatched task.

The invention relates to the technical field of computers, and provides a multi-core system starting task processing method and device, equipment and a storage medium, and the method comprises the steps: obtaining a processing instruction for a multi-core system starting task; in response to a processing instruction, performing topology analysis on the starting task to obtain a task type of the starting task; based on the task type, determining a target processing core for the starting task; the target processing core comprises a first processing core and a second processing core, and the performance of the first processing core is higher than that of the second processing core; based on the target processing core, processing the starting task to obtain a processing result for the starting task; the processing result is used for starting the multi-core system. According to the method, the starting tasks are allocated to different processing cores for parallel processing, so that the problems of low efficiency and low multi-core resource utilization rate caused by serial processing of a plurality of processing cores in related technologies can be solved, and the starting time of the multi-core system is effectively shortened.

The application provides a task execution time stamp recording method for simulating data communication of a multi-core system, which comprises the following steps: when an operation state control unit busy signal is valid, a clock timing unit records a current task ID, records a task interval clock timer count value, and stops and clears the task interval clock timer count; a task execution clock timer count is started; when a task execution state signal changes, a task execution clock timer count value is recorded and cleared, and the count value of each state is sent to a time stamp information arrangement unit; when the task execution state jumps from a write-back state to an idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started, and a relative task ID is updated to the current task ID. The application realizes recording of multiple time stamps, and according to the recorded relative time stamp information, the order of task execution of a task in each core and the occupation time of each state can be recovered, thereby assisting in simulating a multi-core system data communication process.

The present disclosure discloses a method, device and related product for performing an operation task on a multi-core system. The device can be included in a combined processing device as a processing device, and the combined processing device can further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected with the computing device and the processing device respectively, for storing data of the computing device and the processing device. The scheme of the present disclosure provides a method for performing an operation task on a multi-core system, which can effectively reduce data access and improve processing efficiency.

This invention discloses a log collection method, apparatus, device, and medium for a multi-core system. The method is executed by the master core and multiple slave cores in a multi-core system, including: writing log strings into a buffer in the shared memory of the slave cores and generating log descriptors; writing the log descriptors into a lock-free circular queue; monitoring the state count value of the lock-free circular queue in real time by the master core, and obtaining a target log descriptor when the lock-free circular queue is determined to be non-empty; determining a target buffer in the shared memory of the slave cores and transferring the log strings in the target buffer to the master core memory; and determining that the log upload conditions are met based on a timer or master core memory usage, determining at least one target master core memory block in the master core memory and uploading the log strings in the target master core memory block. This technical solution can improve log writing efficiency and log upload real-time performance in high-concurrency scenarios of multi-core systems.

The application belongs to the security field in a multi-core system chip, and discloses a security bus architecture for a multi-core Chiplet chip system, which comprises five parts of an active interposer, a function chip, a storage chip, a Core chip and a security chiplet, the Core chip contains CPU cores of the chip system, the storage chip contains a memory for storing data and codes, the function chip contains most peripherals and function IPs, the active interposer is used for connecting all the chiplets and realizing access control of the chiplets, and the security chiplet is used for controlling and managing the security configuration of the whole chip system. When the chiplet provided by a supplier cannot be trusted, the security bus architecture can realize isolation and access limitation of the non-security chiplet. The bus architecture is realized in the security active interposer, and a security chiplet is used for configuring the access permission of each chiplet in the chip system, so that the data access of the remaining chiplets can be controlled, and the system security is enhanced.

The invention discloses a multi-core system and a debugging management device and method of the multi-core system, and is applied to the technical field of circuits, and the multi-core system comprises a scheduler which is connected with each processor and is used for carrying out enabling control on a tracking debugging function of each processor based on trigger information and sending received tracking debugging information to a filter; based on the trigger information, selecting various filtering rules currently started by the filter; and the filter is connected with the scheduler and used for filtering the received tracking debugging information based on the currently started filtering rules so as to discard the tracking debugging information which does not pass through the filtering rules in the tracking debugging information and output the tracking debugging information which passes through the filtering rules in the tracking debugging information. By means of the scheme, debugging management of the multi-core system can be effectively achieved, loss of key trace information is avoided, flexibility is high, and rapid transmission and processing of the trace information can be achieved.