334 results about "Multicore systems" patented technology

A distributed processing system delegates the allocation and control of computing work units to agent applications running on computing resources including multi-processor and multi-core systems. The distributed processing system includes at least one agent associated with at least one computing resource. The distributed processing system creates work units corresponding with execution phases of applications. Work units can be associated with concurrency data that specifies how applications are executed on multiple processors and/or processor cores. The agent collects information about its associated computing resources and requests work units from the server using this information and the concurrency data. An agent can monitor the performance of executing work units to better select subsequent work units. The distributed processing system may also be implemented within a single computing resource to improve processor core utilization of applications. Additional computing resources can augment the single computing resource and execute pending work units at any time.

The present invention is directed towards systems and methods for managing a rate of request for an object transmitted between a server and one or more clients via a multi-core intermediary device. A first core of the intermediary device can receive a request for an object and assume ownership of the object. The first core can store the object in shared memory along with a rate-related counter for the object and generate a hash to the object and counter. Other cores can obtain the hash from the first core and access the object and counter in shared memory. Policy engines and throttlers in operation on each core can control the rate of access to the stored object.

A method, system, and apparatus may route an interrupt to a first core of a plurality of cores of a multi-core system. If the first core is in an idle or low power state, or operating in a power state at or below a threshold power state, a core in a least idle state may be found. The interrupt may be rerouted to and processed by the core in the least idle state. Cores in a multi-core system may be rated based on for example, power states or other characteristics, and interrupts may be assigned based on these ratings. Other embodiments are described and claimed.

The present application is directed towards systems and methods for providing link management in a multi-core system. In some embodiments, the present application describes solutions for managing address resolution in IPv4 networks in a multi-core system. In other embodiments, the present application describes solutions for managing neighbor discovery in IPv6 networks in a multi-core system. In still other embodiments, the present application describes solutions for managing network bridging in a multi-core system. In yet other embodiments, the present application describes solutions for managing link aggregation in a multi-core system. And in still other embodiments, the present application describes solutions for managing virtual routers in a multi-core system.

Described herein is a method and system for distributing request and responses across a multi-core system. Each core executes a packet engine that further processes data packets allocated to that core. A flow distributor executing within the multi-core system forwards client requests to a packet engine on a core that is selected based on a value generated when a hash is applied to a tuple comprising a client IP address, a client port, a server IP address and a server port identified in the request. The packet engine selects a first IP address and a first port of the core, and determines whether a hash of a tuple comprising those values identifies the selected core. A modification is then made to the client request so that the client request includes a tuple comprising the first IP address, the server IP address, the first port and the server port.

The present solution is directed towards systems and methods for managing cookies by a multi-core device. The device is intermediary to a client and one or more servers. A first core of a multi-core device receives a response from a server to a request of the client through a user session. The response comprises a cookie. The first core removes the cookie from the response and stores the cookie in a corresponding storage for the session. The first core forwards the response without the cookie to the client. A second core then receives via a session, a second request from the client. The second core determines the identification of the first core as owner of the session from the second request. The second core then communicates to the first core a third request for cookie information for the session.

The present invention is directed towards systems and methods for handling limit parameters for multi-core systems. A pool manager divides the limited number of uses of a resource into an exclusive quota pool and a shared quota pool. Each packet processing engine operating on a core is allocated an exclusive number of uses of the resource from the exclusive quota pool. If a packet processing engine wishes to use the resource beyond its exclusive number, the packet processing engine must borrow from the shared quota pool.

A multi-core system that includes a 64-bit cache storage and a 32-bit memory storage that stores a 32-bit cache object directory. One or more cache engines execute on cores of the multi-core system to retrieve objects from the 64-bit cache, create cache directory objects, insert the created cache directory object into the cache object directory, and search for cache directory objects in the cache object directory. When an object is stored in the 64-bit cache, a cache engine can create a cache directory object that corresponds to the cached object and can insert the created cache directory object into an instance of a cache object directory. A second cache engine can receive a request to access the cached object and can identify a cache directory object in the instance of the cache object directory, using a hash key calculated based on one or more attributes of the cached object.

The present application is directed towards systems and methods for providing a cookie by an intermediary device comprising a plurality of packet processing engines executing on a corresponding plurality of cores, the cookie identifying a session of a user that was redirected responsive to a service exceeding a response time limit. The cookie may be generated with identifiers based off a name of a virtual server managing a service of a server, and a name of a policy associated with the virtual server. Each packet processing engine of the plurality of packet processing engines may interpret cookies generated by other packet processing engines due to the name of the virtual server and name of the policy, and may provide preferred client connectivity based on cookies included in requests for access to a service.

The present application is directed towards systems and methods for managing server initiated connections via a multi-core system that provides VPN access between clients and servers. The solution described herein provides a mechanism by which server and client communications via the multi-core system for a server initiated connection may be received on different cores and for the system to manage these communications across different cores to provide an end-to-end connectivity between the client and the server.

A method and system for generating a web log that includes transaction entries from transaction queues of one or more cores of a multi-core system. A transaction queue is maintained for each core so that either a packet engine or web logging client executing on the core can write transaction entries to the transaction queue. In some embodiments, a timestamp value obtained from a synchronized timestamp variable can be assigned to the transaction entries. When a new transaction entry is added to the transaction queue, the earliest transaction entry is removed from the transaction queue and added to a heap. Periodically the earliest entry in the heap is removed from the heap and written to a web log. When an entry is removed from the heap, the earliest entry in a transaction queue corresponding to the removed entry is removed from the transaction queue and added to the heap.

A lock-free write barrier buffer is used to combine multiple writes to identical locations and save old values of written memory locations and to reduce TLB misses compared to card marking. The old value of a written location as well as the address of the header of the written object can be saved, which is not possible with card marking. Scanning the card table and marked pages are eliminated. The method is lock-free, scaling to highly concurrent multiprocessors and multi-core systems.

A debugger includes: a plurality of processor cores; and a scheduler configured to control an allocation of a plurality of basic modules to the processor cores based on an execution rule for enabling parallel execution of a program that is divided into the basic modules that are executable asynchronously with one another, the program being defined with the execution rule of the basic modules for executing the basic modules in time series, wherein the scheduler includes a break point setting module configured to set a group of break points that are designated through a graphical user interface.

Methods, storage mediums, and apparatuses for evaluating the reliability of Three-Dimensional (3D) Network-on-Chip (NoC) designs are described. The described embodiments provide a 3D NoC specific fault-injector tool which is able to model logic-level fault models of 3D NoC specific physical faults in 3D-NoC platform. These embodiments automate the whole process of static and dynamic fault injection base on the user preference and reports the specific reliability metrics for 3D NoC platform as a single tool. The described embodiments can be used for the reliability evaluation and effectiveness of fault-tolerant designs in any of the 3D-many core designs such as manycore systems in different ranges of application from embedded systems in cellphones to larger systems which can be used in next generation of autonomous cars or hypercube memory cells.

Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.

The invention relates to a task scheduling method in a multi-core DSP system. A shared task pool is established in a shared memory in the multi-core DSP system, tasks are input into the task pool, the tasks are firstly classified into two categories of time-related and non-time-related, then each task is carried out the numbering, the time-related tasks have the same serial number, the non-time-related tasks are independently carried out the numbering, the initial states of the tasks with the different serial numbers are set as the non-locked states; and a task obtaining device of each idle slave core carries out the inquiry to the shared task pool and carries out the processing of the task after obtaining the task. The task scheduling method changes the technical proposal of using a main core for distributing tasks by the traditional multi-core DSP system and adopts the method of using the slave cores to actively obtain the tasks during the idle time, which can effectively reduce the requirements on the reliability of priori knowledge and reduce the load balance of the multi-core system.

In a multi-core system, multiple packet engines across corresponding cores may be working concurrently processing data packets from data flows of SSL VPN sessions. For example, a first core may establish a SSL VPN session with a client. Any one of the other cores, such as a second core, may received packets related to the session owned by the first core. Embodiments of the systems and method described below provide management of IIP addresses for the multi-core/multi-packet engine approach to providing SSL VPN service. In some embodiments, the approach to managing IIP addresses is to have one packet engine on a core act as a master or controller of the IIPs for the remaining packet engines and cores. The packet engines/cores use a protocol for communications regarding IIP management.

Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

The present application is directed towards systems and methods for providing connection surge protection to one or more servers by an intermediary multi-core system. A packet processing engine of a multi-core device deployed as an intermediary between a plurality of clients and one or more servers determines an estimated number of total pending requests received by all packet processing engines based on a value of a local counter of received requests, the total number of pending requests received by all other packet processing engines at a last predetermined interval, and a rate of change of the total number of pending requests received by all other packet processing engines multiplied by the time since the last predetermined interval. The packet processing engine applies a surge protection policy to received pending requests responsive to the determined estimated number of total pending requests.