94 results about "Multicore systems" patented technology

The invention discloses a multi-core scheduling system and method based on interrupt affinity and a storage medium. The technical problem that data locality guarantee and load balancing are difficult to consider at the same time is solved by constructing a self-adaptive optimization closed loop of perception-decision-execution-feedback, and the method comprises the steps that a routing interruption configuration mechanism provides a basis for dynamic adjustment; an interrupt guide task placement mechanism ensures that an interrupt service program and an associated task are executed in the same CPU core, and the cache hit rate is increased; the execution overhead of an interrupt service program is brought into core load statistics through task context switching and a'task + ISR 'two-dimensional precise load evaluation mechanism triggered by ISR inlet / outlet double nodes, and real load awareness is achieved; a load-driven dynamic interrupt routing mechanism is combined with dual control of a hysteresis threshold and cooling time, so that a ping-pong effect is avoided. According to the method, dynamic load balancing is realized on the premise of keeping data locality, and the real-time response performance and throughput of the multi-core system are remarkably improved.

A device can provide a unified and scalable multiprocessor communication framework that enables communication between multiple processor cores in a multicore device. For example, the device may be configured to perform data payload management using a Smart Message Queue (SMQ) and / or shared memory. Additionally or alternatively, the communication framework may enable the processors to communicate with each other and / or peripherals of the device while abstracting details of various communication protocols, hardware interfaces, and / or the like. For example, the communication framework may provide a common interface for applications, enabling a first application associated with a processor to establish a connection to any processor and / or peripheral without knowing details of a communication protocol for each connection.

The invention discloses a management and maintenance method and system for a heterogeneous multi-core processor of a spaceborne computer, and relates to the technical field of space scientificity, and the method comprises the following steps: configuring a global addressing controller through a main core in a power-on initialization stage, and executing address access authority distribution of a heterogeneous multi-core processor core; on the basis of combination of a sub-core storage partition strategy and a heartbeat monitoring reset mechanism, a master core periodically detects the state of a slave core and executes reset operation, and lightweight fault-tolerant management of a heterogeneous multi-core processor is achieved to guarantee continuous operation of a multi-core system under local faults; according to the method, radiation-induced storage errors are corrected based on a master core read-back refreshing strategy, slave core access behaviors are restrained through an address space locking mechanism, a master-slave collaborative reliability maintenance system is formed to ensure on-orbit stable operation of the spaceborne computer, and continuous and stable operation of the heterogeneous multi-core processor of the spaceborne computer in a complex space environment can be ensured.

Systems and techniques for selectable slice mapping in shared cache levels are described. In one example, a processor includes a cache system having a shared cache level of a hierarchy of cache levels and slice hashing circuitry associated with the shared cache level. The shared cache level includes multiple slices accessible by threads running on multiple processor cores. The slice hashing circuitry assigns memory addresses used by a particular thread to a subset of the multiple slices closest to the processor core on which the thread runs. The assignment of the slice subset is based on the latency requirements or the data usage of the thread in at least one implementation. The described techniques improve tail latencies for multiple core systems and alleviate the need for additional interconnections for shared cache levels.

The present disclosure relates to the technical field of data processing, and relates to a data synchronization method, a distributed system, a computer readable storage medium and an electronic device. The data synchronization method is applied to a subsystem in a distributed system, the subsystem comprising a plurality of sub-processes and a shared memory between the plurality of sub-processes, and the data synchronization method comprises: in response to a data synchronization request, a first sub-process determining a data processing strategy according to a request type; and the first sub-process performing data synchronization on the shared memory according to the data processing strategy; wherein the first sub-process monitors a read state of old data corresponding to the data synchronization based on a timing mechanism, so as to perform invalidation processing on the old data according to the read state. The data synchronization method of the present disclosure avoids resource competition between multi-core systems, realizes data consistency of each core in the multi-core system, and guarantees the performance of the distributed system.

This application provides a method, apparatus, device, and storage medium for inter-core interaction in a multi-core system, relating to, but not limited to, the field of computer technology. The method includes: a first core determining an interaction channel group corresponding to a destination core based on a destination core for first interaction data to be transmitted; the destination core being one of at least one second core, with each second core corresponding to a specific interaction channel group; selecting a first interaction channel from a plurality of second interaction channels in the interaction channel group based on the interaction type of the first interaction data; and sending the first interaction data to the first interaction channel, so that the destination core obtains the first interaction data by listening to the interaction channel group. The apparatus, device, and storage medium are applied to the above interaction method. Embodiments of this application can simplify inter-core interaction operations and thus improve the execution efficiency of threads between multiple cores.

The invention provides a matrix multiplication calculation optimization method and device and electronic equipment. The method is applied to a multi-core system and comprises the following steps: acquiring left matrix data and right matrix data multiplied by a target matrix, and determining basic information of a network-on-chip; dividing the right matrix data into a plurality of right matrix data blocks, and storing the plurality of right matrix data blocks to the DRAM; performing feature extraction on the plurality of right matrix data blocks to obtain feature information of the plurality of right matrix data blocks, and performing feature extraction on the basic information to obtain feature information of the network-on-chip; based on the feature information of the plurality of right matrix data blocks and the feature information of the network-on-chip, determining a plurality of optimal target calculation cores from the plurality of cores; and performing parallel matrix multiplication calculation based on the plurality of target calculation cores according to the left matrix data and the plurality of right matrix data blocks to obtain a calculation result. According to the method, the parallel computing efficiency and performance of matrix multiplication can be effectively improved by dynamically distributing the computing tasks.

The invention relates to a task congestion processing method and device, a control system, a vehicle, a storage medium, a program product and a chip system, and the method comprises the steps that a first processor obtains information generated when a second processor executes a task from a shared memory; the first processor judges whether the task operated by the second processor is congested or not based on the information; and the first processor outputs prompt information of congestion of the second processor under the condition that the tasks operated by the second processor are congested. The method is used for automatically detecting the running state of the multi-core system.

The invention discloses a heterogeneous multi-core system, a vehicle-mounted application operation method, computer equipment and a computer readable storage medium, the heterogeneous multi-core system comprises a plurality of processors, at least one processor is provided with a high computing power system, and at least another processor is provided with a low computing power system. A mathematics arithmetic unit service module is deployed on the high computing power system, mathematics arithmetic unit services are published through a service oriented architecture (SOA), and the mathematics arithmetic unit services comprise a basic mathematics arithmetic service and an enhanced mathematics arithmetic service; and the low computing power system subscribes to the mathematics arithmetic unit service through a service oriented architecture (SOA). Through the computing power deployment, if the application deployed in the low computing power system has a high computing requirement, a plurality of applications do not need to be specially added and deployed on the high computing power system, so that the development workload is greatly reduced; and there is no need to deploy applications and construct inter-core communication protocols in high and low computing power systems, thereby simplifying the software architecture.

The invention discloses a dynamic self-adaptive MSMC shared storage management method and device, and the method comprises the steps: pre-configuring a static partition of an MSMC shared storage region, and dividing a physical storage region into a plurality of partitions with fixed sizes through a partition reconfiguration module; initializing parameters of the dynamic monitoring module, and starting the dynamic monitoring module to periodically acquire real-time data of each partition; and circularly executing the sub-steps of data acquisition and anomaly detection, scheduling strategy calculation, partition reconfiguration and arbitration weight updating. Through hardware-level dynamic monitoring, priority perception scheduling and a microsecond-level reconfiguration mechanism, the utilization rate of storage resources is remarkably improved, high-priority tasks are guaranteed in real time, multi-core bandwidth allocation is optimized, and the dynamic adaptability of the system is enhanced; the contradiction between resource allocation fixity and task load dynamics in a traditional static partitioning scheme is fundamentally solved, and a breakthrough solution is provided for efficient parallel processing of a multi-core DSP system in a high-real-time scene.

The present application relates to the technical field of memory management, and discloses a memory management method for a multi-core system, a multi-core system, a device, and a medium. The method comprises: a master core unit marking initial memory management priorities of the master core unit and slave core units as a second level, the memory management priorities further comprising: a first level higher than the second level and a third level lower than the second level; determining a system operating condition; on the basis of the system operating condition and the second level, updating and determining current memory management priorities of the master core unit and the slave core units; and on the basis of a memory scheduling and allocation request sent by an applicant, the system operating condition, the type of the applicant, and a current memory management priority of the applicant, a memory manager performing memory scheduling and allocation processing, and allocating an idle memory unit to the applicant, so that the applicant executes a task in a task queue, the applicant being the master core unit or one of the slave core units. The present application can improve system memory utilization rate and ensure efficient and correct operation of the multi-core system.

A heterogeneous multi-core system to execute a real-time system of an automobile includes a plurality of system-on-chips in electronic communication with one another. Each system-on-chip includes a plurality of central processing units (CPUs) arranged into a plurality of logical domains. The heterogeneous multi-core system also includes a plurality of dispatched tasks that execute based on an execution pipeline and each perform a particular set of tasks for one of the logical domains. The plurality of dispatched tasks includes at least one offset dispatched task that executes at an offset time and a reference dispatched task that is located upstream of the execution stage of the offset dispatched task on the execution pipeline. The reference dispatched task communicates data to the offset dispatched task and the offset time represents a period of time measured relative to the reference dispatched task.

The application provides a task execution time stamp recording method for simulating data communication of a multi-core system, which comprises the following steps: when an operation state control unit busy signal is valid, a clock timing unit records a current task ID, records a task interval clock timer count value, and stops and clears the task interval clock timer count; a task execution clock timer count is started; when a task execution state signal changes, a task execution clock timer count value is recorded and cleared, and the count value of each state is sent to a time stamp information arrangement unit; when the task execution state jumps from a write-back state to an idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started, and a relative task ID is updated to the current task ID. The application realizes recording of multiple time stamps, and according to the recorded relative time stamp information, the order of task execution of a task in each core and the occupation time of each state can be recovered, thereby assisting in simulating a multi-core system data communication process.

The present disclosure discloses a method, device and related product for performing an operation task on a multi-core system. The device can be included in a combined processing device as a processing device, and the combined processing device can further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected with the computing device and the processing device respectively, for storing data of the computing device and the processing device. The scheme of the present disclosure provides a method for performing an operation task on a multi-core system, which can effectively reduce data access and improve processing efficiency.

This invention discloses a log collection method, apparatus, device, and medium for a multi-core system. The method is executed by the master core and multiple slave cores in a multi-core system, including: writing log strings into a buffer in the shared memory of the slave cores and generating log descriptors; writing the log descriptors into a lock-free circular queue; monitoring the state count value of the lock-free circular queue in real time by the master core, and obtaining a target log descriptor when the lock-free circular queue is determined to be non-empty; determining a target buffer in the shared memory of the slave cores and transferring the log strings in the target buffer to the master core memory; and determining that the log upload conditions are met based on a timer or master core memory usage, determining at least one target master core memory block in the master core memory and uploading the log strings in the target master core memory block. This technical solution can improve log writing efficiency and log upload real-time performance in high-concurrency scenarios of multi-core systems.

The application belongs to the security field in a multi-core system chip, and discloses a security bus architecture for a multi-core Chiplet chip system, which comprises five parts of an active interposer, a function chip, a storage chip, a Core chip and a security chiplet, the Core chip contains CPU cores of the chip system, the storage chip contains a memory for storing data and codes, the function chip contains most peripherals and function IPs, the active interposer is used for connecting all the chiplets and realizing access control of the chiplets, and the security chiplet is used for controlling and managing the security configuration of the whole chip system. When the chiplet provided by a supplier cannot be trusted, the security bus architecture can realize isolation and access limitation of the non-security chiplet. The bus architecture is realized in the security active interposer, and a security chiplet is used for configuring the access permission of each chiplet in the chip system, so that the data access of the remaining chiplets can be controlled, and the system security is enhanced.

The invention discloses a multi-core system and a debugging management device and method of the multi-core system, and is applied to the technical field of circuits, and the multi-core system comprises a scheduler which is connected with each processor and is used for carrying out enabling control on a tracking debugging function of each processor based on trigger information and sending received tracking debugging information to a filter; based on the trigger information, selecting various filtering rules currently started by the filter; and the filter is connected with the scheduler and used for filtering the received tracking debugging information based on the currently started filtering rules so as to discard the tracking debugging information which does not pass through the filtering rules in the tracking debugging information and output the tracking debugging information which passes through the filtering rules in the tracking debugging information. By means of the scheme, debugging management of the multi-core system can be effectively achieved, loss of key trace information is avoided, flexibility is high, and rapid transmission and processing of the trace information can be achieved.

Embodiments of the present application provide a multi-core system display method, a multi-core system, an electronic device and a storage medium. In some embodiments, the multi-core system display method can include the following steps: in response to the first core system being started, drawing first image data to a first sub-layer of a first display layer, and drawing mask data to a second sub-layer of the first display layer; in response to establishing a heartbeat connection with the second core system, determining whether the video transmission chip receives second image data output by the second core system; in response to the video transmission chip receiving the second image data, drawing the second image data forwarded by the video transmission chip to a second display layer, and removing the mask data in the second sub-layer; and outputting display data according to the first display layer and the second display layer.

The invention discloses a shared debugging terminal implementation method and a shared debugging terminal implementation system for an asymmetric multi-processing system. The shared debugging terminal implementation method and the shared debugging terminal implementation system have the following beneficial effects: (1) a plurality of cores share a single physical serial port through a shared memory area and a central routing agent; (2) each sub-region in the shared memory region comprises a core identifier region, so that a core identifier can be automatically added to each piece of debugging information to ensure that the source of the debugging information is clear, and the debugging efficiency is improved; (3) the method does not depend on a complex network protocol stack, so that the method can work reliably even at the initial stage of system starting or when the system crashes, and the debugging reliability is improved; (4) the resource occupation is less, and the debugging requirement of the multi-core system can be met by only needing one physical serial port and other types of interfaces; and (5) the method also has a failover mechanism, and when the main routing agent fails, the main routing agent can be automatically switched to the standby agent, namely, the main routing agent is automatically switched to the new central routing agent, so that the normal work of a debugging function is better ensured.

The application discloses a heterogeneous multi-core system and a running method thereof, an electronic device and a medium, and relates to the technical field of heterogeneous multi-core systems.The method comprises the following steps: packaging real-time core programs and non-real-time core programs into a unified program package; when the heterogeneous multi-core system starts, separating the real-time core programs and the non-real-time core programs according to the unified program package; performing version detection on the real-time core and the non-real-time core; when the version information of the non-real-time core is inconsistent with the version information of the real-time core, writing version update information into a shared memory area through the non-real-time core; performing version update on the real-time core according to the version update information; and when the version information of the non-real-time core is consistent with the version information of the real-time core, loading and running the real-time core programs and the non-real-time core programs respectively.The method can package the real-time core programs and the non-real-time core programs into a unified program package, and facilitate simultaneous management of the real-time core programs and the non-real-time core programs.

The invention belongs to the field of integrated circuit design and computer networks, and discloses a multi-path polling arbitration method and a related device. Input signals of all request source channels are collected in real time, and when any request state signal is detected, an arbitration working state is entered; and locking the request states of all the current request source channels to generate arbitration input information, positioning the latest request source channel based on the information in combination with the current polling pointer, generating an arbitration result, executing access operation, exiting the arbitration state, and updating the polling pointer to wait for next request triggering. By adopting the method, the scheduling flexibility is remarkably improved to adapt to variable loads, the circuit structure is simplified to reduce the implementation complexity, the adaptability to different system bus competition problems is enhanced to relieve conflicts, the problem of shared resource access conflicts in a network-on-chip and a multi-core system is effectively solved, and the efficient access requirement is met.

The application provides a concurrent memory database splitting method and relates to the technical field of databases. The ART index is improved to obtain an IART index, and an IARTC algorithm is proposed based on the IART index. The IARTC algorithm uses the IART index as a splitting index to drive database splitting. Meanwhile, a new database splitting concurrent algorithm PIARTC is obtained based on the IARTC algorithm. The PIARTC algorithm controls locking and unlocking of nodes on the IART index through an optimistic lock coupling concurrent strategy to realize concurrent splitting and index updating, so that small locking granularity is maintained in the concurrent execution process. Compared with existing algorithms, the two adaptive indexes proposed by the application have good query performance in single-core and multi-core systems in the case of facing dynamic environments and large-scale data set queries, and still maintain the lightweight characteristics of the original database splitting algorithm.

The invention discloses an AI data handling optimization method based on a multi-core system. The data handling optimization method comprises the steps that S1, initialization is carried out; s2, asynchronous request; s3, asynchronous processing; and S4, parallel execution. The processor A for executing the AI operation is always in the user state and does not need to fall into the kernel state, so that the system calling overhead is avoided; in the process that the processor A executes the AI operation, the processor B schedules DMA hardware to complete transmission processing of next data required by the AI reasoning operation, the DMA hardware and the AI reasoning operation are completely parallel, and when DMA transmission time is shorter than AI reasoning operation time, time overhead of DMA data transmission is completely masked; based on the software and hardware collaboration framework, the utilization rate of the computing part of the processor A can be close to 100%.

The application discloses a method, device and medium for improving the execution efficiency of a computing-intensive task, relates to the technical field of intensive task processing, and comprises the following steps: in response to an interrupt request received by a multi-core CPU system, determining whether a source CPU for processing the interrupt request is bound to a task; if it is determined that the source CPU is bound to the task, determining a target topology level adapted to the interrupt request according to an interrupt source device of the interrupt request, then determining a target topology node with the lowest interrupt load from the target topology level of the multi-core CPU system, and setting an interrupt affinity mask of the interrupt request to a mask of the target topology node; if it is determined that the source CPU is not bound to the task, then determining that the interrupt request is processed by the source CPU. The application realizes the purpose of considering the influence of interrupt processing on the execution efficiency of a computing-intensive task from the perspective of an external factor, does not need to deploy expensive hardware, does not need to modify the task at the code level, and improves the execution efficiency of the computing-intensive task.

The invention discloses a method, equipment and medium for improving execution efficiency of compute-intensive tasks, and relates to the technical field of intensive task processing.The method comprises the steps that in response to an interrupt request received by a multi-core CPU system, whether a source CPU defaulting to process the interrupt request is bound with a task or not is judged; if it is determined that the source CPU binds the task, a target topology level matched with the interrupt request is determined according to interrupt source equipment of the interrupt request, then a target topology node with the lowest interrupt load is determined from the target topology levels of the multi-core CPU system, and an interrupt affinity mask of the interrupt request is set as a mask of the target topology node; and if it is determined that the source CPU is not bound with the task, determining that the interrupt request is processed by the source CPU. According to the method, the aim of considering the influence on the execution efficiency of the compute-intensive task from the external factor of interrupt processing is achieved, expensive hardware does not need to be deployed, the task does not need to be modified at the code level, and the execution efficiency of the compute-intensive task is improved.

The invention discloses an inter-core communication method based on a PLC multi-core system, and relates to the technical field of inter-core communication, the PLC multi-core system is divided into a control core and a calculation core, and initialization configuration is carried out for different types of cores; a hybrid communication mechanism is set, the hybrid communication mechanism comprises an openAMP architecture and a shared memory mechanism, and environment establishment is carried out for the two communication modes; establishing a message type identification mechanism, and automatically classifying according to message features; constructing a self-adaptive routing algorithm to select an optimal communication mode; constructing a double linked list optimization management mechanism, calculating message priorities, and setting message sending time in a double linked list; when the PLC multi-core system sends a message, a sending core selects a core type according to the optimal communication mode, and openAMP architecture communication and shared memory mechanism communication are executed respectively according to the core type; and checking a communication result, executing an automatic retransmission strategy when the communication fails, and calculating retransmission times and retransmission intervals.

The invention provides a cache optimization method and device for an RISC-V multi-core processor. The cache optimization method comprises the following steps: identifying a shared variable generated by a transmission side RISC-V processor and read by a receiving side RISC-V processor in a software code; the receiving side RISC-V processor allocates a cache reserved space corresponding to the special address identifier in a local cache according to the configuration information; constructing an address mapping table according to the configuration information and the special address identifier; querying an address mapping table according to the target address; and if the target address is queried to be the special address identifier, transmitting the data from the transmission side register file to the cache reserved space corresponding to the receiving side through a direct cache link. According to the invention, a special direct cache data transmission link is constructed, and a producer-consumer model is adopted on the link to replace a traditional global cache consistency protocol, so that the problem of consistency traffic overload in a multi-core system is greatly relieved, and the overall efficiency of the system is improved.

Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

The application discloses a parallel operation cooperative control method of a multi-core processing chip, and comprises the following steps: S1, receiving a parallel computing task and analyzing, wherein after receiving the parallel computing task, the application deeply analyzes the task and generates a task topology graph, clearly presents data dependency between subtasks, adopts a dynamic adaptive cooperative mapping strategy, matches task dependency characteristics and actual states of each processing core in subtask distribution, improves rationality and efficiency of distribution, realizes dynamic and comprehensive detection of resource states through an on-chip distributed monitoring unit, dynamically adjusts a detection period according to system load, shortens the period when the load exceeds a threshold value, lengthens the period when the load is lower than the threshold value, and real-time monitors processing core performance and communication path states in subtask execution, and when the load exceeds the threshold value or communication congestion is detected, the subtask is quickly migrated to a lightly loaded processing core, and the communication path is updated, so that stable and efficient operation of the multi-core system is ensured.

An image rendering system comprising a preprocessing unit coupled to a feature extract unit and a color rendering unit over a data bus. The preprocessing unit generates vector representations of spatial coordinates of sample points along camera rays corresponding to pixels of an image to be rendered. The feature extract unit generates a feature map of the image based on the vector representations, color and intensity values of the sample point through a first machine learning model. The color rendering unit renders the image based on the feature map through a second machine learning model. The first machine learning model is different from the second machine learning model.