54 results about "Multicore systems" patented technology

The invention discloses a multi-core scheduling system and method based on interrupt affinity and a storage medium. The technical problem that data locality guarantee and load balancing are difficult to consider at the same time is solved by constructing a self-adaptive optimization closed loop of perception-decision-execution-feedback, and the method comprises the steps that a routing interruption configuration mechanism provides a basis for dynamic adjustment; an interrupt guide task placement mechanism ensures that an interrupt service program and an associated task are executed in the same CPU core, and the cache hit rate is increased; the execution overhead of an interrupt service program is brought into core load statistics through task context switching and a'task + ISR 'two-dimensional precise load evaluation mechanism triggered by ISR inlet / outlet double nodes, and real load awareness is achieved; a load-driven dynamic interrupt routing mechanism is combined with dual control of a hysteresis threshold and cooling time, so that a ping-pong effect is avoided. According to the method, dynamic load balancing is realized on the premise of keeping data locality, and the real-time response performance and throughput of the multi-core system are remarkably improved.

The invention relates to a task congestion processing method and device, a control system, a vehicle, a storage medium, a program product and a chip system, and the method comprises the steps that a first processor obtains information generated when a second processor executes a task from a shared memory; the first processor judges whether the task operated by the second processor is congested or not based on the information; and the first processor outputs prompt information of congestion of the second processor under the condition that the tasks operated by the second processor are congested. The method is used for automatically detecting the running state of the multi-core system.

The invention discloses a heterogeneous multi-core system, a vehicle-mounted application operation method, computer equipment and a computer readable storage medium, the heterogeneous multi-core system comprises a plurality of processors, at least one processor is provided with a high computing power system, and at least another processor is provided with a low computing power system. A mathematics arithmetic unit service module is deployed on the high computing power system, mathematics arithmetic unit services are published through a service oriented architecture (SOA), and the mathematics arithmetic unit services comprise a basic mathematics arithmetic service and an enhanced mathematics arithmetic service; and the low computing power system subscribes to the mathematics arithmetic unit service through a service oriented architecture (SOA). Through the computing power deployment, if the application deployed in the low computing power system has a high computing requirement, a plurality of applications do not need to be specially added and deployed on the high computing power system, so that the development workload is greatly reduced; and there is no need to deploy applications and construct inter-core communication protocols in high and low computing power systems, thereby simplifying the software architecture.

The invention discloses a dynamic self-adaptive MSMC shared storage management method and device, and the method comprises the steps: pre-configuring a static partition of an MSMC shared storage region, and dividing a physical storage region into a plurality of partitions with fixed sizes through a partition reconfiguration module; initializing parameters of the dynamic monitoring module, and starting the dynamic monitoring module to periodically acquire real-time data of each partition; and circularly executing the sub-steps of data acquisition and anomaly detection, scheduling strategy calculation, partition reconfiguration and arbitration weight updating. Through hardware-level dynamic monitoring, priority perception scheduling and a microsecond-level reconfiguration mechanism, the utilization rate of storage resources is remarkably improved, high-priority tasks are guaranteed in real time, multi-core bandwidth allocation is optimized, and the dynamic adaptability of the system is enhanced; the contradiction between resource allocation fixity and task load dynamics in a traditional static partitioning scheme is fundamentally solved, and a breakthrough solution is provided for efficient parallel processing of a multi-core DSP system in a high-real-time scene.

The present application relates to the technical field of memory management, and discloses a memory management method for a multi-core system, a multi-core system, a device, and a medium. The method comprises: a master core unit marking initial memory management priorities of the master core unit and slave core units as a second level, the memory management priorities further comprising: a first level higher than the second level and a third level lower than the second level; determining a system operating condition; on the basis of the system operating condition and the second level, updating and determining current memory management priorities of the master core unit and the slave core units; and on the basis of a memory scheduling and allocation request sent by an applicant, the system operating condition, the type of the applicant, and a current memory management priority of the applicant, a memory manager performing memory scheduling and allocation processing, and allocating an idle memory unit to the applicant, so that the applicant executes a task in a task queue, the applicant being the master core unit or one of the slave core units. The present application can improve system memory utilization rate and ensure efficient and correct operation of the multi-core system.

The present disclosure discloses a method, device and related product for performing an operation task on a multi-core system. The device can be included in a combined processing device as a processing device, and the combined processing device can further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected with the computing device and the processing device respectively, for storing data of the computing device and the processing device. The scheme of the present disclosure provides a method for performing an operation task on a multi-core system, which can effectively reduce data access and improve processing efficiency.

This invention discloses a log collection method, apparatus, device, and medium for a multi-core system. The method is executed by the master core and multiple slave cores in a multi-core system, including: writing log strings into a buffer in the shared memory of the slave cores and generating log descriptors; writing the log descriptors into a lock-free circular queue; monitoring the state count value of the lock-free circular queue in real time by the master core, and obtaining a target log descriptor when the lock-free circular queue is determined to be non-empty; determining a target buffer in the shared memory of the slave cores and transferring the log strings in the target buffer to the master core memory; and determining that the log upload conditions are met based on a timer or master core memory usage, determining at least one target master core memory block in the master core memory and uploading the log strings in the target master core memory block. This technical solution can improve log writing efficiency and log upload real-time performance in high-concurrency scenarios of multi-core systems.

The invention discloses a multi-core system and a debugging management device and method of the multi-core system, and is applied to the technical field of circuits, and the multi-core system comprises a scheduler which is connected with each processor and is used for carrying out enabling control on a tracking debugging function of each processor based on trigger information and sending received tracking debugging information to a filter; based on the trigger information, selecting various filtering rules currently started by the filter; and the filter is connected with the scheduler and used for filtering the received tracking debugging information based on the currently started filtering rules so as to discard the tracking debugging information which does not pass through the filtering rules in the tracking debugging information and output the tracking debugging information which passes through the filtering rules in the tracking debugging information. By means of the scheme, debugging management of the multi-core system can be effectively achieved, loss of key trace information is avoided, flexibility is high, and rapid transmission and processing of the trace information can be achieved.

Embodiments of the present application provide a multi-core system display method, a multi-core system, an electronic device and a storage medium. In some embodiments, the multi-core system display method can include the following steps: in response to the first core system being started, drawing first image data to a first sub-layer of a first display layer, and drawing mask data to a second sub-layer of the first display layer; in response to establishing a heartbeat connection with the second core system, determining whether the video transmission chip receives second image data output by the second core system; in response to the video transmission chip receiving the second image data, drawing the second image data forwarded by the video transmission chip to a second display layer, and removing the mask data in the second sub-layer; and outputting display data according to the first display layer and the second display layer.

The invention discloses a shared debugging terminal implementation method and a shared debugging terminal implementation system for an asymmetric multi-processing system. The shared debugging terminal implementation method and the shared debugging terminal implementation system have the following beneficial effects: (1) a plurality of cores share a single physical serial port through a shared memory area and a central routing agent; (2) each sub-region in the shared memory region comprises a core identifier region, so that a core identifier can be automatically added to each piece of debugging information to ensure that the source of the debugging information is clear, and the debugging efficiency is improved; (3) the method does not depend on a complex network protocol stack, so that the method can work reliably even at the initial stage of system starting or when the system crashes, and the debugging reliability is improved; (4) the resource occupation is less, and the debugging requirement of the multi-core system can be met by only needing one physical serial port and other types of interfaces; and (5) the method also has a failover mechanism, and when the main routing agent fails, the main routing agent can be automatically switched to the standby agent, namely, the main routing agent is automatically switched to the new central routing agent, so that the normal work of a debugging function is better ensured.

The application provides a concurrent memory database splitting method and relates to the technical field of databases. The ART index is improved to obtain an IART index, and an IARTC algorithm is proposed based on the IART index. The IARTC algorithm uses the IART index as a splitting index to drive database splitting. Meanwhile, a new database splitting concurrent algorithm PIARTC is obtained based on the IARTC algorithm. The PIARTC algorithm controls locking and unlocking of nodes on the IART index through an optimistic lock coupling concurrent strategy to realize concurrent splitting and index updating, so that small locking granularity is maintained in the concurrent execution process. Compared with existing algorithms, the two adaptive indexes proposed by the application have good query performance in single-core and multi-core systems in the case of facing dynamic environments and large-scale data set queries, and still maintain the lightweight characteristics of the original database splitting algorithm.

The invention discloses an AI data handling optimization method based on a multi-core system. The data handling optimization method comprises the steps that S1, initialization is carried out; s2, asynchronous request; s3, asynchronous processing; and S4, parallel execution. The processor A for executing the AI operation is always in the user state and does not need to fall into the kernel state, so that the system calling overhead is avoided; in the process that the processor A executes the AI operation, the processor B schedules DMA hardware to complete transmission processing of next data required by the AI reasoning operation, the DMA hardware and the AI reasoning operation are completely parallel, and when DMA transmission time is shorter than AI reasoning operation time, time overhead of DMA data transmission is completely masked; based on the software and hardware collaboration framework, the utilization rate of the computing part of the processor A can be close to 100%.

The application discloses a method, device and medium for improving the execution efficiency of a computing-intensive task, relates to the technical field of intensive task processing, and comprises the following steps: in response to an interrupt request received by a multi-core CPU system, determining whether a source CPU for processing the interrupt request is bound to a task; if it is determined that the source CPU is bound to the task, determining a target topology level adapted to the interrupt request according to an interrupt source device of the interrupt request, then determining a target topology node with the lowest interrupt load from the target topology level of the multi-core CPU system, and setting an interrupt affinity mask of the interrupt request to a mask of the target topology node; if it is determined that the source CPU is not bound to the task, then determining that the interrupt request is processed by the source CPU. The application realizes the purpose of considering the influence of interrupt processing on the execution efficiency of a computing-intensive task from the perspective of an external factor, does not need to deploy expensive hardware, does not need to modify the task at the code level, and improves the execution efficiency of the computing-intensive task.

The invention discloses an inter-core communication method based on a PLC multi-core system, and relates to the technical field of inter-core communication, the PLC multi-core system is divided into a control core and a calculation core, and initialization configuration is carried out for different types of cores; a hybrid communication mechanism is set, the hybrid communication mechanism comprises an openAMP architecture and a shared memory mechanism, and environment establishment is carried out for the two communication modes; establishing a message type identification mechanism, and automatically classifying according to message features; constructing a self-adaptive routing algorithm to select an optimal communication mode; constructing a double linked list optimization management mechanism, calculating message priorities, and setting message sending time in a double linked list; when the PLC multi-core system sends a message, a sending core selects a core type according to the optimal communication mode, and openAMP architecture communication and shared memory mechanism communication are executed respectively according to the core type; and checking a communication result, executing an automatic retransmission strategy when the communication fails, and calculating retransmission times and retransmission intervals.

Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

Disclosed are techniques for runtime adaptive operation configuration in a many-core system. In an aspect, a method for runtime adaptive operation configuration in a many-core system includes performing a dynamic operation configuration, where the dynamic operation configuration includes determining a core utilization in the many-core system, determining an operation configuration based on the core utilization, and configuring at least one core in the many-core system according to the operation configuration. In some aspects, the dynamic operation configuration may be performed periodically or in response to a trigger condition.

Embodiments of the present application provide a scheduling table restart method and device, a vehicle and a medium. The method comprises: starting the main core to process the scheduling table of at least one slave core; detecting, by the main core, an abnormal condition of the scheduling table of the at least one slave core; and restarting, for a target slave core with an abnormal condition of the scheduling table, the processing of the scheduling table of the target slave core by the main core. The scheduling table is individually specified for each slave core, and the monitoring of the scheduling table of a single slave core is implemented, so that the main core can detect the failure of a single slave core, the individual processing of the scheduling table of a single slave core is implemented, and the functional safety and flexibility of the multi-core system are improved.

The application is suitable for the field of microprocessor architecture, on-chip multi-core system and embedded real-time computing technology, and provides a fine-grained cache partition lock method based on RISC-V extension instruction and a processor, the method comprising: adding a Zicpl extension instruction family in the RISC-V instruction set architecture, the Zicpl extension instruction family comprising a LOCK.CP instruction, an UNLOCK.CP instruction, a TESTLOCK.CP instruction and a SET.CP instruction; adding a partition lock table on the cache controller side of the processor, the partition lock table comprising a plurality of entries, each entry comprising an owner field, a timeout field and a valid field; adding a lock flag and a partition identification field in the Tag area of the cache memory; the application can significantly improve the real-time performance and system energy efficiency, and has significant industrial and economic value.

A multi-core system includes a first processor core, a first memory coupled to the first processor core, a first communication IF including a first DMA unit coupled to the first memory, a second processor core, a second memory coupled to the second processor core, a second communication IF including a second DMA unit coupled to the second memory, and an MMU. In a case where page data of a page designated as a read destination by the first processor core is stored in the second memory, the MMU causes the first DMA unit to set a first transmission descriptor based on a page number of the page. The first communication IF transmits a data request including the page number and destination data to the second communication IF according to the first transmission descriptor.

The invention provides a shared memory management method and a multi-core system. The multi-core system comprises a master core and a slave core and is provided with a shared memory management module, and the shared memory management module is provided with an initialization interface and a read-write access interface. The shared memory management method comprises the following steps: acquiring a configuration attribute of a shared data block from a local core through a main core, and calling an initialization interface according to the configuration attribute so as to execute an initialization operation on a shared memory through a shared memory management module; wherein the local core is a master core or a slave core for writing data; and after the initialization operation is completed, calling the read-write access interface through the master core or the slave core to access the shared data block address in the shared memory, and executing a corresponding shared data read-write operation. According to the application, the shared memory access interface is unified through the shared memory management module, the modular management of the shared memory is realized, the problem of resource shortage caused by unreasonable memory use is avoided, and meanwhile, an Autosar complex drive development specification is met.

This disclosure provides a power consumption control method and apparatus for a multi-core system. The multi-core system includes a master processor and at least one slave processor, and is applied in a device including the multi-core system. The method includes: the master processor determining whether a slave processor needs to enter a sleep state based on a comparison of the amount of unprocessed data stored in the input cache space of any slave processor with a first preset threshold, and a comparison of the amount of processed data stored in the output cache space of the slave processor with a second preset threshold; if the master processor determines that the slave processor needs to enter a sleep state, the master processor sets the frequency of the slave processor to a first specified frequency, wherein the first specified frequency is less than an intermediate frequency, and the intermediate frequency is the minimum frequency required for the slave processor to operate normally. This sets the slave processor to a sleep state, thereby reducing the power consumption of the multi-core system.

The present disclosure discloses a task scheduling method based on a multi-core system, a task scheduling device and related products. The task scheduling device can be included in a combined processing device as a processing device, which can further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected with the computing device and the processing device respectively, for storing data of the computing device and the processing device. The scheme of the present disclosure provides a method for scheduling group matrix multiplication operation tasks on a multi-core system, which can effectively reduce data access and improve processing efficiency.

The invention relates to the field of video signal processing, and particularly discloses a real-time video compression system for multi-core parallel processing. The system comprises a video frame analysis module, a region segmentation module, a priority allocation module, a task dependency graph construction module, a task scheduling module and a resource allocation module. The core of the method is that a space-time complexity mapping graph is generated by analyzing texture and motion features of video frames, and compression areas are dynamically divided and processing priorities are allocated according to the space-time complexity mapping graph; and then a priority-based dynamic task dependency graph is established, tasks are allocated to multiple processing cores by adopting a critical path priority scheduling strategy, and differentiated computing resources are allocated according to the priority. Through content-aware adaptive task division and scheduling, the problem of low efficiency caused by uneven load in a multi-core system is effectively solved, and the processing efficiency of real-time video compression and the utilization rate of system resources are improved.

The invention discloses a heterogeneous multi-core system and an operation method thereof, electronic equipment and a medium, and relates to the technical field of heterogeneous multi-core systems. The method comprises the following steps: packing a real-time core program and a non-real-time core program into a unified program package; when the heterogeneous multi-core system is started, the real-time core program and the non-real-time core program are separated according to the unified program package; performing version detection on the real-time core and the non-real-time core; when the version information of the non-real-time core is inconsistent with the version information of the real-time core, version updating information is written into the shared memory area through the non-real-time core; updating the version of the real-time core according to the version updating information; and when the version information of the non-real-time core is consistent with the version information of the real-time core, respectively loading and running the real-time core program and the non-real-time core program. According to the method, the real-time core program and the non-real-time core program can be packaged into the unified program package, so that the real-time core program and the non-real-time core program can be conveniently managed at the same time.

The invention discloses a heterogeneous multi-core system hybrid task allocation method and device, and the method comprises the steps: carrying out the instruction cycle according to the hierarchy of each task and the worst case of the task, and sorting the tasks, and obtaining the allocation priority of each task; selecting to-be-allocated tasks according to the allocation priority sequence, and allocating the selected task forcing part to a processor core which meets the task deadline and system energy consumption requirements of the tasks and has the highest task execution efficiency; according to the total energy consumption of the distributed task forcing parts and the total energy consumption budget of the system, sequentially carrying out energy consumption extension on the task forcing parts according to the task distribution priority; and selecting the tasks to be distributed according to the distribution priority sequence, and distributing the selectable parts of the selected tasks to the processor core which meets the task deadline of the tasks and has the highest task execution efficiency. According to the technical scheme, system resources are fully utilized to improve the service quality of the system, and collaborative optimization of hybrid task scheduling is achieved.

A multicore computing device includes a memory and a processor coupled to the memory. The processor includes plural cores and a multiple input multiple output (MIMO) block coupled to the cores. The MIMO block receives a halt request from a first core of the cores, transmits a core-halt request to one or more other cores other than the first core, to halt execution of the one or more other cores, and permits the first core to lock with a shared resource.

The invention discloses a high-efficiency parallel data extraction and preprocessing model for nuclear emergency, which realizes high-efficiency preprocessing of meteorological and ocean data in a GRIB format by constructing a parallel data processing method based on task fragmentation. Firstly, an original GRIB file is logically divided through a data fragmentation step to form task fragments capable of being independently processed, and then the task fragments are uniformly distributed to a local task queue through a task initialization step in combination with multi-core system resources. Furthermore, a core emergency parallel task stealing algorithm is adopted, and cross-processing-unit task collaboration and stealing scheduling are realized on the basis of local priority execution, so that the resource utilization rate and the task throughput capacity of the multi-core system are improved. In the whole process, an error monitoring and fault-tolerant mechanism is combined, automatic rescheduling and retry can be carried out when processing fails, stability and integrity of data processing are guaranteed, and processing results are rearranged into structured output according to a time sequence and a space structure by means of a result integration step.

The invention provides a hardware access control device used in a multi-core system. The device comprises a plurality of main cores and a hardware lock module, the hardware lock module comprises a hardware lock register module and a hardware lock arbitration response module; the bit width of a register in the hardware lock register module is consistent with the number of the main cores, each bit corresponds to an access permission mark of one main core, only one bit is allowed to be set at the same moment, if one main core has set a lock bit, other main cores cannot set the lock bit, and the lock bit can be set after being unlocked; the hardware lock arbitration response module comprises a peripheral hardware lock arbitration module and a memory hardware lock arbitration module, and the peripheral hardware lock arbitration module and the memory hardware lock arbitration module correspond to APB and AHB bus access paths respectively. According to the hardware access control device used in the multi-core system provided by the invention, the hardware lock module is introduced into the multi-core system, so that hardware-level atom mutual exclusion access of resource access is realized, and the conflict that multiple cores access peripheral or memory resources at the same time is prevented.

This invention relates to the field of computer technology, and particularly to a method, apparatus, and storage medium for allocating memory in a multi-core system. The method involves: determining the identifier of each core in the multi-core system; determining the functional code of each core from a shared memory area based on the identifier; allocating multiple instruction-tightly coupled memory areas and one data-tightly coupled memory area to each core in the multi-core system based on the functional code; each instruction-tightly coupled memory area corresponding to at least one core; dynamically loading the functional code of each core from the shared memory area into the corresponding instruction-tightly coupled memory area, and dynamically loading global variables from the shared memory area into the data-tightly coupled memory area. This improves both the data processing efficiency and storage efficiency of the multi-core system.

The invention provides a memory access method and device, equipment, a medium and a program product, which are applied to a multi-core system, and the multi-core system comprises a main processor and a coprocessor; the method comprises the following steps: determining a first memory space from a memory space of a main processor; removing the access authority of the main processor to the first memory space, so that the main processor cannot access the first memory space; and mapping the physical address of the first memory space to the coprocessor, so that the coprocessor accesses the first memory space based on the physical address. According to the scheme, the memory access reliability of the coprocessor can be improved.