16 results about "Multicore systems" patented technology

The present application relates to the technical field of memory management, and discloses a memory management method for a multi-core system, a multi-core system, a device, and a medium. The method comprises: a master core unit marking initial memory management priorities of the master core unit and slave core units as a second level, the memory management priorities further comprising: a first level higher than the second level and a third level lower than the second level; determining a system operating condition; on the basis of the system operating condition and the second level, updating and determining current memory management priorities of the master core unit and the slave core units; and on the basis of a memory scheduling and allocation request sent by an applicant, the system operating condition, the type of the applicant, and a current memory management priority of the applicant, a memory manager performing memory scheduling and allocation processing, and allocating an idle memory unit to the applicant, so that the applicant executes a task in a task queue, the applicant being the master core unit or one of the slave core units. The present application can improve system memory utilization rate and ensure efficient and correct operation of the multi-core system.

The present disclosure discloses a method, device and related product for performing an operation task on a multi-core system. The device can be included in a combined processing device as a processing device, and the combined processing device can further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected with the computing device and the processing device respectively, for storing data of the computing device and the processing device. The scheme of the present disclosure provides a method for performing an operation task on a multi-core system, which can effectively reduce data access and improve processing efficiency.

This invention discloses a log collection method, apparatus, device, and medium for a multi-core system. The method is executed by the master core and multiple slave cores in a multi-core system, including: writing log strings into a buffer in the shared memory of the slave cores and generating log descriptors; writing the log descriptors into a lock-free circular queue; monitoring the state count value of the lock-free circular queue in real time by the master core, and obtaining a target log descriptor when the lock-free circular queue is determined to be non-empty; determining a target buffer in the shared memory of the slave cores and transferring the log strings in the target buffer to the master core memory; and determining that the log upload conditions are met based on a timer or master core memory usage, determining at least one target master core memory block in the master core memory and uploading the log strings in the target master core memory block. This technical solution can improve log writing efficiency and log upload real-time performance in high-concurrency scenarios of multi-core systems.

Embodiments of the present application provide a multi-core system display method, a multi-core system, an electronic device and a storage medium. In some embodiments, the multi-core system display method can include the following steps: in response to the first core system being started, drawing first image data to a first sub-layer of a first display layer, and drawing mask data to a second sub-layer of the first display layer; in response to establishing a heartbeat connection with the second core system, determining whether the video transmission chip receives second image data output by the second core system; in response to the video transmission chip receiving the second image data, drawing the second image data forwarded by the video transmission chip to a second display layer, and removing the mask data in the second sub-layer; and outputting display data according to the first display layer and the second display layer.

The application provides a concurrent memory database splitting method and relates to the technical field of databases. The ART index is improved to obtain an IART index, and an IARTC algorithm is proposed based on the IART index. The IARTC algorithm uses the IART index as a splitting index to drive database splitting. Meanwhile, a new database splitting concurrent algorithm PIARTC is obtained based on the IARTC algorithm. The PIARTC algorithm controls locking and unlocking of nodes on the IART index through an optimistic lock coupling concurrent strategy to realize concurrent splitting and index updating, so that small locking granularity is maintained in the concurrent execution process. Compared with existing algorithms, the two adaptive indexes proposed by the application have good query performance in single-core and multi-core systems in the case of facing dynamic environments and large-scale data set queries, and still maintain the lightweight characteristics of the original database splitting algorithm.

The invention discloses an inter-core communication method based on a PLC multi-core system, and relates to the technical field of inter-core communication, the PLC multi-core system is divided into a control core and a calculation core, and initialization configuration is carried out for different types of cores; a hybrid communication mechanism is set, the hybrid communication mechanism comprises an openAMP architecture and a shared memory mechanism, and environment establishment is carried out for the two communication modes; establishing a message type identification mechanism, and automatically classifying according to message features; constructing a self-adaptive routing algorithm to select an optimal communication mode; constructing a double linked list optimization management mechanism, calculating message priorities, and setting message sending time in a double linked list; when the PLC multi-core system sends a message, a sending core selects a core type according to the optimal communication mode, and openAMP architecture communication and shared memory mechanism communication are executed respectively according to the core type; and checking a communication result, executing an automatic retransmission strategy when the communication fails, and calculating retransmission times and retransmission intervals.

Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

Disclosed are techniques for runtime adaptive operation configuration in a many-core system. In an aspect, a method for runtime adaptive operation configuration in a many-core system includes performing a dynamic operation configuration, where the dynamic operation configuration includes determining a core utilization in the many-core system, determining an operation configuration based on the core utilization, and configuring at least one core in the many-core system according to the operation configuration. In some aspects, the dynamic operation configuration may be performed periodically or in response to a trigger condition.

A multi-core system includes a first processor core, a first memory coupled to the first processor core, a first communication IF including a first DMA unit coupled to the first memory, a second processor core, a second memory coupled to the second processor core, a second communication IF including a second DMA unit coupled to the second memory, and an MMU. In a case where page data of a page designated as a read destination by the first processor core is stored in the second memory, the MMU causes the first DMA unit to set a first transmission descriptor based on a page number of the page. The first communication IF transmits a data request including the page number and destination data to the second communication IF according to the first transmission descriptor.

The present disclosure discloses a task scheduling method based on a multi-core system, a task scheduling device and related products. The task scheduling device can be included in a combined processing device as a processing device, which can further include an interface device and a computing device. The computing device interacts with the processing device to jointly complete a user-specified computing operation. The combined processing device can further include a storage device connected with the computing device and the processing device respectively, for storing data of the computing device and the processing device. The scheme of the present disclosure provides a method for scheduling group matrix multiplication operation tasks on a multi-core system, which can effectively reduce data access and improve processing efficiency.

This invention relates to the field of computer technology, and particularly to a method, apparatus, and storage medium for allocating memory in a multi-core system. The method involves: determining the identifier of each core in the multi-core system; determining the functional code of each core from a shared memory area based on the identifier; allocating multiple instruction-tightly coupled memory areas and one data-tightly coupled memory area to each core in the multi-core system based on the functional code; each instruction-tightly coupled memory area corresponding to at least one core; dynamically loading the functional code of each core from the shared memory area into the corresponding instruction-tightly coupled memory area, and dynamically loading global variables from the shared memory area into the data-tightly coupled memory area. This improves both the data processing efficiency and storage efficiency of the multi-core system.

A kind of in-core bidirectional timer suitable for multi-core system includes ascending timer, countdown timer, adder and in-core timer interrupt module;The output of kernel clock is connected respectively with adder and in-core timer interrupt module;Ascending timer is used to realize absolute time point timing function, and the absolute time point configured is sent to in-core timer interrupt module;Countdown timer is used to realize relative time point timing function, and the countdown value configured is sent to adder;Adder converts the countdown value configured into ascending time value, and the converted ascending time value is sent to in-core timer interrupt module by ascending timer;In-core timer interrupt module, according to kernel clock time value in combination with the absolute time point configured, kernel clock ascending time arrives at the absolute time point, then generates interrupt signal, and informs interrupt controller timing end;According to kernel clock time value in combination with ascending time value, when countdown value reduces to 0, interrupt signal is generated, and informs interrupt controller timing end.

This application discloses a memory access method, a multi-core system, a processor, and a system-on-a-chip, relating to the field of processors. The method includes: in response to a received atomic operation, determining the memory address carried in the atomic operation; based on the memory address, determining the address layout state of first data in memory, wherein the address layout state characterizes whether the memory address crosses the cache line boundary or data page boundary of any processing unit; if the address layout state characterizes that the memory address crosses the cache line boundary or data page boundary, splitting the atomic operation into multiple first sub-operations, wherein different first sub-operations carry different sub-addresses; and based on the sub-addresses carried by the multiple first sub-operations, accessing the first data stored in memory through the cache of any processing unit. This application solves the technical problem of low processing efficiency in multi-core systems caused by improper control of unaligned atomic operations.

The present specification relates to the technical field of integrated circuits, and particularly relates to a multi-core system atomic instruction scheduling method, system and device, the method comprising: determining an atomic instruction near-end execution reliability index according to the number of times of successful near-end execution of the atomic instruction in a historical period; scheduling an execution position of the atomic instruction in a hierarchical cache according to the hit condition of to-be-processed data in the hierarchical cache, the data exclusive state of the to-be-processed data and the atomic instruction near-end execution reliability index, to obtain a scheduling execution result; and updating the atomic instruction near-end execution reliability index according to the scheduling execution result. The application can perceive the competition degree of access to a critical section in a multi-core scenario, dynamically adjust atomic instruction near-end execution and remote execution according to the system atomic instruction execution state, and improve the atomic instruction execution efficiency.

This invention discloses a load balancing method, apparatus, program product, electronic device, and storage medium, relating to the field of server technology. Addressing the problem of unbalanced load scheduling in heterogeneous systems, this invention provides a load balancing method. The method involves obtaining first load information for each core processor from shared memory; each core processor, after obtaining its corresponding first load information, writes it into the shared memory; based on the first load information, predicts the future second load information for each core processor; and performs task scheduling based on the second load information. The task scheduling process includes: the source core processor packaging task protocol data and writing it into the shared memory, and the destination core processor reading the task protocol data from the shared memory. This method can achieve load balancing in heterogeneous systems, and the task scheduling implemented by this method is predictive, better ensuring load balancing in multi-core systems.

This invention belongs to the field of integrated circuit design and computer networks, and discloses a multi-channel polling arbitration method and related apparatus. By real-time acquisition of input signals from all request source channels, the method enters arbitration mode upon detecting any request status signal, locks the request status of all current request source channels to generate arbitration input information, and uses this information combined with the current polling pointer to locate the nearest request source channel and generate an arbitration result. After performing the access operation, the method exits arbitration mode and updates the polling pointer to await the next request trigger. This method significantly improves scheduling flexibility to adapt to varying loads, simplifies circuit structure to reduce implementation complexity, enhances adaptability to different system bus contention problems to alleviate conflicts, effectively solves the problem of shared resource access conflicts in on-chip networks and multi-core systems, and meets the requirements for efficient access.