62 results about "Debugger" patented technology

The invention relates to an embedded chip simulation and debugging method and system. The method comprises the following steps: expanding an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set in a GDB debugger, and generating a special debugging front-end program; the method comprises the following steps: expanding a C28x JTAG protocol adaptation module in an OpenOCD debugging agent, and generating a debugging agent program; a C28x instruction set execution simulation unit is realized in the NEMU simulator, and a GDB Server communication module is embedded in the NEMU simulator; seamless switching between a simulation debugging mode and a hardware debugging mode is realized based on a unified configuration file through a software and hardware debugging environment rapid switching control module. The problems that a traditional debugging mode depends on a special hardware simulator, the cost is high and the simulation environment is inaccurate are solved, and through an integrated software and hardware collaborative debugging scheme, the debugging cost is greatly reduced, and the development efficiency and the comprehensiveness of system verification are improved.

Disclosed are systems and methods for debugging program code using a computing system. The disclosed method includes designating a control point in a software application subject to a debugging procedure, and then executing the program code for the software application as a guest application executing within a virtual machine. Upon detection of a virtualization event, the hardware processor transfers program control to a hypervisor which then determines whether the virtualization event corresponds to the designated control point based on an execution state of the guest application. If so, the virtualization event handler may generate a debugging event that is used by a debugger.

This invention relates to the technical field of program burning, and discloses a wireless SWD debugging and burning system and method for a collaborative arm. The wireless SWD debugging and burning method, applied to an SWD debugging and burning device, specifically includes the following steps: S101: Receiving a debugging and burning command sent by a host computer, and setting the embedded pins on the wireless debugging adapter of the ESP32 module. This invention, through a wireless gateway and software protocol simulator built around the ESP32 module, successfully upgrades the debugging and burning link, which previously relied on physical cables and dedicated hardware debuggers, to a fully wireless method. This eliminates the need for technicians to disassemble the device casing for each operation, completely avoiding mechanical wear and sealing failure caused by repeated disassembly and reassembly.

The embodiment of the invention discloses a code debugging method and device, equipment and a medium, and relates to the technical field of computers. According to the code debugging method, the target simulation environment and the debugger of the target compiler are integrated, and the debugger of the target compiler can be directly called in the simulation running process to conduct real-time and source code level step-by-step debugging. Moreover, developers can set the breakpoint at the specified position of the source code in the target compiler, and when the source code runs to the breakpoint, the source code is directly debugged through the debugger of the target compiler, so that the problem positioning efficiency and the problem processing efficiency are improved, and the overall development efficiency is improved.

The invention provides an on-chip debugging method, an on-chip debugger, an on-chip debugging system and a storage medium, the method is applied to the on-chip debugger, debugging component resources are pre-configured in the on-chip debugger, and the debugging component resources comprise hardware debugging function components corresponding to different debugging target hardware platforms respectively. The method comprises the steps of obtaining a debugging instruction, wherein the debugging instruction comprises hardware platform attribute information of a debugging target; according to the debugging instruction, target debugging function components are determined from the debugging component resources, the target debugging function components comprise a first target debugging function component, and the first target debugging function component comprises a hardware debugging function component matched with hardware platform attribute information of the debugging target; and based on the target debugging function component, debugging the debugging target. According to the scheme, the on-chip debugging efficiency can be remarkably improved.

A software service such as a daemon monitors traffic at virtual com ports of virtual machines to facilitate debugging of virtual functions in real time as the virtual functions take turns using a hardware resource in round-robin fashion. If the daemon detects that a kernel debugger has initiated a kernel debugging session for a particular virtual function via the com port, the monitor halts world switching between virtual functions allocated to the hardware resource. The daemon makes the virtual function indicated by the kernel debugger the active partition while the kernel debugger reads one or more registers of the hardware resource allocated to the virtual function. When the kernel debugger has completed reading the register(s), the daemon signals the host to resume world switching between the virtual functions.

A power state framework executes a workload in supported computing device types and configurations during a sequence of power state transitions to simulate user experiences. Workloads can be combined, e.g., default workload plus add-on workload(s). Device states are monitored, collected, reported, and analyzed to identify faults, which are prioritized for repair, e.g., based on the projected impact of the faults on users, e.g., if the users were to experience the faults. Computing device states include states of attached peripheral devices and wireless or wired connectivity before and after power state transitions. Device state indicates device stability throughout supported device power state transitions. Devices under test can be on debuggers during execution of workload and power state transitions. Automated, accelerated simulation of the execution of end user workloads and power state transitions in actual computing devices saves time and avoids replication errors compared to manual user-driven device testing.

The present disclosure relates to the technical field of computer, and particularly relates to a trap management device, a processor, a chip and an electronic device, which comprises: at least one processing core configured to execute a thread; a processor trap management unit coupled with the at least one processing core; and an interrupt reporting unit coupled with the processor trap management unit; wherein: the processing core suspends execution of the thread and reports a trap event to the processor trap management unit in response to the thread executed therein satisfying a trap condition; and the processor trap management unit performs coordinated management and triggers the interrupt reporting unit to report an interrupt to an external debugger in response to receiving the trap event. According to the embodiment of the present disclosure, the resource utilization efficiency of the processor in a debugging or monitoring scenario can be effectively improved.

A debugging method and an electronic device relate to the technical field of computers, and dynamically call a debugging interface of a second programming language by registering the debugging interface of the second programming language in a first programming language debugger, thereby obtaining call stack information and variable information of the second programming language, setting breakpoints, modifying variables and the like. In the method, the electronic equipment displays a debugging interface of a debugger adaptive to a first programming language, and loads a service program which is subjected to mixed programming by adopting the first programming language and a second programming language to test equipment. A runtime debugging interface is configured in the runtime matched with the second programming language. During debugging, when a service process runs to a first service code segment obtained by programming of a first programming language, a debugging breakpoint is entered, and the electronic equipment calls a runtime debugging interface through a debugger registered with the runtime debugging interface; and executing debugging processing operation on a second business code segment obtained by programming in the business program loaded by the test equipment by adopting the second programming language.

A method for blocking external debugger application from analysing code of software program installed on computing device. The method including initializing software program including an application program and an internal debugger application. The software program, upon initialization thereof, instructs internal debugger application to load application program in internal debugger application. The internal debugger application is configured to utilize kernel resources of an operating system of the computing device. The method includes executing internal debugger application to set one or more break-points in code of application program to define execution path for code of application program, executing application program as per defined execution path for code thereof, stopping execution of code of application program upon reaching any of one or more break-points therein, and handing control to internal debugger application to provide an address for next instruction to be executed in defined execution path for code of application program.

This invention provides an interactive software debugging and automatic repair method based on a large language model, addressing the problems of traditional software debugging relying on manual operation and being time-consuming, as well as the low repair accuracy caused by the lack of a dynamic operating environment in existing static automatic program repair technologies. The method first triggers a program exception by executing a reproduction command and captures the original crash stack information; then, it uses a large model to extract a simplified core function call sequence; subsequently, it constructs a closed-loop debugging mechanism, controlling the large model to generate hypotheses about the root cause of the defect and executing debugger probe commands, iteratively revising the hypotheses based on the dynamic information obtained by the debugger until the defective code is accurately located; finally, it combines the debugging context with the large model to complete root cause analysis and automatically generate and verify executable repair patches. This invention alleviates the "illusion" of large model inference by continuously capturing the underlying dynamic operating state, significantly improving the automation and accuracy of defect repair.

The application discloses a chip and a chip debugging system, and relates to the technical field of chip debugging. The chip comprises a controller, a reset signal generating unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module and a general interface. The general interface is used for connecting with a debugger, and the instruction receiving unit is connected with the general interface. The reset signal generating unit is used for generating an effective first reset signal and a second reset signal. The release time of the first reset signal is earlier than the release time of the second reset signal. The instruction receiving unit is used for detecting whether an instruction sent by the debugger is received after the release of the first reset signal and before the release of the second reset signal. When the instruction receiving unit receives the instruction, the instruction receiving unit controls the interface multiplexing unit to select the general interface and the debugging module. When the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to select the general interface and the functional module. According to the application, no additional multiplexing control pin is needed, and flexible multiplexing of a debugging interface and a functional interface is realized.

The invention discloses an ST language debugging method based on LLVM debugging information and a GDB / MI interface, and relates to the technical field of language development, and the method comprises the steps: carrying out the lexical analysis, grammatical analysis and semantic analysis of an ST source code through an ST language front-end analyzer, and generating a middle presentation layer of an LLVM; encoding the debugging metadata into a debugging information segment in a debugging information recording format, and compiling the debugging information segment and other machine codes into an executable file; the ST debugger starts the GDB through the process control interface and loads the executable file, and the debugging information segment is analyzed through the GDB; the ST debugger sends the debugging command to the GDB through the MI interface, and the GDB debugs the executable file after receiving the debugging command; and the ST debugger receives the feedback information to perform MI interface response analysis. The universal debugging method supports source-level debugging of a universal debugger on a program, improves debugging availability and expansibility, and is irrelevant to a platform and complete in function.

The application belongs to the technical field of device debugging, and relates to a general debugger of a computing device, a debugging system and a debugging method, wherein the debugging method comprises the following steps: a debugging host computer acquires input information and sends the input information to the general debugger; the general debugger performs debugging verification on the input information to determine debugging information; the general debugger selects a bus interface according to a bus type field of the debugging information; the general debugger performs register read and write on the computing device by using the bus interface, and generates debugging result data; and the general debugger acquires the debugging result data and sends the debugging result data to the debugging host computer. The application can independently debug the computing device by using the general debugger; the debugging function can be used to acquire the running condition of a connected device at an interface end of the debugging device; one set of bus interfaces can be used to simultaneously acquire all information of all on-board devices and all machine modules of the computing device, and the application is not limited by different chip address widths and different positions of the chips on the bus.

In some aspects, a method of enhancing security of a computing application. The method includes establishing, by a debugger blocking module of the computing application, a connection to a debugger port associated with the computing application to block other connections to the debugger port. The method further includes determining, by a bypass check module of the computing application, that the debugger blocking module has been modified. The method further includes, responsive to the determining that the debugger blocking module has been modified, performing, by the computing application, one or more actions to protect the computing application from debugger access.

The present invention discloses a method and a system for testbench replication of an assertion counterexample in hierarchical C++ high level synthesis designs, comprising: - defining a high level synthesis (HLS) design for an integrated chip wherein the design of the integrated chip is programmed as a C++ hierarchical design; - verifying the HLS design and reporting inline assertions that are added via calls to an assert function of the high level synthesis design; - using a high level verification engine to debug a falsified assertion thereby providing an executable of the C++ hierarchical design that is built with a gcc compiler along with a gdb based debugger and that is used for the replication of a counterexample to remedy the falsified assertation which is referred to as testbench; - using the counterexample of the high level verification engine to drive the debugging of the falsified assertion with input values of the counterexample that will address the debugging at ac_channel operation level; - creating a database within the testbench being pre-populated with every ac_channel's read / nb_read operations data value being calculated in the counterexample that exist in cone of the falsified property where a falsified assertion has been generated for; - during the execution of the testbench when a read / nb_read operation of an internal ac_channel is performed using the pre-populated ac_channel's read / nb_read operations data value as input value for performing a read / nb_read operation during the debugging of the falsified assertion.

A computer-implemented method for obtaining an access notification as part of a taint analysis when testing a software program. The software program is executed on a hardware target. The hardware target has a memory. During execution of the software program, the software program stores data at least in part of the memory. The method includes: generating input data for the software program by means of a test module; transmitting the generated input data to the software program by means of the test module; monitoring at least one address of the memory by means of a debugger while the software program at least partially processes the transmitted input data; transmitting an access notification to the test module if at least one access is detected at the at least one address of the monitored memory.

The invention belongs to the field of digital signal processing and digital integrated circuits, and particularly relates to a debugger circuit board capable of customizing a communication protocol for high-frequency data processing of a bus encoder and upper computer software of the debugger circuit board, which can realize communication debugging of encoders with common interfaces such as RS485, SSI, BiSS-C, ABZ, USB and the like. Simple hardware design operation display can be realized through the touch panel, data uploading and detailed data display can be realized through USB connection with an upper computer, communication protocol editing and hardware writing can be realized, high-frequency signals of an encoder can be pre-processed by the hardware, the application to different encoder communication protocols is realized, the operation is visual and convenient, the carrying is convenient, and the application range is wide. The method is high in adaptability and suitable for debugging in various occasions.

The invention relates to a debugging data modification method and device, electronic equipment and a storage medium, and the method comprises the steps: when it is monitored that a debugging session is in a starting state, loading and rendering a visual interaction interface, the debugging session is used for debugging the debugging session in a lightweight integrated development environment, and the debugging session is used for debugging the debugging session; establishing communication connection for debugging data interaction between the code debugging plug-in and the debugger; after loading and rendering on the interactive interface are completed, a data initialization request is issued to the code debugging plug-in, initialization data obtained by the code debugging plug-in from the debugger based on the data initialization request are received and displayed on the interactive interface, and the initialization data are in an editable state; when a debugging instruction aiming at the initialized data is detected, issuing the debugging instruction to a debugger through the code debugging plug-in, so that the debugger executes data debugging operation; and receiving and displaying a data debugging result fed back by the code debugging plug-in on the interactive interface. According to the invention, the debugging data modification process is simplified.

This invention discloses a remote verification method and system based on a multi-FPGA verification public cloud platform. The method includes: a user selecting a corresponding resource configuration module from multiple candidate resource configuration templates provided by the cloud platform; receiving the design source file uploaded by the user through an encrypted channel; performing logic synthesis, probe insertion, partitioning, mapping, and top module generation operations to complete the simulation configuration; acquiring and calling computing resources from the computing cluster; generating a bitstream file according to the simulation configuration; allocating corresponding resources from the resource pool according to the simulation configuration; configuring the switching architecture routing table; connecting the resources corresponding to the simulation configuration to build a hardware simulation execution environment; loading the generated bitstream file onto the FPGA chip allocated to the user; configuring the peripheral interface board; connecting the debugger to the peripheral and making it ready; and the user remotely logging into the debugger via a virtual network computing protocol to perform simulation and debugging operations to obtain waveform data, thus completing the remote verification.

The application relates to a software fault diagnosis method for an electronic control unit, which comprises the following steps: monitoring the running state of software in the electronic control unit based on a watchdog timer; when the software fails to reset the watchdog timer within a preset timeout period, generating a timeout event and triggering a non-maskable interrupt associated with the timeout event, executing a corresponding interrupt service program to capture software context information at a fault moment; storing the software context information into a predetermined memory area whose content is maintained after the electronic control unit is reset; and reading the software context information stored in the predetermined memory area through a communication interface after the electronic control unit is reset. The application has the effect that high-value underlying software context information at a fault occurrence moment can be automatically and reliably captured without the need of physically connecting a debugger and without the need of reproducing the fault.

A method for predicting progress of a code development project, comprising: monitoring behavior of a plurality of software developers through interaction with at least an integrated development environment; providing a predictive model of the code development project adapted to predict a future status of the code development project; and outputting a prediction dependent on a status of the code development project at a future time, the interaction comprising: exploration events comprising browsing source code for understanding or investigation; coding events comprising actively modifying source code; debugging events comprising interacting with a debugger stepping through code in a debugging phase; and testing events comprising coding or running unit tests and test automation.

The application provides a simulation debugging system and method of a 51 single-chip microcomputer simulator with double threads, which comprises a debugger for inputting a debugging command, sending the debugging command to the simulator through a communication port after analyzing the debugging command, a main control program of the simulator, a plurality of debugging functions for realizing the debugging command and a checking program for checking an interrupt signal arranged in the main control program, a main thread and a listening thread created, the main thread being used for loading and executing a 51 single-chip microcomputer program, the listening thread being used for information interaction with the debugger, analyzing the received debugging command, calling the corresponding debugging function to execute a debugging operation, and feeding back a debugging result to the debugger. The application establishes communication between the simulator and the debugger and creates double threads, so that the simulator can execute the main thread and realize various debugging operations on the 51 single-chip microcomputer program through the listening thread, thereby realizing the debugging function of the 51 single-chip microcomputer simulator and improving the development efficiency of the single-chip microcomputer.

The invention relates to a data processing device (100), preferably programmable and preferably capable of learning, data processing device (100), for a system (101), in particular a vehicle, comprising: - a computing unit, especially a central one (10), - a learning unit (20), in particular a central one, with a debugger (21), in particular a central one, - a switching unit, in particular a central one (30).

The software agile test tool of the present application comprises a software compiling and debugging environment and a test framework, the software compiling and debugging environment is used for compiling and running the software to be tested, and is provided with a compiler and a debugger; the test framework is a tool provided for a tester for organizing and managing test scripts, automatically running the test scripts, and automatically generating test records and reports; the present application does not make any change to the code to be tested, does not make syntax semantic analysis, and does not reconstruct the code, and only needs to compile the code to be tested once; during the test, only the compiled executable program is loaded into the debugger, then different inputs are set to the code to be tested in the debugger according to different test scripts, the debugger is controlled to run the code to be tested, the software test is completed, and the test result is obtained. The technical advantage of the present application is that the test method based on the reconstruction of the test object is abandoned, and the test method based on the debugger is adopted, and compared with the mainstream software test tool, the efficiency can be greatly improved.

The invention belongs to the technical field of embedded development instruments, and relates to an integrated multifunctional debugger based on a microcontroller. The integrated multifunctional debugger comprises a shell, a main control board, a signal board, a screen, a battery and a rotary encoder. A microcontroller module, a power meter module, a spectrum analyzer module, a PWM output module, a development module and a Bluetooth module are integrated on the main control board, and bus voltage, current and power measurement, spectrum analysis, adjustable PWM signal output, user-defined function development and remote control operation through keyboard Bluetooth can be achieved. The signal board is provided with a logic analyzer module and a USBHUB module and is used for analyzing digital circuit signals. The debugger integrates multiple functions, and solves the problems that a traditional instrument is single in function, large in size and high in cost.

A computer-implemented method for obtaining an access notification as part of a taint analysis when testing a software program, wherein the software program is executed on a hardware target (140), the hardware target (140) having a memory, wherein, during the execution of the software program, the software program stores data in at least a part of the memory, the method comprising: - Generating input data for the software program using a test module; - Transmitting the generated input data to the software program using the test module; - Monitoring at least one memory address using a debugger (138) while the software program processes at least part of the transmitted input data; - Sending an access notification to the test module when at least one access is detected at at least one address of the monitored memory.

The invention provides a mobile storage hardware protection method based on an anti-debugging technology, which comprises the following steps of: monitoring the operation of mobile storage hardware by using a runtime detection mechanism, and judging whether a debugging environment exists or not, the runtime detection mechanism comprising register detection, software breakpoint detection and exception handling detection; if the debugging environment exists in the mobile storage hardware, anti-debugging codes are automatically injected, and normal operation of the debugger is interfered; performing confusion in a key data area of the mobile storage hardware by using a dynamic confusion technology to protect the key data; and introducing a multi-layer encryption mechanism on the key data area to increase the data complexity so as to improve the defensive performance for potential attacks. According to the method, the storage device is monitored and detected in real time, any possible malicious injection behavior is found and stopped in time, and the security and protection capability of data are improved.

This invention discloses a method, apparatus, and device for verifying debugging functions on a hardware-accelerated simulation platform, relating to the field of simulation testing and verification. The method includes deploying the Design Under Test (DUT) and an Embedded Debug Execution Unit (MCU) on the EMU, loading and executing a debugging program on the MCU to generate a debugging command sequence; converting the debugging command sequence into timing drive signals corresponding to the DUT's test interface specification for debugging or tracing interaction with the DUT, obtaining response information, status information, and tracing information returned by the DUT; comparing the DUT's returned information with the target result, and continuing EMU debugging and verification based on the comparison result. This application enables automated debugging and verification without relying on an external physical debugger.