165 results about "Debugger" patented technology

A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux to disconnect an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load / store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

Providing issue resolution in a cluster system by monitoring system operation to detect occurrence of a system error, and automatically generating, upon detection of the error condition, a core file for a user node. The core file captures a current memory state of a respective node, where the current memory state comprises system statistics, system information, and logs. An intelligent core debugger extracts information from a core file to generate a core file report that is sent to a vendor for a quick determination of whether sufficient information is in the report to allow the vendor to recommend a fix, or whether further information from is required, including the core file itself, if necessary. This prevents the need to send an entire core file to a vendor in every instance of a system fault.

A non-transitory computer readable medium is provided comprising instructions that when executed on a processor load a software program into a software debugger for execution on an emulated processor representing a processor portion of a system on chip (SoC), load a hardware design into a hardware simulator representing a programmable gate array portion of the SoC, coordinate execution of software debugger and hardware simulator to simulate operation of the SoC, communicate data between the software debugger and the hardware simulator, and display computed results and current values.

The utility model relates to an MCU simulation debugger with high-voltage isolation protection. The MCU simulation debugger comprises a USB power supply communication circuit module, a first DC step-down circuit, a DC-DC power isolation module, a second DC step-down circuit, a main control chip minimum system, a burning code external storage FLASH control circuit, an off-line burning BURN key detection circuit, a JTAG simulation / IIC burning interface isolation module and a three-section dial switch. A dial switch state detection module; and a machine burning control interface. The JTAG simulation / IIC burning interface isolation module realizes 1500Vrms electrical isolation of a debugging board card and simulator equipment, online simulation debugging of resistance product firmware can be realized, and a software developer does not need to care about the electrical isolation condition of the debugging board card and only needs to concentrate on debugging codes; multi-interface and multi-level high-speed simulation and burning are supported, level switching of a debugging board card is rapidly achieved through a dial-up gear, and the level compatibility of the simulator is improved.

Efficient replacement of software breakpoint instructions in a processor-based device is disclosed. In regard to this, in one exemplary embodiment, a processor-based device is provided. The processor-based device includes a system memory and a processor. The processor includes a breakpoint slip register (BSR) configured to store instructions of a software process that are replaced in system memory by a software breakpoint instruction, and the processor further includes a breakpoint slip enable (BSE) indicator. The processor is configured to execute the software breakpoint instruction during execution of a software process. The processor is further configured to, in response to executing the software breakpoint instruction, transfer program control to the debugger. The processor is further configured to determine that the BSE indicator is set after the program control is returned from the debugger. Further, the processor is configured to, in response to determining that the BSE indicator is set, execute the instructions stored in the BSR.

DLL hooks are protected by mapping the starting address of the new executable to a sample of the former executable. Attempts to read the starting address are responded to with the sample of the former executable. Attempts to write to the starting address are responded to with confirmation of success without actually writing data. Debuggers are detected upon launch or by evaluating an operating system. A component executing in the kernel denies debugging privileges to prevent inspection and modification of DLL hooks.

The invention belongs to the technical field of digital signal processors, and particularly relates to a non-intrusive real-time monitoring debugger for a DSP (digital signal processor). The real-time monitoring debugger comprises a bus monitoring module and a tracking buffer module, and the bus monitoring module and the tracking buffer module jointly complete debugging and obtain real-time operation information. The bus monitoring module is used for monitoring the memory access operation of the DSP, and meanwhile, the tracking buffer module is used for recording execution tracks of a program before and after an event, so that comprehensive and accurate debugging information is provided for a system, and problems occurring in the running process of the DSP can be quickly positioned and solved, and the debugging efficiency is improved; in addition, by arranging a special register, high configurability is achieved, so that monitoring and recording strategies can be flexibly adjusted according to different debugging requirements, and the debugging process is more targeted and efficient.

The invention discloses a chip prototype verification method and device, a medium and a product, relates to the technical field of chip design, is applied to a hardware debugger of a simulation test tool, and comprises the following steps: analyzing a capability maturity model script; the analyzed script and the execution mode switching condition are sent to a central processing unit of the field programmable gate array, so that the central processing unit determines a current execution mode according to the analyzed script and the execution mode switching condition; test case codes of different execution modes in the capability maturity model script are stored in different data areas of a preset memory pool respectively, so that a central processing unit obtains the corresponding test case codes based on the current execution mode, verification data are generated according to the test case codes and peripheral equipment of a pre-configured chip, and the verification data are stored in the preset memory pool; returning the verification data to a hardware debugger of the simulation test tool; and generating a prototype verification report based on the verification data and the expected data to complete chip prototype verification. And chip prototype verification can be realized by dynamically switching verification modes.

Some embodiments find locations of targets which are related to a symbol in a source code snippet, when the snippet is external to a project codebase. Finding a target's location allows user-directed or proactive automatic navigation from the symbol into the codebase, display of data type, signature, and other semantic information of the symbol, proactive automatic creation of an import statement for a definition of the symbol, and other utilizations of the target location in an enhanced editor or enhanced debugger or another tool. In some scenarios, the external snippet is generated by an artificial intelligence agent, using part of the codebase as context. Some embodiments find a target of an external snippet's symbol in another external snippet, allowing a tool utilization that is informed by the project codebase even when both snippets are outside the project codebase.

The invention belongs to the technical field of MCU (Microprogrammed Control Unit) fault monitoring and diagnosis, and particularly relates to an MCU hardware error abnormity monitoring and analyzing method, an MCU hardware error abnormity monitoring and analyzing device and electronic equipment. Comprising the steps that a serial SWD debugging interface is connected with an inner core of a target MCU, a CMSIS-DAP protocol is used for accessing a CoreSight assembly in the target MCU, and R0-R15 registers and a function register of the target MCU are monitored in real time; according to the method, the value of an error register is read in real time to monitor the occurrence time of error abnormity, and after the error abnormity occurs, the read-back states and contents of the R0-R15 registers are utilized, and the numerical value of the stack pressing PC is combined, so that the cause of problem occurrence and the instruction position of error generation are determined. The R0-R15 registers and the special function registers of the ARM are monitored in real time, and the running condition of the chip can be monitored and tracked for a long time without the help of a debugger and an upper computer development environment.

The invention belongs to the field of software testing, and relates to a debugger testing method based on a large language model. The method comprises the steps that firstly, a random function protocol is generated, the random function protocol is constructed by a statement template and semantic constraints, the generated random function protocol serves as a cue word to be input into a large language model, and a function template meeting description of the random function protocol is generated; thirdly, compiling the generated function template, and if compiling of the function template fails, regenerating a function protocol and performing iterative correction until codes meet grammar and semantic constraint requirements; and if the function template is successfully compiled, reserving the function template for subsequent use. And secondly, performing grammar variation on the successfully compiled function template, and outputting a source file after the grammar variation. And combining and compiling the source file output after variation with the corresponding header file and the test case. And generating an executable file after combination and compilation. And finally, inputting the executable file into a debugger for execution, and detecting whether a bug exists or not.

The invention relates to an embedded chip simulation and debugging method and system. The method comprises the following steps: expanding an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set in a GDB debugger, and generating a special debugging front-end program; the method comprises the following steps: expanding a C28x JTAG protocol adaptation module in an OpenOCD debugging agent, and generating a debugging agent program; a C28x instruction set execution simulation unit is realized in the NEMU simulator, and a GDB Server communication module is embedded in the NEMU simulator; seamless switching between a simulation debugging mode and a hardware debugging mode is realized based on a unified configuration file through a software and hardware debugging environment rapid switching control module. The problems that a traditional debugging mode depends on a special hardware simulator, the cost is high and the simulation environment is inaccurate are solved, and through an integrated software and hardware collaborative debugging scheme, the debugging cost is greatly reduced, and the development efficiency and the comprehensiveness of system verification are improved.

Disclosed are systems and methods for debugging program code using a computing system. The disclosed method includes designating a control point in a software application subject to a debugging procedure, and then executing the program code for the software application as a guest application executing within a virtual machine. Upon detection of a virtualization event, the hardware processor transfers program control to a hypervisor which then determines whether the virtualization event corresponds to the designated control point based on an execution state of the guest application. If so, the virtualization event handler may generate a debugging event that is used by a debugger.

According to various implementations, a method for learning a state machine of a program is described, comprising: executing a state machine learning algorithm by means of a host computer system, in which the host computer system controls an embedded system via a debug interface by means of a debugger such that the embedded system executes the program multiple times, and wherein the host computer system, for each execution of the program, detects whether a program segment that has not been reached when a previous program is executed has been reached when the program is executed; and if this case is detected, determining, at least for some of these cases, an input to the program that is not provided to the program by the host computer system and causes the program to reach the program segment, by the host computer system determining, by means of a debugger, a storage area in the memory of the embedded system in which the input is written, the storage area is read out and the determined input is added to an alphabet of a state machine learning algorithm.

A power state framework executes a workload in supported computing device types and configurations during a sequence of power state transitions to simulate user experiences. Workloads can be combined, e.g., default workload plus add-on workload(s). Device states are monitored, collected, reported, and analyzed to identify faults, which are prioritized for repair, e.g., based on the projected impact of the faults on users, e.g., if the users were to experience the faults. Computing device states include states of attached peripheral devices and wireless or wired connectivity before and after power state transitions. Device state indicates device stability throughout supported device power state transitions. Devices under test can be on debuggers during execution of workload and power state transitions. Automated, accelerated simulation of the execution of end user workloads and power state transitions in actual computing devices saves time and avoids replication errors compared to manual user-driven device testing.

This invention relates to the technical field of program burning, and discloses a wireless SWD debugging and burning system and method for a collaborative arm. The wireless SWD debugging and burning method, applied to an SWD debugging and burning device, specifically includes the following steps: S101: Receiving a debugging and burning command sent by a host computer, and setting the embedded pins on the wireless debugging adapter of the ESP32 module. This invention, through a wireless gateway and software protocol simulator built around the ESP32 module, successfully upgrades the debugging and burning link, which previously relied on physical cables and dedicated hardware debuggers, to a fully wireless method. This eliminates the need for technicians to disassemble the device casing for each operation, completely avoiding mechanical wear and sealing failure caused by repeated disassembly and reassembly.

The invention relates to a software fault diagnosis method for an electronic control unit, and the method comprises the steps: monitoring the operation state of software in the electronic control unit based on a watchdog timer, and when the software does not reset the watchdog timer within a preset timeout period, starting the watchdog timer; generating a timeout event, triggering a non-maskable interrupt associated with the timeout event, and executing a corresponding interrupt service program to capture software context information at a fault moment; storing the software context information to a predetermined memory area, wherein the content of the software context information is kept after the electronic control unit is reset; and after the electronic control unit is reset, reading the software context information stored in the predetermined memory area through a communication interface. The method has the effect of automatically and reliably capturing the high-value underlying software context information at the moment of fault occurrence under the conditions that a debugger does not need to be physically connected and the fault does not need to be reproduced.

The invention provides a common debugging method and system for a source code, a byte code and a target code, and belongs to the field of computers, and the method comprises the steps that S1, the source code is converted into the byte code; acquiring a corresponding relationship between the source code and the byte code, and combining the byte code with the source code through the row and column numbers to generate a new source code file; s2, merging the line number information of the source code and the line number information of the byte code to form a new line number; adding the new line number as debugging information to the debugging instruction to obtain an adjusted debugging instruction; s3, when the adjusted debugging instruction is used for debugging the source code file, displaying source code and byte code information at the same time; and an instruction is newly added and is used for performing single-step debugging on the byte code. According to the method, by modifying the debugging information and enhancing the debugger, mixed debugging of the source code, the byte code and the target code is supported at the same time.

The embodiment of the invention discloses a code debugging method and device, equipment and a medium, and relates to the technical field of computers. According to the code debugging method, the target simulation environment and the debugger of the target compiler are integrated, and the debugger of the target compiler can be directly called in the simulation running process to conduct real-time and source code level step-by-step debugging. Moreover, developers can set the breakpoint at the specified position of the source code in the target compiler, and when the source code runs to the breakpoint, the source code is directly debugged through the debugger of the target compiler, so that the problem positioning efficiency and the problem processing efficiency are improved, and the overall development efficiency is improved.

The embedded firmware hybrid symbolic execution test system, method, device and medium provided by the embodiments of the present disclosure comprise an initial converter, a symbolic execution virtual machine and a peripheral debugger; the initial converter fuses high semantic source code and low semantic assembly code in semantics to obtain a hybrid semantic IR file; the symbolic execution virtual machine finds a plurality of behavior paths included in the hybrid semantic IR file and state information of nodes included in each behavior path through a symbolic variable, and generates a test case corresponding to each abnormal trigger node according to the abnormal trigger nodes of the plurality of behavior paths; and the peripheral debugger reproduces and analyzes a test problem according to the test case. The engineering value of test vulnerability verification is improved.

The invention provides an on-chip debugging method, an on-chip debugger, an on-chip debugging system and a storage medium, the method is applied to the on-chip debugger, debugging component resources are pre-configured in the on-chip debugger, and the debugging component resources comprise hardware debugging function components corresponding to different debugging target hardware platforms respectively. The method comprises the steps of obtaining a debugging instruction, wherein the debugging instruction comprises hardware platform attribute information of a debugging target; according to the debugging instruction, target debugging function components are determined from the debugging component resources, the target debugging function components comprise a first target debugging function component, and the first target debugging function component comprises a hardware debugging function component matched with hardware platform attribute information of the debugging target; and based on the target debugging function component, debugging the debugging target. According to the scheme, the on-chip debugging efficiency can be remarkably improved.

The invention relates to homonymous variable analysis, in particular to a method for analyzing homonymous variables in a C language function stack, which comprises the following steps of: receiving a variable viewing command by a debugger, and analyzing a variable name and a variable position from the variable viewing command; the debugger analyzes and obtains all homonymous variables and corresponding action ranges in the function stack from the debugging information of the executable file according to the variable name, and analyzes and obtains a corresponding PC range from the debugging information of the executable file according to the variable position; comparing the PC range with the action range of each homonymous variable, wherein the homonymous variable corresponding to the minimum action range of the PC range is a target variable specified to be checked; according to the inquired variable information, determining a physical position of the target variable in the function stack, reading a memory value of the physical position, and taking the memory value as a variable value specified to be checked and returning the variable value; according to the technical scheme provided by the invention, the defect that the values of the homonymous variables at different positions in the function stack cannot be accurately obtained can be effectively overcome.

A protocol designer for a test and measurement instrument, comprising an input to receive a signal, a memory configured to store the signal, an author configured to generate protocol definitions based on a user input, a debugger configured to output textual and visual decode results based on the protocol definitions and the signal, and a deployer configured to output a compiled protocol definition file to the test and measurement instrument.

A software service such as a daemon monitors traffic at virtual com ports of virtual machines to facilitate debugging of virtual functions in real time as the virtual functions take turns using a hardware resource in round-robin fashion. If the daemon detects that a kernel debugger has initiated a kernel debugging session for a particular virtual function via the com port, the monitor halts world switching between virtual functions allocated to the hardware resource. The daemon makes the virtual function indicated by the kernel debugger the active partition while the kernel debugger reads one or more registers of the hardware resource allocated to the virtual function. When the kernel debugger has completed reading the register(s), the daemon signals the host to resume world switching between the virtual functions.

The invention discloses a reverse debugging increment recording method based on dynamic layering and predictive filtering, which comprises the following steps of: analyzing a binary file division region of a target program, establishing a global region mapping table among an address range, a region type and debugging attributes, executing the binary file by a reverse debugger, constructing a first mapping table for modifying a record circular queue, according to the global region mapping table, performing differentiation recording on the region to form a first record, a stack frame snapshot, a second record and a register block snapshot, and performing repeated coverage filtering to reduce the recorded data volume to form an execution state track; and performing intelligent compression on stack frame snapshots, heap memories, global variable records, register snapshots and variable values in the execution state trajectory, and finally forming a low-overhead and accurate execution state trajectory to support reverse debugging backtracking.

A power state framework executes a workload in supported computing device types and configurations during a sequence of power state transitions to simulate user experiences. Workloads can be combined, e.g., default workload plus add-on workload(s). Device states are monitored, collected, reported, and analyzed to identify faults, which are prioritized for repair, e.g., based on the projected impact of the faults on users, e.g., if the users were to experience the faults. Computing device states include states of attached peripheral devices and wireless or wired connectivity before and after power state transitions. Device state indicates device stability throughout supported device power state transitions. Devices under test can be on debuggers during execution of workload and power state transitions. Automated, accelerated simulation of the execution of end user workloads and power state transitions in actual computing devices saves time and avoids replication errors compared to manual user-driven device testing.

The present disclosure relates to the technical field of computer, and particularly relates to a trap management device, a processor, a chip and an electronic device, which comprises: at least one processing core configured to execute a thread; a processor trap management unit coupled with the at least one processing core; and an interrupt reporting unit coupled with the processor trap management unit; wherein: the processing core suspends execution of the thread and reports a trap event to the processor trap management unit in response to the thread executed therein satisfying a trap condition; and the processor trap management unit performs coordinated management and triggers the interrupt reporting unit to report an interrupt to an external debugger in response to receiving the trap event. According to the embodiment of the present disclosure, the resource utilization efficiency of the processor in a debugging or monitoring scenario can be effectively improved.

The present invention provides a safety protection method and device for high-voltage equipment debugging. Among them, the method includes: obtaining debugging project information, determining the high-voltage equipment to be debugged and several associated devices according to the debugging project information; performing power risk analysis on the high-voltage equipment to be debugged and several associated devices, obtaining a debugging risk coefficient, and determining a safety distance according to the risk coefficient; outputting the safety distance to the debugger, and giving an alarm when the debugger is within the safety distance. The solution of the present invention analyzes the debugging project information to automatically determine the high-voltage equipment to be debugged and associated devices, and analyzes the corresponding debugging risk coefficient, so that the targeted safety distance can be automatically determined, effectively protecting the personal safety of the debugger during high-voltage equipment debugging.

A debugging method and an electronic device relate to the technical field of computers, and dynamically call a debugging interface of a second programming language by registering the debugging interface of the second programming language in a first programming language debugger, thereby obtaining call stack information and variable information of the second programming language, setting breakpoints, modifying variables and the like. In the method, the electronic equipment displays a debugging interface of a debugger adaptive to a first programming language, and loads a service program which is subjected to mixed programming by adopting the first programming language and a second programming language to test equipment. A runtime debugging interface is configured in the runtime matched with the second programming language. During debugging, when a service process runs to a first service code segment obtained by programming of a first programming language, a debugging breakpoint is entered, and the electronic equipment calls a runtime debugging interface through a debugger registered with the runtime debugging interface; and executing debugging processing operation on a second business code segment obtained by programming in the business program loaded by the test equipment by adopting the second programming language.

1. Name of the product in this design: Circuit board debugger housing. 2. Purpose of this design: Housing for a circuit board debugger. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: 3D view 1.