111 results about "Instruction memory" patented technology

The present application discloses a compute-in-memory chip, an instruction scheduling method, and a related apparatus. The compute-in-memory chip comprises an instruction memory, an instruction scheduler, and at least one compute-in-memory memory; each compute-in-memory memory comprises at least one storage array; the instruction memory is used for acquiring a first tensor instruction to be executed; and the instruction scheduler is used for scheduling, on the basis of the association relationship between the first tensor instruction and a second tensor instruction and the state of a target storage array needing to be operated for executing the first tensor instruction, the first tensor instruction to the compute-in-memory memory to which the target storage array belongs so that the compute-in-memory memory executes the first tensor instruction. According to embodiments of the present application, diversified compute-in-memory computing can be supported, efficient out-of-order execution scheduling of a tensor instruction set is achieved on the basis of the compute-in-memory chip, and the requirements of compute-in-memory technology for high concurrency and high throughput rate are met.

An I / O circuit block comprising:a register unit;an input / output unit connected to a plurality of terminals;an instruction memory; anda state machine configured to execute a program stored in the instruction memory to transfer data between the register unit and the input / output unit.The state machine is configured to execute instructions of an instruction set, the instruction set consisting of: an IN instruction to transfer a specified number of bits into the register unit; and an OUT instruction to transfer a specified number of bits from the register unit; a JMP instruction; a WAIT instruction; a PUSH instruction; a PULL instruction; a MOV instruction; an IRQ instruction; and a SET instruction.

A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux to disconnect an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load / store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

A system comprises pulse instruction memory and pulse generation circuitry, wherein the pulse generation circuitry is operable to retrieve a pulse instruction from the pulse instruction memory, and concurrently generate one or more analog pulses based on a first one or more fields present in the pulse instruction, and one or more digital pulses based on a second one or more fields present in the pulse instruction.

Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.

A system for autonomous compliance with legal regulations in smart contracts; the system includes: a regulatory data collection unit comprising a network interface controller physically connected to an external communications port, a hardware-based public key infrastructure circuit configured to validate digital certificates of regulatory servers, and a direct memory access controller configured to transfer authenticated regulatory update packets from the network interface controller to a volatile buffer memory without processor intervention; a Compliance Code Conversion Unit with a hardware lexicon scanner implemented as a finite state machine and embedded in reconfigurable FPGA logic blocks, a microcontroller executing a hardware-based lexical analysis pipeline stored in firmware registers, and a translation cache memory configured to temporarily store tokenized compliance rules before writing them to a non-volatile instruction memory; a policy evaluation and enforcement unit comprising a transaction verification processor connected to a secure enclave memory, a hardware comparator circuit configured to compare transaction parameters with compliance thresholds stored in the secure enclave memory, and a logic gate circuit configured to generate execution gate signals that selectively allow, block, or modify smart contract execution signals transmitted to a blockchain execution processor; and an audit logging unit with a cryptographic hashing circuit configured to generate block hashes of enforcement records, a timestamp oscillator configured to generate temporal signatures of compliance enforcement actions, and a Merkle tree generation circuit configured to create tamper-proof hierarchical hash structures, with the enforcement records being passed to a decentralized storage interface for anchoring in the chain or distributed ledger.

The invention provides a lightweight elliptic curve cryptographic reconfigurable processor. The reconfigurable computing unit array comprises a shared data area and a reconfigurable instruction memory, the shared data area is used for an upper layer system to write initial data, global configuration parameters, two sets of moduli, two sets of pre-computing parameters Mu and to-be-computed data, the initial data comprises elliptic curve configuration parameters and a group of noise data, and the global configuration parameters comprise reconfigurable data of the computing unit array; the reconfigurable instruction memory is used for an upper-layer system to write reconfigurable instructions, and the reconfigurable instructions comprise an initialization instruction, an operation instruction and a jump instruction. The method can cope with application scenes such as high security, low power consumption, rapid switching and reconstruction of the ECC algorithm, can be flexibly applied to the fields of national password security, network security teaching and commercial password, and has a wide application prospect.

The present application relates to the field of integrated circuit technologies and provides a training system and method for a high-speed parallel port IP. The system includes: a high-speed transceiver for transmitting and receiving data and command signals; a delay and reference voltage regulator for performing delay adjustment and reference voltage adjustment; a multi-branch generator for separately generating command combinations, data sequences, and adjustment signals; a microprocessor for controlling the generation of the multi-branch generator based on a first instruction combination; and an instruction memory for storing the first instruction combination. The microprocessor is further configured to generate, based on the first instruction combination, a first scanning strategy including a first scanning object, which is determined based on a first high-speed parallel port IP. The microprocessor controls the generation of the multi-branch generator to utilize the delay and reference voltage regulator to implement the first scanning strategy for the first scanning object in the data and command signals so as to complete eye diagram adaptation. In this way, flexibility and compatibility are achieved.

The invention discloses an intelligent heterogeneous radar hardware accelerator applied to rail transit, and belongs to the technical field of radar signal processing and integrated circuits. The accelerator is based on an SoC FPGA platform, a microprocessor soft core based on an RISC-V instruction set is constructed at an FPGA end, and an FFT calculation module and a CFAR calculation module are integrated to serve as hardware acceleration units. And the microprocessor soft core dynamically schedules each hardware acceleration unit by executing a program stored in the instruction memory, constructs a reconfigurable data path, and completes a radar signal processing flow. The method overcomes the defects of power consumption, communication bandwidth and flexibility of traditional DSP and FPGA schemes, and is particularly suitable for efficient and real-time detection and identification of roadbed structure damage in rail transit.

The invention belongs to the field of neural network hardware acceleration, and provides a Softmax instruction set extension method and system based on RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method comprises an instruction fetching stage, in the decoding stage, corresponding instruction functions are analyzed for Opcode, Funct7 and Funct3 of the Softmax instruction, and corresponding control signals are generated. In the execution stage, data to be subjected to Softmax operation is taken out from the data memory and transmitted into the Softmax calculation unit according to a control signal; executing Softmax calculation according to the following formula, and writing a Softmax calculation result back to the target register; the calculation process is divided into four sub-modules of maximum solution, index calculation, summation and normalization, and a hardware acceleration strategy is designed, so that the operation delay and the resource overhead are greatly reduced, the degree of parallelism, the precision and the energy efficiency ratio of calculation are effectively improved, and the method is suitable for a high-performance neural network reasoning acceleration scene.

This invention belongs to the field of computer technology and relates to an angle calculation system based on CORDIC instructions. The system includes an IFU (Instruction Fetch Unit) and an EXU (Execution Unit). During the instruction fetch phase, the IFU reads CORDIC instructions from the instruction memory according to the address of the PC. The EXU includes a decoding module, an arithmetic logic unit, a load-memory unit, and a write-back unit. This invention extends the CORDIC angle calculation instruction set based on the RISC-V architecture and designs a complete pipelined hardware structure, supporting trigonometric function operations. It has a complete CORDIC operation path hardware circuit structure, reusing the same operation path for different operation processes, improving hardware resource utilization. It overcomes the limitation of convergence of the calculation result range when performing angle calculation based on the CORDIC algorithm by pre-storing special angle results to reduce calculation time and optimize the circuit operating frequency.

In one aspect, a system-on-a-chip (SoC) includes a plurality of programmable channels. The SoC includes an analog front end in communication with the plurality of programmable channels. The SoC includes a processing element array configured to receive output signals from the analog front end. The SoC includes an instruction memory supporting an instruction set architecture for supervising computing task of the processing element array, wherein the instruction memory comprises infinite impulse response instructions, discrete Fourier transform instructions, convolutional layer instructions, and fully connected layer instructions, wherein the processing element array is configured to execute instructions in the instruction memory, which, when executed, cause the processing element array to perform functions of a confusion matrix based teach-student convolutional neural network for low power and low latency, and perform functions of a sparsity controller for lower power.

The invention relates to a performance counting device and a chip, and the performance counting device comprises a performance counting module which is used for receiving at least one instruction memory address from a program counter associated with the performance counting module, and according to the at least one instruction memory address and a pre-configured instruction memory address interval, counting the at least one instruction memory address; obtaining a statistical value of a performance signal of at least one instruction memory address in the instruction memory address interval; the storage module is used for storing the statistical value of the performance signal of the at least one instruction memory address of the performance statistical module; the write-in control module is used for writing the statistical value, obtained by the performance statistical module, of the performance signal of the at least one instruction memory address into the storage module; and the configuration module is used for configuring an instruction memory address interval of the performance statistics module. According to the method and the device, the configuration flexibility of performance statistics can be improved, performance statistics of a plurality of specified program segments can be realized at the same time on the basis, and parallel processing of the performance statistics and accurate positioning of the program segments are further realized.

A printed circuit board (PCB) wiring automatic design method in a PCB wiring automatic design system, the system including at least one processor and at least one memory including an instruction, and the PCB wiring automatic design method performed in cooperation with the instruction, the memory, and the processor, includes: receiving PCB data including a net list and information on a plurality of terminals; updating a cost of a wiring exploration region so that a cost of at least some of the wiring exploration region is increased based on a preset constraint condition; exploring a shortest path for wiring the plurality of terminals according to the net list in a cost-updated wiring exploration region; and performing wiring of the plurality of terminals based on wiring probability according to the shortest path.

The application discloses a FLASH-based data access method, comprising the following steps: obtaining a next data storage starting address, executing a data storage instruction by a FLASH memory, and detecting whether there is a data reading instruction; detecting the data reading instruction, stopping the data storage instruction execution by the FLASH memory and executing the data reading instruction; and if the data reading instruction is not detected, continuing the data storage instruction execution by the FLASH memory. The FLASH-based data access method, the address cyclic storage mode in the address space, compared with erasing the FLASH each time the address is updated, reduces the number of times of FLASH erasing in the address space, increases the service life of the FLASH, organizes the storage and reading data, and maximizes the use of the FLASH storage space to store more data.

A digital data processor (100) comprising: an instruction memory (121) storing instructions, each of the instructions specifying a data processing operation and at least one data operand field; an instruction decoder (113) coupled to the instruction memory for sequentially retrieving instructions from the instruction memory and determining the data processing operation and the at least one data operand; and at least one arithmetic unit (110) coupled to a data register file (123) and to the instruction decoder for performing a data processing operation on at least one operand corresponding to an instruction decoded by the instruction decoder and storing the result of the data processing operation. The arithmetic unit is configured to increment a histogram value in response to a histogram instruction by incrementing a bin entry at a specified location in at least one histogram of a specified number.

The invention relates to histogram operation. A digital data processor (100) includes: an instruction memory (121) storing instructions each specifying a data processing operation and at least one data operation digit segment; an instruction decoder (113) coupled to the instruction memory for sequentially invoking instructions from the instruction memory and determining the data processing operation and the at least one data operand; and at least one arithmetic unit (110) coupled to the data register file (123) and to an instruction decoder to perform a data processing operation on at least one operand corresponding to an instruction decoded by the instruction decoder and to store a result of the data processing operation. The arithmetic unit is configured to incrementing a histogram value in response to a histogram instruction by incrementing a bin entry at a specified location in at least one histogram of a specified number.

Multi-agent instruction execution engines for neural inference processing are provided. In various embodiments, a neural core is provided. The neural core includes an instruction memory. The instruction memory comprises a plurality of instruction streams, each instruction stream associated with one of a plurality of agents. The instruction memory further comprises a plurality of shared functional units. The neural core is adapted to concurrently execute the plurality of instruction streams on the plurality of associated agents. The execution includes maintaining a separate program counter for each of the plurality of agents, determining a plurality of operations from the instructions of each instruction stream, and directing the operations to the shared functional units. The instructions of each instruction stream are statically scheduled prior to runtime to ensure their execution is conflict free.

A processor (100) has: an instruction memory (114) configured to store processor instructions; a data memory (120) configured to store processor data representing an array, the array comprising a plurality of data elements; a controller (102); and an instruction pipeline (104). The instruction pipeline includes: a load stage circuit (126) configured to load array elements from the data memory; a comparison stage circuit (128) configured to compare the array elements to a reference value; a storage stage circuit (130) configured to store a result set comprising a result of the comparison of the array element with the reference value; and a loop hit detection stage circuit (132) configured to determine whether any of the set of results is associated with a hit for the reference value.

The invention discloses an address vector table instruction fetching method and device based on a finite-state machine. The method comprises the steps that the finite-state machine used for reading an address vector table is arranged; a multiplexer is arranged, a first data input port and a second data input port respectively acquire a next instruction counter and an address vector table, and a signal input port is selected to acquire the state of the finite-state machine; the multiplexer selects a next instruction counter or address vector table according to the state of the finite-state machine, and assigns the instruction counter or address vector table to the instruction counter through an output port; when the finite-state machine is in a first state, the current instruction fetching unit is used for reading an instruction from the instruction memory; when the finite-state machine is in a second state, the finite-state machine is sending a request for reading an address vector table to the instruction memory; and when the finite-state machine is in the third state, the finite-state machine successfully sends a request for reading the address vector table to the instruction memory. According to the method, the finite-state machine and the multiplexer are arranged, so that efficient fetch of the address vector table is realized.

The embodiment of the invention discloses a microcontroller and an operation method thereof. The microcontroller includes a processor, an instruction memory, and an instruction read circuit. The instruction reading circuit comprises a cache, a decoder, a branch predictor and an address arbiter. And the cache receives the current instruction address I sent by the processor. And the decoder obtains an instruction corresponding to the next instruction address I + 1 from the cache, decodes the instruction and judges whether the instruction is a branch instruction or not. When the instruction corresponding to the instruction address I + 1 is a branch instruction and jumps, the branch predictor determines a target instruction address J; and the target instruction address J is arbitrated by the address arbiter and then is sent to the instruction memory. And the instruction reading circuit reads instructions corresponding to the target instruction address J to the instruction address J + P from the instruction memory and stores the instructions in the cache. And if the processor requests to access any instruction address from the target instruction address J to the instruction address J + P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, so that the instruction fetching speed of the processor is increased.

A quantum-computing control system includes a script processor, an instruction memory, an instruction fetcher, and a waveform player. The instruction memory stores a plurality of local instructions forming a local instruction set. The script processor executes a local script and transmits to the instruction fetcher a sequence of fetch commands that is based on the local script. The instruction fetcher retrieves, based on each fetch command of the sequence of fetch commands, a fetched instruction from the instruction memory. The fetched instruction belongs to the local instruction set. The instruction fetcher also transmits, to the waveform player, the fetched instruction as one of a sequence of fetched instructions. The waveform player executes the sequence of fetched instructions to generate a digital waveform. The control system may be used to implement mid-circuit (i.e., during runtime) non-sequential control flow of a quantum computer or other type of quantum-engineered system.

To provide an information processing device that can reduce development man-hours and lower vulnerabilities. [Solution] The memory 10 of the information processing device 1 stores a secure function module 111a that contains instructions to be executed by the processor 20 in the performance of a function and is restricted from external interference. The memory 10 also stores a processing function module 131 that contains instructions common to the secure function module 111a, has less restrictive external interference than the secure function module 111a, and is processed into a disabled state in which the processor 20 cannot execute instructions. The memory 10 also stores a release module 112 that has more restricted external interference than the processing function module 131 and can release the disabled state in the processing function module 131. The memory 10 also stores a security request determination flag 115 that defines the security level required in the performance of a function.

To provide a memory control circuit of a micro computer that can enhance a processing speed of the micro computer in comparison with conventional arts.SOLUTION: A micro computer memory control circuit comprises: a memory read control circuit that stores an address where a processor reads a command from a memory, and a next address in a memory address register, stores a command of the address and a command of a next address in a command memory, and stores the next address and a command of the next address in a first command cache; and a cache controller that, when the processor reads a next command from the memory, if the address stored in the memory address register and the address stored in the first command cache are mismatched, stores the address stored in the memory address register, the command of the address and a frequency of the mismatch in a second command cache.SELECTED DRAWING: Figure 1

A quantum-computing control system includes a script processor, an instruction memory, an instruction fetcher, and a waveform player. The instruction memory stores a plurality of local instructions forming a local instruction set. The script processor executes a local script and transmits to the instruction fetcher a sequence of fetch commands that is based on the local script. The instruction fetcher retrieves, based on each fetch command of the sequence of fetch commands, a fetched instruction from the instruction memory. The fetched instruction belongs to the local instruction set. The instruction fetcher also transmits, to the waveform player, the fetched instruction as one of a sequence of fetched instructions. The waveform player executes the sequence of fetched instructions to generate a digital waveform. The control system may be used to implement mid-circuit (i.e., during runtime) non-sequential control flow of a quantum computer or other type of quantum-engineered system.

The application discloses an FPGA-based target detection neural network accelerator and a target detection system, the accelerator is arranged on an FPGA and comprises a control module, an input buffer module, a parameter buffer module, a systolic array module, a post-processing module and a pooling module; the control module comprises an instruction memory and a controller; the instruction memory is used for storing an instruction set of a neural network; the controller is used for generating control instructions according to the instruction set and controlling the operation of each module; the input buffer module is used for storing input feature data blocks of the target detection neural network; the parameter buffer module is used for storing bias data and weight data of the target detection neural network; the systolic array module is used for performing convolution operation; the post-processing module is used for processing the convolution calculation result; the pooling module is used for performing maximum pooling operation on data; and the output buffer module is used for reading and writing cache of data. The application improves the inference efficiency of the accelerator by configuring parameters of the target detection neural network, and realizes the high-performance and high-flexibility target detection neural network accelerator.

Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.

Circuits and methods for implementing one or more handover subprocess instructions are described. In some examples, a hardware processor (e.g., a core) includes (e.g., a coupling to) a memory management circuit to control memory access based on a memory tag stored in a memory tag data structure and a memory tag based on a pointer to the memory; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising an operand to identify a memory tag data structure for a sub-process of a plurality of memory tag data structures for a corresponding sub-process of a process and an opcode, the operand to identify a memory tag data structure for the sub-process of the process. The opcode is used for indicating the execution circuitry to switch from another memory tag data structure for another sub-process of the process to a memory tag data structure for the sub-process; and execution circuitry to execute the decoded instruction according to the opcode. The memory tag data structure may be resumed for providing access control permissions for sub-processes per memory particle.

The present invention discloses a system for implementing an asymmetric algorithm multi-core parallel architecture using a single instruction memory for multiple lightweight processors. The system comprises an AXI bus, an interface terminal, an ultra-high-speed interface, a high-speed interface, a master processor, an instruction register, an asymmetric key memory, and multiple lightweight processors. Each lightweight processor is connected to an asymmetric algorithm core and an asymmetric interface memory, and each lightweight processor is connected to the instruction register and the asymmetric key memory. The asymmetric key memory, asymmetric interface memory, interface terminal, ultra-high-speed interface, high-speed interface, and master processor are all connected to the AXI bus. Advantages of the system include: using one instruction memory to provide instruction reading for multiple lightweight processors and one asymmetric key memory to provide asymmetric keys for multiple lightweight processors to implement an asymmetric algorithm chip with a reduced area, thereby reducing costs and preventing excessive heat generation during chip operation.

The invention discloses a variable register block structure supporting different scene applications of an MCU chip, and belongs to the technical field of chip design, the variable register block structure is applied to the MCU chip, the MCU chip comprises a core, an instruction memory, a data memory and a variable register block, the core is used as a main device, and the instruction memory is used as an auxiliary device. The register block module, the instruction memory, the data memory and the variable register block are used as slave devices; wherein the core is respectively connected with the instruction memory, the data memory and the variable register group through a bus; and the variable register group is used as slave equipment and accesses registers in the variable register group through the core. The variable register block disclosed by the invention can be used as different functional modules in different working scenes; by using the variable register block structure, more flexible and changeable applications can be provided, and meanwhile, the relatively fixed area and power consumption can be reduced; and a certain protection effect is also achieved for the exposure risk of starting the ROM.