39 results about "Instruction memory" patented technology

A system comprises pulse instruction memory and pulse generation circuitry, wherein the pulse generation circuitry is operable to retrieve a pulse instruction from the pulse instruction memory, and concurrently generate one or more analog pulses based on a first one or more fields present in the pulse instruction, and one or more digital pulses based on a second one or more fields present in the pulse instruction.

Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.

The invention discloses an intelligent heterogeneous radar hardware accelerator applied to rail transit, and belongs to the technical field of radar signal processing and integrated circuits. The accelerator is based on an SoC FPGA platform, a microprocessor soft core based on an RISC-V instruction set is constructed at an FPGA end, and an FFT calculation module and a CFAR calculation module are integrated to serve as hardware acceleration units. And the microprocessor soft core dynamically schedules each hardware acceleration unit by executing a program stored in the instruction memory, constructs a reconfigurable data path, and completes a radar signal processing flow. The method overcomes the defects of power consumption, communication bandwidth and flexibility of traditional DSP and FPGA schemes, and is particularly suitable for efficient and real-time detection and identification of roadbed structure damage in rail transit.

The invention relates to a performance counting device and a chip, and the performance counting device comprises a performance counting module which is used for receiving at least one instruction memory address from a program counter associated with the performance counting module, and according to the at least one instruction memory address and a pre-configured instruction memory address interval, counting the at least one instruction memory address; obtaining a statistical value of a performance signal of at least one instruction memory address in the instruction memory address interval; the storage module is used for storing the statistical value of the performance signal of the at least one instruction memory address of the performance statistical module; the write-in control module is used for writing the statistical value, obtained by the performance statistical module, of the performance signal of the at least one instruction memory address into the storage module; and the configuration module is used for configuring an instruction memory address interval of the performance statistics module. According to the method and the device, the configuration flexibility of performance statistics can be improved, performance statistics of a plurality of specified program segments can be realized at the same time on the basis, and parallel processing of the performance statistics and accurate positioning of the program segments are further realized.

A printed circuit board (PCB) wiring automatic design method in a PCB wiring automatic design system, the system including at least one processor and at least one memory including an instruction, and the PCB wiring automatic design method performed in cooperation with the instruction, the memory, and the processor, includes: receiving PCB data including a net list and information on a plurality of terminals; updating a cost of a wiring exploration region so that a cost of at least some of the wiring exploration region is increased based on a preset constraint condition; exploring a shortest path for wiring the plurality of terminals according to the net list in a cost-updated wiring exploration region; and performing wiring of the plurality of terminals based on wiring probability according to the shortest path.

The application discloses a FLASH-based data access method, comprising the following steps: obtaining a next data storage starting address, executing a data storage instruction by a FLASH memory, and detecting whether there is a data reading instruction; detecting the data reading instruction, stopping the data storage instruction execution by the FLASH memory and executing the data reading instruction; and if the data reading instruction is not detected, continuing the data storage instruction execution by the FLASH memory. The FLASH-based data access method, the address cyclic storage mode in the address space, compared with erasing the FLASH each time the address is updated, reduces the number of times of FLASH erasing in the address space, increases the service life of the FLASH, organizes the storage and reading data, and maximizes the use of the FLASH storage space to store more data.

To provide an information processing device that can reduce development man-hours and lower vulnerabilities. [Solution] The memory 10 of the information processing device 1 stores a secure function module 111a that contains instructions to be executed by the processor 20 in the performance of a function and is restricted from external interference. The memory 10 also stores a processing function module 131 that contains instructions common to the secure function module 111a, has less restrictive external interference than the secure function module 111a, and is processed into a disabled state in which the processor 20 cannot execute instructions. The memory 10 also stores a release module 112 that has more restricted external interference than the processing function module 131 and can release the disabled state in the processing function module 131. The memory 10 also stores a security request determination flag 115 that defines the security level required in the performance of a function.

A memory device includes a memory bank including one or more bank arrays, a PIM circuit configured to perform an operation logic processing operation, and an instruction memory including a first instruction queue segment to an mth instruction queue segment configured in a circular instruction queue to store instructions provided by a host, wherein the instructions stored in the first instruction queue segment to the mth instruction queue segment are executed in response to an operation request from the host, and each new instruction provided by the host is updated on the fully executed instructions in the circular instruction queue.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to record an entry into a virtual integrity register. The entry is based on a measurement of a module. The module is a part of a confidential computing environment. The machine-readable instructions further include instructions to load the module into a memory. The memory is accessible by the confidential computing environment. The machine-readable instructions further include instructions to record an entry of a log. The log comprises a load history. The entry comprises information about the loading of the module. The machine-readable instructions further include instructions to record an entry into an integrity measurement register. The entry being based on the recorded virtual integrity register entry.

A memory apparatus includes an instruction memory and a plurality of micro control units. The instruction memory outputs a plurality of instruction codes at a predetermined time interval in accordance with a plurality of address signals and a plurality of divided clock signals. The plurality of micro control units are coupled to each of a plurality of memory regions, provide each of the plurality of address signals to the instruction memory in accordance with each of the plurality of divided clock signals, and perform operations in accordance with corresponding instruction codes among the plurality of instruction codes.

An electronic device and a method for correcting the contrast ratio of an image, and a storage medium are provided. The electronic device comprises: at least one processor including a processing circuit; and a memory for storing instructions to be executed by the at least one processor. The instructions stored in the memory are configured to instruct the electronic device to: obtain, from a luminance histogram of the image, a first probability distribution function of luminance that includes a first plurality of Gaussian functions; determine a threshold value from the first probability distribution function of luminance; determine a scale factor of luminance when the threshold value is less than or equal to a preset first value; perform a first luminance correction operation of correcting luminance on the basis of the scale factor; correct the luminance of respective blocks obtained by dividing the image by a preset size; correct the luminance of the entire area of the image; determine, on the basis of the average luminance of the image, a gamma parameter to which a threshold value is applied; and, on the basis of the gamma parameter, generate a corrected image by correcting luminance.

The application discloses a program dynamic updating method and a digital signal processing system. The program dynamic updating method comprises the following steps: executing a pause instruction belonging to an instruction set in a program running on a DSP core; in an execution stage of the instruction, the DSP core enters an idle state specified by an immediate number in the instruction, and stops accessing all memories, at this time, an external host controls to modify the code in an instruction memory; after the idle state ends, the DSP core resumes running according to a previously saved pipeline state. Through the integration of a special pause instruction and a matching hardware cooperative control mechanism, the application fundamentally solves the bus access conflict, the pipeline timing destruction and the multi-cycle instruction adaptation problem during the program dynamic updating, and realizes the safe, real-time and reliable online updating.

This provides a processor and processor architecture adapted to parallelize multiple instructions moving between two poles (strict allocation used in SIMD / MIMD architectures) at a user-defined granularity, by making the wall between instruction slots and PEs fluid. [Solution] The processor includes an instruction memory, a decoder that converts instructions into opcodes and enable signals, a controller that provides instructions to the decoder, and a plurality of processing elements that operate according to the operation codes provided to the input of a target processing element during a time slot to apply mathematical operations to input data elements and generate output data elements. The enable signals control the assignment of opcodes to the processing elements. The interconnection circuit is adapted to provide one of the opcodes to any of the processing elements in each time slot and operates according to the enable signals.

The embodiment of the invention provides a processing method and device of a processor, a storage medium and electronic equipment, and relates to the technical field of computers, a peripheral interface of the processor is used for being connected with a peripheral, and the method comprises the steps of receiving an interrupt request and a priority request of the peripheral, and adjusting the priority of the peripheral according to the priority request and a priority adjustment range corresponding to the peripheral; adjusting the priority of the peripherals; processing the interrupt request by using a processor core according to the adjusted priority; and / or, responding to the determined key process, accessing an instruction memory space of the key process, and determining a target instruction of the key process; detecting a memory space required by the target instruction; and adjusting the memory space of the key instruction according to the memory space required by the target instruction and the unused special space. In this way, the service quality performance of the processor and the balance of the overall performance of the processor are improved through real-time adjustment of the priority and / or real-time adjustment of the memory space of the key process.

The application discloses an adaptive NVM reading method and a device thereof. The reading device is a medium interface controller, which comprises a medium interface, a local cache, a micro instruction memory, an error correction code decoder and a cache management unit. The medium interface is coupled with the micro instruction memory, the local cache and the cache management unit. The cache management unit is further coupled with the local cache, and the cache management unit provides a reading pause signal to the medium interface according to the available space size in the local cache. The cache management unit of the application manages the operation related to the use of the local cache in a manner independent of the micro instruction, thereby avoiding introducing excessive complexity due to the expansion of the micro instruction.

The present disclosure generally relates to offloading the orchestration and control of a communication collective to a specialized collective offload engine. The systems, methods, and specialized computing hardware described herein avoid the latencies and other inefficiencies introduced when software applications control the execution of a communication collective. For example, the described systems, methods, and specialized computing hardware generate a binary representation of one or more direct acyclic graphs of node operations for a communication collective, and load this representation into the instruction memories of specialized collective offload engines residing on network endpoints connected to one or more network switches. During execution of the collective, the collective offload engines initiate node operations based on whether corresponding dependencies are met. By offloading these tasks to the collective offload engines, no additional latencies are introduced and other computing resources are kept free for use by other applications.

The invention provides a processor, a board card and electronic equipment, the processor comprises an instruction memory, an instruction decompression module, an instruction execution module and a data memory, the instruction memory is used for storing a compression instruction; the instruction decompression module is used for decompressing the compression instruction and generating a corresponding instruction to be processed; the instruction execution module is used for executing the instruction to be processed; the data memory is used for storing to-be-processed data and corresponding processing results; wherein the compression instruction comprises instruction parameters, and the instruction parameters comprise an operation code, an input data base address, a loop parameter and a step length parameter. According to the processor provided by the embodiment of the invention, the execution efficiency of the processor is improved.

The invention discloses a game auxiliary information obtaining method, device and equipment and a readable storage medium, and the method comprises the steps that a game runs through a virtual running environment of a terminal, and an initial game instruction of the game needs to be translated into an instruction capable of being executed by the terminal; obtaining an instruction memory address and instruction parameter information of a first game instruction in response to the fact that the first game instruction of the game is translated; when the instruction memory address is matched with a preset global address, the auxiliary information is obtained based on the memory address indicated by the instruction parameter information, and the global address is determined in advance based on a function used for indicating the auxiliary information in the game. Related instruction information is obtained in an instruction translation layer of a simulation running environment, game functions and parameters which are currently executed can be accurately recognized under the condition that a game memory is adjusted, and then game data needed by auxiliary functions are obtained according to the information. And more selectable game auxiliary information conforming to game regulations is provided for the user.

The invention relates to an Internet of Things equipment communication method adapting to a severe network environment and a computer system, and belongs to the technical field of communication. Comprising the following steps that when a master station side application program issues a control instruction to terminal equipment, the master station side application program creates an instruction memory block used for storing the control instruction received by the terminal equipment, the control instruction is stored in the instruction memory block, a monitoring program of the instruction memory block scans the instruction memory block regularly, and when the terminal equipment is online, the monitoring program of the instruction memory block sends the control instruction to the terminal equipment; and issuing the control instruction to the terminal equipment. When the master station side application program issues the control instruction to the terminal equipment, the control instruction is stored in the instruction memory block created by the master station side application program, the monitoring program of the instruction memory block regularly scans the instruction memory block, and when the terminal equipment is online, the control instruction is issued to the terminal equipment, so that the control instruction is prevented from being damaged when the terminal equipment is offline. Therefore, the reliability of communication between the master station side and the terminal equipment side is effectively improved.

This application discloses a quantum control system and an instruction execution method. The quantum control system includes: a scheduler, an instruction memory, a plurality of processing units, and corresponding private instruction caches (PICs). The scheduler is configured to determine k sub-circuits executed in parallel in a quantum circuit, k being an integer greater than 1 and not greater than n; obtain instructions respectively corresponding to the k sub-circuits from the instruction memory, and respectively store the instructions into PICs respectively corresponding to k processing units. A target processing unit of the k processing units is configured to obtain an instruction corresponding to a target sub-circuit of the k sub-circuits from a PIC corresponding to the target processing unit for execution, the k processing units executing respective corresponding instructions in parallel. A solution of sub-circuit-level parallelism disclosed in this application has better scalability when facing more complex quantum applications and ever-increasing qubits.

A kind of coprocessor and operation system for implementing elliptic curve cryptography algorithm, the coprocessor includes instruction memory and multiple microcode type coprocessor cores, instruction memory is used to store instruction flow written according to preset instruction set, and the instruction set is the set of instructions that microcode type coprocessor core can identify and execute;Multiple microcode type coprocessor cores are used to obtain instruction flow, and the mathematical operation required by elliptic curve cryptography algorithm is executed in parallel according to the instruction in instruction flow.This application can be written according to the algorithm needs instruction flow, improve the algorithm flexibility;Multiple microcode type coprocessor cores parallel operation, improve the algorithm performance.

A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

A method and instruction memory for processing acoustic images of a downhole casing to determine perforations of the tubular. The images may be acquired by an acoustic logging tool deployed into cased well. A Machine Learning model is trained to recognize regions of the acoustic images that are perforations or not, in order to calculate geometric properties of the perforation and overall casing. Renderings of the imaged casing may be overlaid with contours and properties of perforations to improve perforation, fracturing and producing operations.

The invention relates to a network processor and a chip, and the method comprises the steps: an instruction prefetching module generates a prefetching instruction request according to a prefetching instruction address and a thread identifier of a target thread, and transmits the prefetching instruction request to an instruction memory; the instruction preprocessing module obtains a target instruction block returned by the instruction memory, stores a first special instruction in the target instruction block and a plurality of previous instructions in the instruction cache module, obtains a next prefetch instruction address according to the first special instruction, and if prediction succeeds, sends the next prefetch instruction address to the instruction cache module; if not, sending the predicted next prefetch instruction address, the thread state information and the corresponding thread identifier to an instruction prefetch module; the instruction pre-fetching module generates a new pre-fetching instruction request according to the next pre-fetching instruction address, the thread pre-fetching control signal and the corresponding thread identifier output by the instruction preprocessing module, and sends the new pre-fetching instruction request to the instruction memory, through the application, the instruction pre-fetching time delay of the processor can be reduced.

The invention discloses a direct memory access (DMA) engine system for satellite-borne synthetic aperture radar (SAR) in-orbit imaging processing based on an instruction set, relates to the technical field of remote sensing satellites, and solves the technical problems of overuse of DMA resources and low data access efficiency caused by repeated configuration and execution of a large number of transmission commands and address increase commands in the prior art. The AXIS bus module is used for configuring a register related to transmission in the register-level instruction processing module; after the configuration of the register is completed, writing a data access operation instruction into the instruction memory read-write module through the AXIS bus module; the instruction set read-write analysis module reads the instruction data from the instruction memory read-write module and analyzes the instruction data to obtain a control instruction; controlling the state machine to jump through the control instruction, and outputting a control signal; a control signal enters the one-dimensional instruction analysis module after passing through the one-dimensional read-write instruction module; and the one-dimensional instruction analysis module is controlled by the control signal to perform read-write operation on the data.

This invention discloses a reconfigurable engine circuit for non-public-key cryptographic algorithms. The reconfigurable engine circuit includes: a reconfigurable arithmetic logic unit (RC_ALU) responsible for implementing the common basic operational logic of non-public-key algorithms; a shared buffer, composed of a register array, providing both short-vector and long-vector memory access modes for storing global parameters, hash messages to be processed, intermediate results, extended instructions, and S-Box data; and a reconfigurable instruction memory, using multiple SRAM blocks to store the reconfigurable instructions configuring the RC_ALU. The general hardware implementation circuit for non-public-key cryptographic algorithms provided by this invention can support the non-public-key cryptographic algorithms required by the aforementioned IoT security chips in a reconfigurable manner, ensuring that the cryptographic service performance meets the requirements of IoT information security systems.

The invention provides a data recovery method and device, electronic equipment and a storage medium, and relates to the technical field of terminals, and the method is applied to the electronic equipment comprising a processor and a memory. The method comprises the following steps: a processor sends an LBA remapping instruction to a memory to indicate that valid data corresponding to an original LBA segment is transferred to a target LBA segment in a mode of modifying a mapping relationship, and the valid data corresponding to the original LBA segment is stored in an original PBA segment; the memory then modifies the original LBA segment and original PBA segment mutual mapping to the target LBA segment and original PBA segment mutual mapping in response to the LBA remapping instruction. According to the method, the processor sends the LBA remapping instruction to the memory to indicate the memory to realize data recovery by changing the mapping relation between the LBA and the PBA, so that unnecessary data migration and command transmission in the data recovery process can be reduced, the system power consumption is reduced, and the recovery efficiency is improved.

Neural inference chips for computing neural activations are provided. In embodiments, a neural inference chip includes at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a location corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between locations in the instruction buffer. The instruction buffer provides the at least one instruction from an associated location in the instruction buffer to at least one element of the memory array when the memory of the at least one element of the plurality of elements of the memory array contains data associated with the at least one instruction. Each element of the memory array provides a block of data from its memory to its horizontal buffer in response to arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides the block of data to a horizontal buffer of another element of the memory array or to the at least one neural core.

The embodiment of the present disclosure provides a processor processing method and device, a storage medium and an electronic device, and relates to the technical field of computers. A peripheral interface of a processor is used for connecting peripherals. The method comprises the following steps: receiving an interrupt request and a priority request of the peripheral, adjusting the priority of the peripheral according to the priority request and a priority adjustment range corresponding to the peripheral; processing the interrupt request using a processor core according to the adjusted priority; and / or, in response to a determined key process, accessing an instruction memory space of the key process, determining a target instruction of the key process, detecting a memory space required by the target instruction, and adjusting the memory space of the key instruction according to the memory space required by the target instruction and an unused special space. In this way, the real-time adjustment of the priority and / or the real-time adjustment of the memory space of the key process improve the service quality performance of the processor and the balance of the overall performance of the processor.