59 results about "Instruction memory" patented technology

A system comprises pulse instruction memory and pulse generation circuitry, wherein the pulse generation circuitry is operable to retrieve a pulse instruction from the pulse instruction memory, and concurrently generate one or more analog pulses based on a first one or more fields present in the pulse instruction, and one or more digital pulses based on a second one or more fields present in the pulse instruction.

Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.

A system for autonomous compliance with legal regulations in smart contracts; the system includes: a regulatory data collection unit comprising a network interface controller physically connected to an external communications port, a hardware-based public key infrastructure circuit configured to validate digital certificates of regulatory servers, and a direct memory access controller configured to transfer authenticated regulatory update packets from the network interface controller to a volatile buffer memory without processor intervention; a Compliance Code Conversion Unit with a hardware lexicon scanner implemented as a finite state machine and embedded in reconfigurable FPGA logic blocks, a microcontroller executing a hardware-based lexical analysis pipeline stored in firmware registers, and a translation cache memory configured to temporarily store tokenized compliance rules before writing them to a non-volatile instruction memory; a policy evaluation and enforcement unit comprising a transaction verification processor connected to a secure enclave memory, a hardware comparator circuit configured to compare transaction parameters with compliance thresholds stored in the secure enclave memory, and a logic gate circuit configured to generate execution gate signals that selectively allow, block, or modify smart contract execution signals transmitted to a blockchain execution processor; and an audit logging unit with a cryptographic hashing circuit configured to generate block hashes of enforcement records, a timestamp oscillator configured to generate temporal signatures of compliance enforcement actions, and a Merkle tree generation circuit configured to create tamper-proof hierarchical hash structures, with the enforcement records being passed to a decentralized storage interface for anchoring in the chain or distributed ledger.

The invention discloses an intelligent heterogeneous radar hardware accelerator applied to rail transit, and belongs to the technical field of radar signal processing and integrated circuits. The accelerator is based on an SoC FPGA platform, a microprocessor soft core based on an RISC-V instruction set is constructed at an FPGA end, and an FFT calculation module and a CFAR calculation module are integrated to serve as hardware acceleration units. And the microprocessor soft core dynamically schedules each hardware acceleration unit by executing a program stored in the instruction memory, constructs a reconfigurable data path, and completes a radar signal processing flow. The method overcomes the defects of power consumption, communication bandwidth and flexibility of traditional DSP and FPGA schemes, and is particularly suitable for efficient and real-time detection and identification of roadbed structure damage in rail transit.

The invention belongs to the field of neural network hardware acceleration, and provides a Softmax instruction set extension method and system based on RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method comprises an instruction fetching stage, in the decoding stage, corresponding instruction functions are analyzed for Opcode, Funct7 and Funct3 of the Softmax instruction, and corresponding control signals are generated. In the execution stage, data to be subjected to Softmax operation is taken out from the data memory and transmitted into the Softmax calculation unit according to a control signal; executing Softmax calculation according to the following formula, and writing a Softmax calculation result back to the target register; the calculation process is divided into four sub-modules of maximum solution, index calculation, summation and normalization, and a hardware acceleration strategy is designed, so that the operation delay and the resource overhead are greatly reduced, the degree of parallelism, the precision and the energy efficiency ratio of calculation are effectively improved, and the method is suitable for a high-performance neural network reasoning acceleration scene.

This invention belongs to the field of computer technology and relates to an angle calculation system based on CORDIC instructions. The system includes an IFU (Instruction Fetch Unit) and an EXU (Execution Unit). During the instruction fetch phase, the IFU reads CORDIC instructions from the instruction memory according to the address of the PC. The EXU includes a decoding module, an arithmetic logic unit, a load-memory unit, and a write-back unit. This invention extends the CORDIC angle calculation instruction set based on the RISC-V architecture and designs a complete pipelined hardware structure, supporting trigonometric function operations. It has a complete CORDIC operation path hardware circuit structure, reusing the same operation path for different operation processes, improving hardware resource utilization. It overcomes the limitation of convergence of the calculation result range when performing angle calculation based on the CORDIC algorithm by pre-storing special angle results to reduce calculation time and optimize the circuit operating frequency.

The invention relates to a performance counting device and a chip, and the performance counting device comprises a performance counting module which is used for receiving at least one instruction memory address from a program counter associated with the performance counting module, and according to the at least one instruction memory address and a pre-configured instruction memory address interval, counting the at least one instruction memory address; obtaining a statistical value of a performance signal of at least one instruction memory address in the instruction memory address interval; the storage module is used for storing the statistical value of the performance signal of the at least one instruction memory address of the performance statistical module; the write-in control module is used for writing the statistical value, obtained by the performance statistical module, of the performance signal of the at least one instruction memory address into the storage module; and the configuration module is used for configuring an instruction memory address interval of the performance statistics module. According to the method and the device, the configuration flexibility of performance statistics can be improved, performance statistics of a plurality of specified program segments can be realized at the same time on the basis, and parallel processing of the performance statistics and accurate positioning of the program segments are further realized.

A printed circuit board (PCB) wiring automatic design method in a PCB wiring automatic design system, the system including at least one processor and at least one memory including an instruction, and the PCB wiring automatic design method performed in cooperation with the instruction, the memory, and the processor, includes: receiving PCB data including a net list and information on a plurality of terminals; updating a cost of a wiring exploration region so that a cost of at least some of the wiring exploration region is increased based on a preset constraint condition; exploring a shortest path for wiring the plurality of terminals according to the net list in a cost-updated wiring exploration region; and performing wiring of the plurality of terminals based on wiring probability according to the shortest path.

The application discloses a FLASH-based data access method, comprising the following steps: obtaining a next data storage starting address, executing a data storage instruction by a FLASH memory, and detecting whether there is a data reading instruction; detecting the data reading instruction, stopping the data storage instruction execution by the FLASH memory and executing the data reading instruction; and if the data reading instruction is not detected, continuing the data storage instruction execution by the FLASH memory. The FLASH-based data access method, the address cyclic storage mode in the address space, compared with erasing the FLASH each time the address is updated, reduces the number of times of FLASH erasing in the address space, increases the service life of the FLASH, organizes the storage and reading data, and maximizes the use of the FLASH storage space to store more data.

The invention relates to histogram operation. A digital data processor (100) includes: an instruction memory (121) storing instructions each specifying a data processing operation and at least one data operation digit segment; an instruction decoder (113) coupled to the instruction memory for sequentially invoking instructions from the instruction memory and determining the data processing operation and the at least one data operand; and at least one arithmetic unit (110) coupled to the data register file (123) and to an instruction decoder to perform a data processing operation on at least one operand corresponding to an instruction decoded by the instruction decoder and to store a result of the data processing operation. The arithmetic unit is configured to incrementing a histogram value in response to a histogram instruction by incrementing a bin entry at a specified location in at least one histogram of a specified number.

To provide an information processing device that can reduce development man-hours and lower vulnerabilities. [Solution] The memory 10 of the information processing device 1 stores a secure function module 111a that contains instructions to be executed by the processor 20 in the performance of a function and is restricted from external interference. The memory 10 also stores a processing function module 131 that contains instructions common to the secure function module 111a, has less restrictive external interference than the secure function module 111a, and is processed into a disabled state in which the processor 20 cannot execute instructions. The memory 10 also stores a release module 112 that has more restricted external interference than the processing function module 131 and can release the disabled state in the processing function module 131. The memory 10 also stores a security request determination flag 115 that defines the security level required in the performance of a function.

To provide a memory control circuit of a micro computer that can enhance a processing speed of the micro computer in comparison with conventional arts.SOLUTION: A micro computer memory control circuit comprises: a memory read control circuit that stores an address where a processor reads a command from a memory, and a next address in a memory address register, stores a command of the address and a command of a next address in a command memory, and stores the next address and a command of the next address in a first command cache; and a cache controller that, when the processor reads a next command from the memory, if the address stored in the memory address register and the address stored in the first command cache are mismatched, stores the address stored in the memory address register, the command of the address and a frequency of the mismatch in a second command cache.SELECTED DRAWING: Figure 1

The application discloses an FPGA-based target detection neural network accelerator and a target detection system, the accelerator is arranged on an FPGA and comprises a control module, an input buffer module, a parameter buffer module, a systolic array module, a post-processing module and a pooling module; the control module comprises an instruction memory and a controller; the instruction memory is used for storing an instruction set of a neural network; the controller is used for generating control instructions according to the instruction set and controlling the operation of each module; the input buffer module is used for storing input feature data blocks of the target detection neural network; the parameter buffer module is used for storing bias data and weight data of the target detection neural network; the systolic array module is used for performing convolution operation; the post-processing module is used for processing the convolution calculation result; the pooling module is used for performing maximum pooling operation on data; and the output buffer module is used for reading and writing cache of data. The application improves the inference efficiency of the accelerator by configuring parameters of the target detection neural network, and realizes the high-performance and high-flexibility target detection neural network accelerator.

The invention discloses a variable register block structure supporting different scene applications of an MCU chip, and belongs to the technical field of chip design, the variable register block structure is applied to the MCU chip, the MCU chip comprises a core, an instruction memory, a data memory and a variable register block, the core is used as a main device, and the instruction memory is used as an auxiliary device. The register block module, the instruction memory, the data memory and the variable register block are used as slave devices; wherein the core is respectively connected with the instruction memory, the data memory and the variable register group through a bus; and the variable register group is used as slave equipment and accesses registers in the variable register group through the core. The variable register block disclosed by the invention can be used as different functional modules in different working scenes; by using the variable register block structure, more flexible and changeable applications can be provided, and meanwhile, the relatively fixed area and power consumption can be reduced; and a certain protection effect is also achieved for the exposure risk of starting the ROM.

A memory device includes a memory bank including one or more bank arrays, a PIM circuit configured to perform an operation logic processing operation, and an instruction memory including a first instruction queue segment to an mth instruction queue segment configured in a circular instruction queue to store instructions provided by a host, wherein the instructions stored in the first instruction queue segment to the mth instruction queue segment are executed in response to an operation request from the host, and each new instruction provided by the host is updated on the fully executed instructions in the circular instruction queue.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to record an entry into a virtual integrity register. The entry is based on a measurement of a module. The module is a part of a confidential computing environment. The machine-readable instructions further include instructions to load the module into a memory. The memory is accessible by the confidential computing environment. The machine-readable instructions further include instructions to record an entry of a log. The log comprises a load history. The entry comprises information about the loading of the module. The machine-readable instructions further include instructions to record an entry into an integrity measurement register. The entry being based on the recorded virtual integrity register entry.

Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.

Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.

A memory apparatus includes an instruction memory and a plurality of micro control units. The instruction memory outputs a plurality of instruction codes at a predetermined time interval in accordance with a plurality of address signals and a plurality of divided clock signals. The plurality of micro control units are coupled to each of a plurality of memory regions, provide each of the plurality of address signals to the instruction memory in accordance with each of the plurality of divided clock signals, and perform operations in accordance with corresponding instruction codes among the plurality of instruction codes.

An apparatus for the anonymization of user data is disclosed. The apparatus includes at least processor and a memory communicatively connected to the processor. The memory contains instructions configuring the processor to receive a plurality of user data. The memory contains instructions configuring the processor to identify a plurality of patient identifiers within the plurality of user data. The memory contains instructions configuring the processor to generate contextual data associated with each patient identifier of the plurality of patient identifier. The memory contains instructions configuring the processor to identify one or more false positive patient identifiers within the plurality of patient identifiers as a function of the contextual data.

A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux disconnects an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load / store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

An electronic device and a method for correcting the contrast ratio of an image, and a storage medium are provided. The electronic device comprises: at least one processor including a processing circuit; and a memory for storing instructions to be executed by the at least one processor. The instructions stored in the memory are configured to instruct the electronic device to: obtain, from a luminance histogram of the image, a first probability distribution function of luminance that includes a first plurality of Gaussian functions; determine a threshold value from the first probability distribution function of luminance; determine a scale factor of luminance when the threshold value is less than or equal to a preset first value; perform a first luminance correction operation of correcting luminance on the basis of the scale factor; correct the luminance of respective blocks obtained by dividing the image by a preset size; correct the luminance of the entire area of the image; determine, on the basis of the average luminance of the image, a gamma parameter to which a threshold value is applied; and, on the basis of the gamma parameter, generate a corrected image by correcting luminance.

The application discloses a program dynamic updating method and a digital signal processing system. The program dynamic updating method comprises the following steps: executing a pause instruction belonging to an instruction set in a program running on a DSP core; in an execution stage of the instruction, the DSP core enters an idle state specified by an immediate number in the instruction, and stops accessing all memories, at this time, an external host controls to modify the code in an instruction memory; after the idle state ends, the DSP core resumes running according to a previously saved pipeline state. Through the integration of a special pause instruction and a matching hardware cooperative control mechanism, the application fundamentally solves the bus access conflict, the pipeline timing destruction and the multi-cycle instruction adaptation problem during the program dynamic updating, and realizes the safe, real-time and reliable online updating.

This provides a processor and processor architecture adapted to parallelize multiple instructions moving between two poles (strict allocation used in SIMD / MIMD architectures) at a user-defined granularity, by making the wall between instruction slots and PEs fluid. [Solution] The processor includes an instruction memory, a decoder that converts instructions into opcodes and enable signals, a controller that provides instructions to the decoder, and a plurality of processing elements that operate according to the operation codes provided to the input of a target processing element during a time slot to apply mathematical operations to input data elements and generate output data elements. The enable signals control the assignment of opcodes to the processing elements. The interconnection circuit is adapted to provide one of the opcodes to any of the processing elements in each time slot and operates according to the enable signals.

The embodiment of the invention provides a processing method and device of a processor, a storage medium and electronic equipment, and relates to the technical field of computers, a peripheral interface of the processor is used for being connected with a peripheral, and the method comprises the steps of receiving an interrupt request and a priority request of the peripheral, and adjusting the priority of the peripheral according to the priority request and a priority adjustment range corresponding to the peripheral; adjusting the priority of the peripherals; processing the interrupt request by using a processor core according to the adjusted priority; and / or, responding to the determined key process, accessing an instruction memory space of the key process, and determining a target instruction of the key process; detecting a memory space required by the target instruction; and adjusting the memory space of the key instruction according to the memory space required by the target instruction and the unused special space. In this way, the service quality performance of the processor and the balance of the overall performance of the processor are improved through real-time adjustment of the priority and / or real-time adjustment of the memory space of the key process.

The application discloses an adaptive NVM reading method and a device thereof. The reading device is a medium interface controller, which comprises a medium interface, a local cache, a micro instruction memory, an error correction code decoder and a cache management unit. The medium interface is coupled with the micro instruction memory, the local cache and the cache management unit. The cache management unit is further coupled with the local cache, and the cache management unit provides a reading pause signal to the medium interface according to the available space size in the local cache. The cache management unit of the application manages the operation related to the use of the local cache in a manner independent of the micro instruction, thereby avoiding introducing excessive complexity due to the expansion of the micro instruction.

The present disclosure generally relates to offloading the orchestration and control of a communication collective to a specialized collective offload engine. The systems, methods, and specialized computing hardware described herein avoid the latencies and other inefficiencies introduced when software applications control the execution of a communication collective. For example, the described systems, methods, and specialized computing hardware generate a binary representation of one or more direct acyclic graphs of node operations for a communication collective, and load this representation into the instruction memories of specialized collective offload engines residing on network endpoints connected to one or more network switches. During execution of the collective, the collective offload engines initiate node operations based on whether corresponding dependencies are met. By offloading these tasks to the collective offload engines, no additional latencies are introduced and other computing resources are kept free for use by other applications.

The invention provides a processor, a board card and electronic equipment, the processor comprises an instruction memory, an instruction decompression module, an instruction execution module and a data memory, the instruction memory is used for storing a compression instruction; the instruction decompression module is used for decompressing the compression instruction and generating a corresponding instruction to be processed; the instruction execution module is used for executing the instruction to be processed; the data memory is used for storing to-be-processed data and corresponding processing results; wherein the compression instruction comprises instruction parameters, and the instruction parameters comprise an operation code, an input data base address, a loop parameter and a step length parameter. According to the processor provided by the embodiment of the invention, the execution efficiency of the processor is improved.

A packet-processing method includes looking up a first match-action table on a network interface card (NIC) for a received packet; in response to finding a matching entry indicating an action, queuing the received packet in a first queue and storing the action data in an instruction memory; and responsive to not finding a matching entry, queuing the received packet in the first queue and a second queue. The method includes selecting a first packet from the first queue for processing, which comprises performing a corresponding action stored in the instruction memory; selecting a second packet from the second queue for processing, which comprises forwarding a portion of the second packet to a processor, which looks up a second match-action table; and receiving, from the processor, a lookup result, thereby allowing a third packet in the first queue corresponding to the second packet to be processed based on the lookup result.