6 results about "Indirect branch" patented technology

Aspects of the disclosure are directed to reduction of data transfer overhead. In accordance with one aspect, increment a function call counter for an executed function call; decrement the function call counter for an executed return from function call; infer the indirect branch address based on a function call counter value and when a cumulative count of received executed atoms indicates a return from function call has been executed; oversaturate the function call counter at a maximum counter value if the function call counter contains the maximum counter value and a subsequent function call is executed; and undersaturate the function call counter at a minimum counter value if the function call counter contains the minimum counter value and a subsequent return from function call is executed.

The present invention discloses an indirect branch predictor based on global history classification and a prediction method, belonging to the field of branch predictor design for processors. The indirect branch predictor based on global history classification includes: a single target address prediction module, a multi-target address prediction module, a target address arbitration module, and a multiplexing module; the present invention can respectively utilize the prediction advantages of the instruction path history and the direction history, select more reasonable historical information for prediction according to the confidence level, thereby further improving the prediction accuracy of the indirect branch predictor; moreover, the predictor adopted in the present invention can be implemented by using different indirect branch predictors according to actual design requirements, so as to meet the performance and area requirements of various processors. Therefore, the present invention can reasonably utilize hardware resources and has better applicability in the design of different types of processors.

A data processing apparatus (110) for executing an application with runtime integrity proof is provided. The data processing apparatus (110) comprises processing circuitry (111) for executing a modified version (143) of an application machine code (141) defining the application. The modified version (143) of the application machine code (141) includes one or more direct or indirect branch instructions, and one or more machine code instructions, the one or more machine code instructions being one or more target instructions for the one or more direct or indirect branch instructions. During the execution of the modified version (143) of the application machine code (141), the processing circuitry (111) is further configured to update a first register value in a first register and a second register value in a second register, and to update the modified version (143) of the application machine code (141) based on the first register value and the second register value. And / or triggering an exception if the one or more direct or indirect branch instructions are for instructions of the modified version (143) of the application machine code (141) instead of the one or more target instructions.

Aspects of the disclosure are directed to reduction of data transfer overhead. In accordance with one aspect, increment a function call counter for an executed function call; decrement the function call counter for an executed return from function call; infer the indirect branch address based on a function call counter value and when a cumulative count of received executed atoms indicates a return from function call has been executed; oversaturate the function call counter at a maximum counter value if the function call counter contains the maximum counter value and a subsequent function call is executed; and undersaturate the function call counter at a minimum counter value if the function call counter contains the minimum counter value and a subsequent return from function call is executed.

A data processing apparatus includes a processing circuitry configured to execute a modified version of an application machine code defining the application. The modified version of the application machine code comprises one or more direct or indirect branch instructions and one or more machine code instructions being one or more target instructions for the one or more direct or indirect branch instructions. During the execution of the modified version of the application machine code, the processing circuitry is further configured to update a first register value in a first register and a second register value in a second register and to trigger an exception, based on the first register value and the second register value and / or when the one or more direct or indirect branch instructions target an instruction of the modified version of the application machine code.

Aspects of the disclosure are directed to reduction of data transfer overhead. In accordance with one aspect, increment a function call counter for an executed function call; decrement the function call counter for an executed return from function call; infer the indirect branch address based on a function call counter value and when a cumulative count of received executed atoms indicates a return from function call has been executed; oversaturate the function call counter at a maximum counter value if the function call counter contains the maximum counter value and a subsequent function call is executed; and undersaturate the function call counter at a minimum counter value if the function call counter contains the minimum counter value and a subsequent return from function call is executed.