127 results about "Compile time" patented technology

The invention discloses a UVM verification platform and a verification test execution method, and relates to the technical field of integrated circuits, the verification platform comprises a file management module used for sending a test case file to a script processing module; the script processing module is used for acquiring a test case name and a hardware parameter according to the test case file, and sending the test case name and the hardware parameter to the command generation module; the command generation module is used for generating a target simulation command according to the test case name and the hardware parameters and sending the target simulation command to the compiling library; and the compiling library is used for verifying and testing the design unit according to the basic use case information and the target simulation command. According to the technical scheme, on the premise that the number of the test cases is not changed, the scale of the compiling library of the UVM verification platform is reduced, the compiling time consumption and the dynamic simulation time consumption of the compiling library are reduced, and the verification test execution efficiency of the UVM verification platform is improved.

Apparatuses, systems, and techniques to generate a memory allocation plan for a set of tensors. In at least one embodiment, tensor data corresponding to the set of tensors is stored into memory locations at run time based, at least in part, on the memory allocation plan generated at a compile time.

A novel garbled circuit (GC) accelerator and compiler, named HAAC, mitigates performance overheads and makes privacy-preserving computation more practical. HAAC is a hardware-software co-design. GCs are exemplars of co-design as programs are completely known at compile time because all dependence, memory accesses, and control flow are fixed. The compiler can leverage its program understanding to realize hardware's performance potential by generating effective instruction schedules, data layouts, and managing off-chip events. Arbitrary GC programs may be expressed as streams, which simplifies hardware, and the development of an adaptive, on-chip scratchpad that tracks program execution to capture data reuse despite the lack of a regular access pattern or requiring tagging.

A self-optimizing and self-programming computing system (SOSPCS) design framework that achieves both programmability and flexibility and exploits computing heterogeneity [e.g., CPUs, GPUs, and hardware accelerators (HWAs)] is provided. First, at compile time, a task pool consisting of hybrid tasks with different processing element (PE) affinities according to target applications is formed. Tasks preferred to be executed on GPUs or accelerators are detected from target applications by neural networks. Tasks suitable to run on CPUs are formed by community detection to minimize data movement overhead. Next, a distributed reinforcement learning-based approach is used at runtime to allow agents to map the tasks onto the network-on-chip-based heterogeneous PEs by learning an optimal policy based on Q values in the environment.

The invention relates to the technical field of data acquisition, in particular to an AOP-based user behavior data acquisition method. The method comprises the following steps: firstly, identifying user behavior related code features by statically analyzing Java source codes of an application program, and constructing a feature template library; during a compiling period, according to a template library identification target method, embedding a point burying instruction by utilizing a byte code enhancement technology, and constructing a monitoring section framework; and during running, dynamically adjusting an execution strategy according to the running state of the application program by virtue of a dynamic rule engine. Meanwhile, an annular buffer area is adopted to asynchronously process user behavior data streams, cache data are managed in a sub-generation mode, and asynchronous processing is triggered when a threshold value is exceeded. The method also constructs an adaptive thread pool model based on a hierarchical thread pool architecture, distributes tasks according to data value weights, monitors the task backlog rate of a high-priority sub-pool, adjusts the sampling frequency or acquisition dimension when the task backlog rate exceeds a threshold value, forms adaptive closed-loop control, and effectively acquires and processes user behavior data.

The invention relates to a method and device for determining program memory allocation based on a large model, equipment and a medium, and the method comprises the steps: obtaining data for determining program memory allocation in a compiling period, and constructing a memory allocation data set which comprises a code slice set and a header file for recording memory allocation; adjusting a large language model by adopting the memory allocation data set to obtain an adjusted target large language model; and obtaining a target application program code, reasoning the target application program code by adopting the target large language model, and generating a target header file for recording memory allocation, which is used for determining the memory allocation of a program in a compilation period. According to the method, the memory allocation condition can be automatically confirmed in the compiling period, the response speed is increased, and the method is suitable for a programming scene with high requirements for real-time performance and safety key performance.

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for unrolling an infinite loop during ray query traversal. A processor obtains, during a compile time, a number of loops associated with a BVH traversal based on a number of ray triangle intersections and a number of ray box intersections and / or a set of features associated with the BVH traversal and code generation associated with a shader. The processor determines, during the compile time, a loop unroll factor based on at least one of the obtained number of loops or the obtained set of features. The processor adjusts, during the compile time, a number of iterations of a loop associated with the BVH traversal based on the loop unroll factor. The processor outputs an indication of the adjusted number of iterations.

The invention provides a compiler performance optimization method. The compiler performance optimization method comprises the steps that a source code program is compiled into an initial intermediate code # imgabs0 # based on the lowest optimization level; executing each optimization in the complete optimization list set on the initial intermediate code # imgabs1 # in sequence to obtain an intermediate code of an execution result; calculating intermediate representation complexity of the intermediate code; according to the intermediate representation complexity of each intermediate code, an optimization with a forward optimization effect is screened out; and compiling the source program code into a target program based on forward optimization. The invention provides a method for judging optimization effectiveness on an intermediate code level according to intermediate representation complexity. The method is used for avoiding invalid or negative optimization in the compiling process. The method does not depend on a specific hardware architecture, has good universality and is suitable for various target platforms; and the optimization effect is dynamically evaluated on the intermediate language level, so that the compiling time is greatly shortened, and the performance of the target program is better.

Systems and methods comprising at least one node comprising an application container; a container image associated with the application container; a static analyzer module deployed to analyze the container image, with instructions configured to autonomously parse, code of an application, during compile time of the application, wherein the application is to be deployed in the application container; determine, based on the parsing, for at least one section of the code, at least one module necessary for execution of the at least one section; annotate, the at least one section of the code, based on the determined at least one module; and inject, at least one wrapper around the at least one section of the code, wherein the wrapper adds at least one restriction to an execution of the at least one section at runtime, wherein the restrictions are based on at least one condition.

The invention discloses a parallel compiler compiling method and system supporting multiple operating systems, which can fully utilize the advantages of a multi-processor or multi-core system and process a plurality of compiling tasks at the same time by acquiring a parallel compiling file, thereby greatly shortening the compiling time. The parallel compiling can significantly improve the compiling speed of large files, especially for complex software projects, the development cycle can be accelerated, and the development efficiency can be improved. A main function node is transformed, AST tree nodes corresponding to operating system interfaces are generated in combination with parallel compiling parameters, and then the AST tree nodes are inserted into an AST tree for node transformation operation, so that compiled files can run on a plurality of operating systems. According to the method, the barrier between different operating systems is broken, a developer does not need to independently write and maintain codes of different versions for each operating system, and the development and maintenance cost is reduced. The method allows adjustment according to different parallel compilation parameters to adapt to various compilation requirements.

A system receives ETL specification for processing stream data, including a transform operation represented using a database query specification. The system generates a dataflow graph of a sequence of database queries by decomposing the database query into a first database query that generates an intermediate results table, and a second database query that receives as input the intermediate results table and outputs data used for performing the transform operation. The system executes the sequence of database queries for performing the transform operation on stream data received from the source. When receiving an incremental data set, the system determines an output change set based on the received incremental data set by traversing an execution plan and processing each operator in the execution plan, and computing a change set of a particular operator from the change sets output by the one or more other operators based on the incremental data set.

In various examples, static single assignment-based control flow graph traversal analysis for uninitialized variable detection system and methods are disclosed. A pre-compiler stage of a compiler system, may reconstruct source code into an SSA form IR and detect and identify uninitialized variables based on applying a variable analysis pass that traverses a CFG corresponding to the SSA form IR. A variable analysis pass may traverse through the CFG to build a defined variable map and a Phi variable map. The maps may be used to map undefined variables to basic blocks of the CFG where the undefined variables occur. The variable analysis pass may pass uninitialized variable data to a compiler error handling process. The compiler error handling process may produce an error report that traces the basic block with undefined variables to lines of the source code to assist in efficiently debugging the source code.

The embodiment of the present application provides a kind of compiling method and electronic equipment, it is related to computer technical field, to solve the problem of low compiling efficiency when the source code is compiled currently.The method, at the time of compiling, can utilize the binary file corresponding to the API information of the binary file that is precompiled with the target function module to be compiled, and the source code of the target function module is compiled, to obtain the machine executable binary file of the target function module.Wherein, binary file is precompiled, not generated at the time of compiling.Furthermore, the binary file that is compiled corresponds to API information, according to the binary file corresponding to the second function module and the API information of the binary file, the compilation of the first source code can be completed, without further determining the function module that the second function module depends on, so that the process of compiling is also simplified, and the compiling time can be reduced, and the compiling efficiency is improved.

The invention discloses a control flow integrity protection method and a related device, and the method can judge whether a function starts to be executed from a starting position of the function or not before an indirect jump instruction of the function is executed, if yes, it is indicated that the possibility of JOP attack in the execution process of the function is small, the function can continue to be executed, and if not, it is indicated that JOP attack exists in the execution process of the function. If yes, JOP attacks possibly exist in the execution process of the function, and execution of the function can be stopped. Therefore, the method can monitor whether the control flow of the function in the execution process is abnormal or not, and further reflects whether the JOP attack occurs or not in the execution process of the function. Moreover, the method does not need to analyze the global call relationship of the function, shortens the compiling time, does not need to generate a CFI check table, reduces the occupation of the memory space, omits the step of table look-up verification, can judge whether the current program control flow is tampered or not only by judging one mark, and improves the verification speed.

The application provides a one-to-many service discovery and dynamic loading method and system in a Hongmeng application, comprising: AST analysis of ArkTS source code by a TypeScript compiler API in a compilation period, identification of a class marked by a @HMModularService decorator, extraction of a service path, a class name, a module name, an instantiation mode and a unique identifier as metadata, generation of a module-level mapping table and merging into a global mapping table, and establishment of a one-to-many mapping relationship from the service path to an implementation item array; loading of the global mapping table into a memory Map structure in a running period, receiving of a service query request from a calling party, searching for a corresponding implementation item according to the service path and supporting of filtering according to an identifier; dynamic loading of a target HSP module by calling a napi_load_module_with_info native interface, obtaining of a constructor from an export object and creation of an instance, and caching of a singleton mode implementation item.

The invention relates to the technical field of data serialization, and particularly provides a structured storage fixed-length serialization method and system based on a Rust process macro, and the method comprises the following steps: analyzing declarative attributes in a structured data definition through the Rust process macro, and obtaining a preset fixed length of a variable-length field; based on the preset fixed length, automatically configuring the memory capacity for the variable-length field to avoid dynamic capacity expansion; converting the structured data into a byte sequence by adopting a fixed-length serialization algorithm, so that the total length of the byte sequence is fixed and is irrelevant to a field actual value; when the actual data length of the variable-length field exceeds a preset fixed length, intelligent truncation is performed on the actual data, and the data integrity is maintained; performing type verification on the serialization process in a compiling period by utilizing a type checking mechanism of a Rust compiler; the execution logic of the previous steps is generated in the compiling period through the Rust process macro, so that no redundant operation exists in the running process; according to the scheme, the fixed-length serialization processing of the structured data is comprehensively optimized.

The invention discloses a method, a system and equipment for calling a generic method by a Rust language. Wherein. The method comprises an expansion step during compiling and a calling step during running, during compiling, a package function for expanding trait and type erasure / recovery is automatically generated through process macro analysis trait and specific implementation, and mapping of the type and the package function is registered to a global table. During operation, when the generic method is called for the trait object, the registry is inquired according to the actual type, the corresponding packaging function is found and executed, and therefore the original generic method is indirectly called for implementation. The core is to realize dynamic distribution of generic methods through compilation period code generation and runtime search. According to the method, the core limitation that the trait object in the Rust language does not support the generic method is successfully solved, and the dynamic generic method calling with safe type and zero running overhead is realized.

The invention relates to the technical field of computer compiling, and discloses a method and a device for simultaneously compiling multiple architectures, computer equipment and a storage medium. According to the method for simultaneously compiling the multiple architectures, the code files input by the user are processed through the user-defined linker, the multiple code files are analyzed, and therefore analysis operation in the compiling process in all the architectures can be advanced, and a unified intermediate file is generated. And continuing to compile the generated unified intermediate file in each architecture, and finally obtaining an executable file or a library file corresponding to each architecture. According to the embodiment of the invention, the analysis operation is advanced, and the unified intermediate file is generated, so that the analysis operation does not need to be executed for multiple times when compiling is continued under each framework, and the effects of shortening the compiling time and saving computing resources can be achieved.

The application provides a script generation method and device, equipment, storage medium and program product, wherein the script generation method is applied to a vehicle, comprising: during pre-compilation, obtaining a standardization document of the vehicle; the standardization document comprises signal data of controller area network (CAN) signals transmitted between an application layer and a framework layer in the vehicle; based on the signal data of each CAN signal in the standardization document, a communication method of each CAN signal is generated; the communication method is used for transmitting the CAN signal between the application layer and the framework layer; according to the communication method of each CAN signal, a script file is generated; the script file is used to be loaded during compilation so that the communication method in the script file is called. Through the above method, the efficiency and accuracy of obtaining the CAN signal of the vehicle are improved.

The invention provides a program variable value forcing method and device during PLC program running, and the method comprises the steps: obtaining variable definition code information through an interactive interface; the compiler compiles the variable definition code information, generates a forcing function program for realizing variable value forcing and downloads the forcing function program to the PLC, and the forcing function program sets a target pointer corresponding to a target variable to point to a specified memory address from pointing to an original target memory address; a variable value forced limiting command is obtained through the interactive interface, and the variable value forced limiting command is used for requesting to forcibly limit a variable value of a target variable in a target PLC program running by the PLC to be a target value; and the PLC executes a forcing function program to endow a target value to a memory space pointed by the target memory address, and forcibly limits the variable value of the target variable to be the target value. The problem that compilation time and program running time are prolonged due to the fact that a target file generated through compilation is larger due to variable value forced limitation is solved.

This disclosure describes a system and method for compiling and executing machine learning inferences in an array of multi-core computing devices. Each multi-core computing device can be an application specific integrated circuit (ASIC) or group of ASICS. In many applications, the array of computing devices changes from inference to inference, and can be adjusted based on the requirements of the inference. Additionally, each ASIC can have multiple processing cores, and multiple types of processing cores. Therefore, performing optimizations and scheduling at compile time, can dramatically increase the efficiency of the array in executing the inference. In some implementations, it is possible to select an amount of time or effort to be spent optimizing during compiling, giving the user flexibility in determining whether to spend time during compilation or during execution.

A method and system provide the ability to process source computer instructions. The source computer instructions are obtained and include input statements that consist of two functions that consume one or more arguments. A legal configuration of the functions and arguments is determined. A first function can be evaluated to yield a non-variable value, and a second function cannot be evaluated to yield a non-variable value. The input statements are compiled into executable code using the determined legal configuration such that during compilation, the first function is executed, and instructions are emitted to execute the second function at an indeterminate time.

Systems and methods for validating operation of a software sequence may include: monitoring signals on a bus of a processor, comparing the contents of the signals on the bus to pre-stored information from compile time. If the comparing generates a match, that may indicate that the software sequence is operating as intended. However, if the comparing generates a mismatch, that may indicate that the software sequence is not operating as intended and may, in fact, indicate a malicious use. Further actions can be taken in response to a mismatch, including resetting a processor, issuing an interrupt, and the like.

The present invention provides an off-line software-in-the-loop simulation development system and an off-line software-in-the-loop simulation method. A general firmware architecture is compiled to generate a chip control program. The general firmware architecture includes an application layer and a hardware abstraction layer. The application layer has a setup header file and a product program. Processing programs required by peripheral modules are added to the hardware abstraction layer at compile time. The chip control program is provided to a controller chip or circuit simulation software to control product-related circuits by controlling peripheral modules.

The invention discloses an application program maintenance method and device, a storage medium and electronic equipment. The method comprises the following steps: loading a class marked with a first annotation; the first annotation is used for triggering a corresponding annotation processor to automatically obtain compiling period information of the application program during the compiling period of the application program; executing the static code block in the class marked with the first annotation, and loading the information during compiling into a Java system variable; the static code block is a static code block after abstract syntax tree enhancement is carried out by using the compiling period information during the compiling period of the application program; collecting and exposing the compiling period information, and maintaining the application program based on the compiling period information. By adopting the scheme, the accuracy of application program maintenance can be improved.

The invention relates to a compiling period parameter classification method and device, a target code generation method and device and computer equipment. The method comprises the steps of determining type information of a formal parameter list of a to-be-extracted function and a return value type in a compiling period; based on the function behavior of the to-be-extracted function, various types of information and return value types of the formal parameter list are processed in a recursive mode, and an input parameter type and an output parameter type are obtained; and classifying the formal parameters belonging to the input parameter type into an input parameter tuple list, and classifying the formal parameters belonging to the output parameter type into an output parameter tuple list. By adopting the method, automatic classification of parameter types can be realized under the condition of not depending on an IDL (Independent Disk Language) file.

A compiler comprises a low-level memory management (LLMM) module that locates computed entities within source code. Each computed entity is analyzed, and resource costs associated with each computed entity are calculated. A memory model is selected for each computed entity, based on memory use, computational complexity, and other factors. User-defined memory model assignment is supported. The compiler auto-generates instructions for allocating memory for, computing, and deallocating memory for each computed entity. The instructions generated for each computed entity will vary based on its assigned memory model. A variety of embodiments are disclosed for auto-generating these instructions during compile time at differing phases of compilation. In all of those, with the resultant executable code, memory is allocated and freed at runtime automatically and accurately without the intervention in source code by a programmer.

The invention relates to a software package compiling method, system and device and a medium, and the method comprises the steps: reading dependency information of each software package in a software development project, and constructing a dependency list of each software package; based on the dependency list, determining software packages meeting compiling conditions from the software packages to obtain a to-be-compiled software package list, and executing parallel compiling of the software packages in the to-be-compiled software package list; deleting and updating compiled software packages in the to-be-compiled software package list from a dependency list of uncompiled software packages; and on the basis of the deleted and updated dependency list, re-obtaining the to-be-compiled software package list, carrying out parallel compiling, and circularly deleting, updating and carrying out parallel compiling until all the software packages of the software development project are compiled. By means of the method and device, parallel compiling directly based on the software package dependency information is achieved, a large amount of compiling time can be saved, and the problem of how to improve the software package compiling efficiency in the application software development process is solved.

The invention discloses a vector chain type calculation method and system based on a C + + expression template. The system comprises a type information extraction module, a vector packaging and interface module, an operation implementation module, an expression node module and an operator reloading module. Firstly, a C + + template mechanism is applied, the whole expression is constructed into an expression type tree during compiling, intermediate temporary variables are completely eliminated, redundant memory allocation and data copying are effectively avoided, and the calculation efficiency during operation is remarkably improved. And secondly, by introducing an inline expansion and loop fusion technology, deeper and more efficient performance optimization can be realized in a compiling stage. Thirdly, an operator reloading mechanism is adopted, unified modeling is conducted on three types of operation, natural expression can be achieved, the expression ability of the system is remarkably improved, and the application range of the system is remarkably widened. Finally, an SIMD instruction set is introduced through an expression template and a type feature extraction mechanism, and single-instruction multi-data-level parallel processing is achieved.

The invention provides a compiling method, a compiling device and computer equipment. Comprising the steps of generating a byte code file and first type information according to a source code; determining second type information according to the byte code file; combining the first type of information and the second type of information in a compiling period to obtain a first composite structure type; at least two data structures are determined according to the first composite structure type, and when the first composite structure type is matched with one or more of the at least two data structures, the phi node is constructed by compiling the first composite structure and one or more of the at least two data structures. According to the compiling method, the compiling device and the computer equipment provided by the invention, the composite structure type is obtained in a mode of mutual complementation of the labeling type information and the sampling type information, and multiple paths are established for constructing the phi node, so that the probability of de-optimization is reduced.