71 results about "Compile time" patented technology

A self-optimizing and self-programming computing system (SOSPCS) design framework that achieves both programmability and flexibility and exploits computing heterogeneity [e.g., CPUs, GPUs, and hardware accelerators (HWAs)] is provided. First, at compile time, a task pool consisting of hybrid tasks with different processing element (PE) affinities according to target applications is formed. Tasks preferred to be executed on GPUs or accelerators are detected from target applications by neural networks. Tasks suitable to run on CPUs are formed by community detection to minimize data movement overhead. Next, a distributed reinforcement learning-based approach is used at runtime to allow agents to map the tasks onto the network-on-chip-based heterogeneous PEs by learning an optimal policy based on Q values in the environment.

The invention relates to the technical field of data acquisition, in particular to an AOP-based user behavior data acquisition method. The method comprises the following steps: firstly, identifying user behavior related code features by statically analyzing Java source codes of an application program, and constructing a feature template library; during a compiling period, according to a template library identification target method, embedding a point burying instruction by utilizing a byte code enhancement technology, and constructing a monitoring section framework; and during running, dynamically adjusting an execution strategy according to the running state of the application program by virtue of a dynamic rule engine. Meanwhile, an annular buffer area is adopted to asynchronously process user behavior data streams, cache data are managed in a sub-generation mode, and asynchronous processing is triggered when a threshold value is exceeded. The method also constructs an adaptive thread pool model based on a hierarchical thread pool architecture, distributes tasks according to data value weights, monitors the task backlog rate of a high-priority sub-pool, adjusts the sampling frequency or acquisition dimension when the task backlog rate exceeds a threshold value, forms adaptive closed-loop control, and effectively acquires and processes user behavior data.

In various examples, static single assignment-based control flow graph traversal analysis for uninitialized variable detection system and methods are disclosed. A pre-compiler stage of a compiler system, may reconstruct source code into an SSA form IR and detect and identify uninitialized variables based on applying a variable analysis pass that traverses a CFG corresponding to the SSA form IR. A variable analysis pass may traverse through the CFG to build a defined variable map and a Phi variable map. The maps may be used to map undefined variables to basic blocks of the CFG where the undefined variables occur. The variable analysis pass may pass uninitialized variable data to a compiler error handling process. The compiler error handling process may produce an error report that traces the basic block with undefined variables to lines of the source code to assist in efficiently debugging the source code.

The embodiment of the present application provides a kind of compiling method and electronic equipment, it is related to computer technical field, to solve the problem of low compiling efficiency when the source code is compiled currently.The method, at the time of compiling, can utilize the binary file corresponding to the API information of the binary file that is precompiled with the target function module to be compiled, and the source code of the target function module is compiled, to obtain the machine executable binary file of the target function module.Wherein, binary file is precompiled, not generated at the time of compiling.Furthermore, the binary file that is compiled corresponds to API information, according to the binary file corresponding to the second function module and the API information of the binary file, the compilation of the first source code can be completed, without further determining the function module that the second function module depends on, so that the process of compiling is also simplified, and the compiling time can be reduced, and the compiling efficiency is improved.

The application provides a one-to-many service discovery and dynamic loading method and system in a Hongmeng application, comprising: AST analysis of ArkTS source code by a TypeScript compiler API in a compilation period, identification of a class marked by a @HMModularService decorator, extraction of a service path, a class name, a module name, an instantiation mode and a unique identifier as metadata, generation of a module-level mapping table and merging into a global mapping table, and establishment of a one-to-many mapping relationship from the service path to an implementation item array; loading of the global mapping table into a memory Map structure in a running period, receiving of a service query request from a calling party, searching for a corresponding implementation item according to the service path and supporting of filtering according to an identifier; dynamic loading of a target HSP module by calling a napi_load_module_with_info native interface, obtaining of a constructor from an export object and creation of an instance, and caching of a singleton mode implementation item.

The invention relates to the technical field of data serialization, and particularly provides a structured storage fixed-length serialization method and system based on a Rust process macro, and the method comprises the following steps: analyzing declarative attributes in a structured data definition through the Rust process macro, and obtaining a preset fixed length of a variable-length field; based on the preset fixed length, automatically configuring the memory capacity for the variable-length field to avoid dynamic capacity expansion; converting the structured data into a byte sequence by adopting a fixed-length serialization algorithm, so that the total length of the byte sequence is fixed and is irrelevant to a field actual value; when the actual data length of the variable-length field exceeds a preset fixed length, intelligent truncation is performed on the actual data, and the data integrity is maintained; performing type verification on the serialization process in a compiling period by utilizing a type checking mechanism of a Rust compiler; the execution logic of the previous steps is generated in the compiling period through the Rust process macro, so that no redundant operation exists in the running process; according to the scheme, the fixed-length serialization processing of the structured data is comprehensively optimized.

The invention discloses a method, a system and equipment for calling a generic method by a Rust language. Wherein. The method comprises an expansion step during compiling and a calling step during running, during compiling, a package function for expanding trait and type erasure / recovery is automatically generated through process macro analysis trait and specific implementation, and mapping of the type and the package function is registered to a global table. During operation, when the generic method is called for the trait object, the registry is inquired according to the actual type, the corresponding packaging function is found and executed, and therefore the original generic method is indirectly called for implementation. The core is to realize dynamic distribution of generic methods through compilation period code generation and runtime search. According to the method, the core limitation that the trait object in the Rust language does not support the generic method is successfully solved, and the dynamic generic method calling with safe type and zero running overhead is realized.

The invention relates to the technical field of computer compiling, and discloses a method and a device for simultaneously compiling multiple architectures, computer equipment and a storage medium. According to the method for simultaneously compiling the multiple architectures, the code files input by the user are processed through the user-defined linker, the multiple code files are analyzed, and therefore analysis operation in the compiling process in all the architectures can be advanced, and a unified intermediate file is generated. And continuing to compile the generated unified intermediate file in each architecture, and finally obtaining an executable file or a library file corresponding to each architecture. According to the embodiment of the invention, the analysis operation is advanced, and the unified intermediate file is generated, so that the analysis operation does not need to be executed for multiple times when compiling is continued under each framework, and the effects of shortening the compiling time and saving computing resources can be achieved.

The application provides a script generation method and device, equipment, storage medium and program product, wherein the script generation method is applied to a vehicle, comprising: during pre-compilation, obtaining a standardization document of the vehicle; the standardization document comprises signal data of controller area network (CAN) signals transmitted between an application layer and a framework layer in the vehicle; based on the signal data of each CAN signal in the standardization document, a communication method of each CAN signal is generated; the communication method is used for transmitting the CAN signal between the application layer and the framework layer; according to the communication method of each CAN signal, a script file is generated; the script file is used to be loaded during compilation so that the communication method in the script file is called. Through the above method, the efficiency and accuracy of obtaining the CAN signal of the vehicle are improved.

The invention provides a program variable value forcing method and device during PLC program running, and the method comprises the steps: obtaining variable definition code information through an interactive interface; the compiler compiles the variable definition code information, generates a forcing function program for realizing variable value forcing and downloads the forcing function program to the PLC, and the forcing function program sets a target pointer corresponding to a target variable to point to a specified memory address from pointing to an original target memory address; a variable value forced limiting command is obtained through the interactive interface, and the variable value forced limiting command is used for requesting to forcibly limit a variable value of a target variable in a target PLC program running by the PLC to be a target value; and the PLC executes a forcing function program to endow a target value to a memory space pointed by the target memory address, and forcibly limits the variable value of the target variable to be the target value. The problem that compilation time and program running time are prolonged due to the fact that a target file generated through compilation is larger due to variable value forced limitation is solved.

This disclosure describes a system and method for compiling and executing machine learning inferences in an array of multi-core computing devices. Each multi-core computing device can be an application specific integrated circuit (ASIC) or group of ASICS. In many applications, the array of computing devices changes from inference to inference, and can be adjusted based on the requirements of the inference. Additionally, each ASIC can have multiple processing cores, and multiple types of processing cores. Therefore, performing optimizations and scheduling at compile time, can dramatically increase the efficiency of the array in executing the inference. In some implementations, it is possible to select an amount of time or effort to be spent optimizing during compiling, giving the user flexibility in determining whether to spend time during compilation or during execution.

A method and system provide the ability to process source computer instructions. The source computer instructions are obtained and include input statements that consist of two functions that consume one or more arguments. A legal configuration of the functions and arguments is determined. A first function can be evaluated to yield a non-variable value, and a second function cannot be evaluated to yield a non-variable value. The input statements are compiled into executable code using the determined legal configuration such that during compilation, the first function is executed, and instructions are emitted to execute the second function at an indeterminate time.

The present invention provides an off-line software-in-the-loop simulation development system and an off-line software-in-the-loop simulation method. A general firmware architecture is compiled to generate a chip control program. The general firmware architecture includes an application layer and a hardware abstraction layer. The application layer has a setup header file and a product program. Processing programs required by peripheral modules are added to the hardware abstraction layer at compile time. The chip control program is provided to a controller chip or circuit simulation software to control product-related circuits by controlling peripheral modules.

A compiler comprises a low-level memory management (LLMM) module that locates computed entities within source code. Each computed entity is analyzed, and resource costs associated with each computed entity are calculated. A memory model is selected for each computed entity, based on memory use, computational complexity, and other factors. User-defined memory model assignment is supported. The compiler auto-generates instructions for allocating memory for, computing, and deallocating memory for each computed entity. The instructions generated for each computed entity will vary based on its assigned memory model. A variety of embodiments are disclosed for auto-generating these instructions during compile time at differing phases of compilation. In all of those, with the resultant executable code, memory is allocated and freed at runtime automatically and accurately without the intervention in source code by a programmer.

The invention relates to a software package compiling method, system and device and a medium, and the method comprises the steps: reading dependency information of each software package in a software development project, and constructing a dependency list of each software package; based on the dependency list, determining software packages meeting compiling conditions from the software packages to obtain a to-be-compiled software package list, and executing parallel compiling of the software packages in the to-be-compiled software package list; deleting and updating compiled software packages in the to-be-compiled software package list from a dependency list of uncompiled software packages; and on the basis of the deleted and updated dependency list, re-obtaining the to-be-compiled software package list, carrying out parallel compiling, and circularly deleting, updating and carrying out parallel compiling until all the software packages of the software development project are compiled. By means of the method and device, parallel compiling directly based on the software package dependency information is achieved, a large amount of compiling time can be saved, and the problem of how to improve the software package compiling efficiency in the application software development process is solved.

The invention discloses a vector chain type calculation method and system based on a C + + expression template. The system comprises a type information extraction module, a vector packaging and interface module, an operation implementation module, an expression node module and an operator reloading module. Firstly, a C + + template mechanism is applied, the whole expression is constructed into an expression type tree during compiling, intermediate temporary variables are completely eliminated, redundant memory allocation and data copying are effectively avoided, and the calculation efficiency during operation is remarkably improved. And secondly, by introducing an inline expansion and loop fusion technology, deeper and more efficient performance optimization can be realized in a compiling stage. Thirdly, an operator reloading mechanism is adopted, unified modeling is conducted on three types of operation, natural expression can be achieved, the expression ability of the system is remarkably improved, and the application range of the system is remarkably widened. Finally, an SIMD instruction set is introduced through an expression template and a type feature extraction mechanism, and single-instruction multi-data-level parallel processing is achieved.

The application discloses a service capability tracking method based on compiling period bytecode analysis, belongs to the technical field of API calling management, and is used for solving the problem of insufficient perception of API calling conditions of a client by a server. The method comprises the following steps: a bytecode acquisition module acquires bytecode files in compiling products in a compiling process of a user-side application program and delivers the bytecode files to a bytecode analysis module; the bytecode analysis module performs iterative analysis on the bytecode files, identifies classes, methods and method calling instructions, analyzes calling behaviors of the client on API capabilities of the server from the bytecode level, extracts API service capability calling information, and delivers the API service capability calling information to a service capability recording module; and the service capability recording module arranges the API service capability calling information, and generates tracking data files used for representing corresponding relationships between the client and API service capabilities. Effects: the server can acquire calling information of various API capabilities of the client, and thus effective perception and management of API using conditions can be realized.

This application relates to a method for generating cross-architecture computationally intensive fusion operators based on hardware abstraction. It constrains and determines the operator subgraph according to preset legality rules, establishes a unified semantic abstraction, defines the fusion operator as a coordinate-driven pure function, and encapsulates auxiliary tensor memory access handles and layout geometry information through runtime context. A backend normalization layer is used to semantically reinterpret the accumulator layout and thread organization of different hardware vendors during compile time, and cross-platform vectorization primitives are invoked to mask the differences in backend instruction set architectures. Arithmetic logic is downgraded to a sequence of instructions executed within a scalar scope. The abstract vector view is first decomposed into independent scalar elements, arithmetic instructions are generated in the scalar dimension, the calculation results are then reorganized into a vector register, and finally, an address expression is constructed by deriving the effective step size to handle broadcast and indexing logic, generating fusion code that can access the underlying vendor's computationally intensive kernel, thus improving development efficiency.

The invention provides a GPU-oriented compiler constant storage method and device, equipment and a medium, and belongs to the field of data processing. According to the method, a control buffer with a dynamic size is divided in a scalar register file and is shared by a whole kernel, a Workload Manager is responsible for space distribution, recovery and initialization, and constants are stored in the control buffer divided by a scalar register during compiling, so that a GPU of an SIMT architecture does not need to have multiple copies in a scalar register file at the same moment, and the number of copies in the scalar register file at the same moment is reduced. And a constant does not need to be obtained from a memory, and the instruction code can accommodate a plurality of 64-bit immediate operands, so that the problem of insufficient resource utilization of a large number of scalar registers in the prior art is solved.

Systems and methods for validating operation of a software sequence may include: monitoring signals on a bus of a processor, comparing the contents of the signals on the bus to pre-stored information from compile time. If the comparing generates a match, that may indicate that the software sequence is operating as intended. However, if the comparing generates a mismatch, that may indicate that the software sequence is not operating as intended and may, in fact, indicate a malicious use. Further actions can be taken in response to a mismatch, including resetting a processor, issuing an interrupt, and the like.

The invention discloses a non-intrusive cloud native fault injection method and device based on compilation period conditional isolation. The method comprises the following steps: declaring that a packet-level function variable points to real implementation in a service code, and indirectly calling through the variable; creating a fault simulation library to construct label isolation, executing a double-track construction process based on constructed labels, redirecting variables to fake implementation during test construction, and producing, constructing and eliminating a fault library; in fake implementation, atomic-scale refined fault semantics are defined based on configurable parameters; injection behaviors are controlled through a state machine model (including a fault injection state, a recovery decision point, a steady-state execution state and a process termination state); and integrating the audit logs and automatically checking the purity of the production binary system in the CI / CD. According to the method, zero residue of production codes and zero performance overhead are realized, accurate fault simulation and full-link auditing are supported, compliance and safety requirements of strong supervision scenes such as finance and government affairs are met, and an efficient scheme is provided for toughness verification of a cloud native system.

A system receives ETL specification for processing stream data, including a transform operation represented using a database query specification. The system generates a dataflow graph of a sequence of database queries by decomposing the database query into a first database query that generates an intermediate results table, and a second database query that receives as input the intermediate results table and outputs data used for performing the transform operation. The system executes the sequence of database queries for performing the transform operation on stream data received from the source. When receiving an incremental data set, the system determines an output change set based on the received incremental data set by traversing an execution plan and processing each operator in the execution plan, and computing a change set of a particular operator from the change sets output by the one or more other operators based on the incremental data set.

Data processing units of a neural network hardware accelerator may be configured to perform neural network operations using configuration descriptors generated by a compiler. Growing sizes of neural network models can mean that the compiled configuration descriptors can become larger in size as well. Compile time can be longer, and storage overhead also increases. To address this issue, a compact configuration descriptor format having a constant configuration descriptor and a variable configuration descriptor can be used. The compact configuration descriptor format facilitates reuse across blocks, within blocks, and within a mixture of experts transformer-based machine learning model. The compact configuration descriptor format can dramatically reduce the size of the compiled configuration descriptors.

The embodiment of the invention provides a compilation period optimization method and system based on an AI large model. The method comprises the following steps: firstly, identifying a target optimization point in an original calculation graph, and generating a query request containing parameter configuration information of each candidate optimization scheme so as to facilitate subsequent performance evaluation; a unique identifier is generated based on the parameter configuration information to query a performance database, repeated measurement of the same optimization scheme is avoided, and redundant operation is reduced; and when the database does not store the performance data corresponding to the identifier, issuing a hardware measurement task containing parameter configuration information to the target hardware equipment, directly obtaining real performance data through a measurement result, and finally determining a target optimization scheme based on the measurement result and generating a target calculation graph. According to the process, a developer does not need to manually compile and add a measurement function for a new optimization scheme, and the limitation of a manual expansion function library on the exploratory optimization capability of a compiler in a traditional scheme is effectively broken through, so that the expandability of a system facing a new optimization mode can be improved.

Techniques for parallel processing using hazard detection and mitigation are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operations are tagged with precedence information. The tagging is contained in the control words. The tagging is provided by the compiler at compile time. Memory access operations are monitored. The monitoring is based on the precedence information and a number of architectural cycles of the cycle-by-cycle basis. The tagging is augmented at run time, based on the monitoring. Memory access data is held before promotion, based on the monitoring.

The invention discloses a mirror image file generation method and device of an operating system and a readable storage medium, and the method comprises the steps: receiving a mirror image file generation instruction, and generating a mirror image file from a shared storage space of a first mirror image file generation device or a second mirror image file generation device based on dependency relationship information carried by the mirror image file generation instruction; according to the method, the corresponding compiling intermediate file or the corresponding compiling target file is obtained, the compiling intermediate file or the compiling target file is processed, and the mirror image file of the target operating system is generated, so that compared with a mode of compiling the source code to generate the compiling target file and then processing the compiling target file to generate the mirror image file, the method is more efficient. The compiling time and the mirror image file generation time can be greatly shortened, and then the construction efficiency of an operating system (such as a personalized embedded Linux operating system) can be improved.

The application discloses an RTOS task hook type adaptation method based on a compiling period static trampoline function table, and comprises the following steps: S1, a compiling period presetting stage; S2, a running period binding stage; S3, a running period calling stage; and S4, a running period canceling stage. According to the application, a static trampoline function is pre-generated in the compiling period, all codes are solidified to a read-only Flash area after being compiled, and any code does not need to be generated in the running time, so that the contradiction between the running time code generation and the MCU hardware characteristics is fundamentally solved, the system complexity and the Flash occupation are reduced, a one-to-one mapping relationship between a user hook function and the trampoline function is established through a bidirectional binding table, and when being canceled, the corresponding slot can be reversely positioned only through the user hook function pointer, the whole hook list does not need to be traversed, the time complexity is O (n), the real-time loss of a traditional dynamic link table scheme is eliminated, and the resource leakage and the hook residual problem are avoided.

The application provides a multi-kernel geometric object and algorithm adaptive mapping method and system, which comprises the following steps: facing a CAD platform layer capable of supporting multiple geometric kernels, a developer selects a target geometric kernel to be bound from candidate geometric kernels before system compilation or construction, and determines the corresponding relationship between the topological object, geometric object, attribute data, precision data and native algorithm function of the selected geometric kernel and the platform unified topological expression and unified algorithm interface according to the pre-defined mapping rule corresponding to the selected geometric kernel; in the compilation or construction stage, the mapping rule is solidified into the corresponding kernel adaptive interface implementation, object construction rule and algorithm encapsulation logic; in the system running period, the upper-layer application performs modeling operation through the unified geometric object model and unified algorithm interface, and the lower layer fixedly calls the geometric kernel native object and native function which have been bound in the compilation period.

The invention discloses a method and device for processing GPU shared memory allocation by an llvm compiler, and belongs to the field of data process.The method includes the steps that a kernel function call chain is reconstructed, equipment functions called by multiple kernels are renamed after being copied, and shared memory variables in the equipment functions are copied at the same time; it is ensured that each device function only exists in one call chain, so that the problem of device function shared memory address conflict in the compiling period is solved, and meanwhile accumulated calculation of offset addresses and memory sizes of related shared memory variables in the kernel function call chains is achieved by setting global variables of a kernel action domain. And the problem of shared memory allocation during compiling is efficiently solved.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus identifies load and store operations in program code that access an array of structures. The apparatus assigns metadata to each of the identified load and store operations. The metadata associated with each operation represents a structure of the array. The apparatus generates oracle conditions for the program code based on the metadata to facilitate register promotion. One or more indices of the array accessed by the load and store operations are not known at compile time.