21 results about "Compile time" patented technology

The embodiment of the present application provides a kind of compiling method and electronic equipment, it is related to computer technical field, to solve the problem of low compiling efficiency when the source code is compiled currently.The method, at the time of compiling, can utilize the binary file corresponding to the API information of the binary file that is precompiled with the target function module to be compiled, and the source code of the target function module is compiled, to obtain the machine executable binary file of the target function module.Wherein, binary file is precompiled, not generated at the time of compiling.Furthermore, the binary file that is compiled corresponds to API information, according to the binary file corresponding to the second function module and the API information of the binary file, the compilation of the first source code can be completed, without further determining the function module that the second function module depends on, so that the process of compiling is also simplified, and the compiling time can be reduced, and the compiling efficiency is improved.

The application provides a script generation method and device, equipment, storage medium and program product, wherein the script generation method is applied to a vehicle, comprising: during pre-compilation, obtaining a standardization document of the vehicle; the standardization document comprises signal data of controller area network (CAN) signals transmitted between an application layer and a framework layer in the vehicle; based on the signal data of each CAN signal in the standardization document, a communication method of each CAN signal is generated; the communication method is used for transmitting the CAN signal between the application layer and the framework layer; according to the communication method of each CAN signal, a script file is generated; the script file is used to be loaded during compilation so that the communication method in the script file is called. Through the above method, the efficiency and accuracy of obtaining the CAN signal of the vehicle are improved.

The present invention provides an off-line software-in-the-loop simulation development system and an off-line software-in-the-loop simulation method. A general firmware architecture is compiled to generate a chip control program. The general firmware architecture includes an application layer and a hardware abstraction layer. The application layer has a setup header file and a product program. Processing programs required by peripheral modules are added to the hardware abstraction layer at compile time. The chip control program is provided to a controller chip or circuit simulation software to control product-related circuits by controlling peripheral modules.

The application discloses a service capability tracking method based on compiling period bytecode analysis, belongs to the technical field of API calling management, and is used for solving the problem of insufficient perception of API calling conditions of a client by a server. The method comprises the following steps: a bytecode acquisition module acquires bytecode files in compiling products in a compiling process of a user-side application program and delivers the bytecode files to a bytecode analysis module; the bytecode analysis module performs iterative analysis on the bytecode files, identifies classes, methods and method calling instructions, analyzes calling behaviors of the client on API capabilities of the server from the bytecode level, extracts API service capability calling information, and delivers the API service capability calling information to a service capability recording module; and the service capability recording module arranges the API service capability calling information, and generates tracking data files used for representing corresponding relationships between the client and API service capabilities. Effects: the server can acquire calling information of various API capabilities of the client, and thus effective perception and management of API using conditions can be realized.

This application relates to a method for generating cross-architecture computationally intensive fusion operators based on hardware abstraction. It constrains and determines the operator subgraph according to preset legality rules, establishes a unified semantic abstraction, defines the fusion operator as a coordinate-driven pure function, and encapsulates auxiliary tensor memory access handles and layout geometry information through runtime context. A backend normalization layer is used to semantically reinterpret the accumulator layout and thread organization of different hardware vendors during compile time, and cross-platform vectorization primitives are invoked to mask the differences in backend instruction set architectures. Arithmetic logic is downgraded to a sequence of instructions executed within a scalar scope. The abstract vector view is first decomposed into independent scalar elements, arithmetic instructions are generated in the scalar dimension, the calculation results are then reorganized into a vector register, and finally, an address expression is constructed by deriving the effective step size to handle broadcast and indexing logic, generating fusion code that can access the underlying vendor's computationally intensive kernel, thus improving development efficiency.

The application provides a multi-kernel geometric object and algorithm adaptive mapping method and system, which comprises the following steps: facing a CAD platform layer capable of supporting multiple geometric kernels, a developer selects a target geometric kernel to be bound from candidate geometric kernels before system compilation or construction, and determines the corresponding relationship between the topological object, geometric object, attribute data, precision data and native algorithm function of the selected geometric kernel and the platform unified topological expression and unified algorithm interface according to the pre-defined mapping rule corresponding to the selected geometric kernel; in the compilation or construction stage, the mapping rule is solidified into the corresponding kernel adaptive interface implementation, object construction rule and algorithm encapsulation logic; in the system running period, the upper-layer application performs modeling operation through the unified geometric object model and unified algorithm interface, and the lower layer fixedly calls the geometric kernel native object and native function which have been bound in the compilation period.

The application discloses a dynamic link library reflection method based on a C language preprocessor, and comprises the following steps: S1, acquiring the file name of a dynamic link library to be agented and a function list to be agented, wherein the function list comprises the function name, return type and parameter type of each function; S2, constructing a registerer by using the macro definition of the C language, wherein the input of the registerer is the file name of the dynamic link library, the function name to be agented, the return type and the parameter type; S3, generating an agent function by using the registerer in the preprocessing process of the compiler at the compiling stage; S4, registering the function to be agented in the source code by using the registerer in step S3; and S5, calling the function to be agented in S1 in the business, and compiling and running the software together with the registration code in step S4. The application solves the compatibility problem caused by using different version library modules or using the same library module in different versions of the same product.

The present technology provides a scripting tool, built on top of an object component architecture of a game engine for creating games, that binds an event class for a tagged event handler in code at compile time. The event handler in code is tied to movement of one or more objects and associated effects within a game environment. Through the scripting tool, game engineers generate and define an event handler in code for the designers to discover and add various other effects to in forming gameplay sequences. The game designers tag the event along with the other effects, and at compile time, forming an event class including the tagged effects.

Hardware semaphores are used to improve the speed of evaluating preconditions. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. A collection of hardware semaphores can be chained together to implement a chained semaphore that can support multiple conditions. Furthermore, hardware semaphores can not only have the ability to generate interrupts, but also commands, such as commands to other semaphores. A compiler can perform the implementation of a chained semaphore across multiple hardware semaphores at compile time or at runtime. An integrated circuit chip can include multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of a hardware semaphore array. A dedicated on-chip network can implement hardware semaphore communication.

The disclosed systems, structures, and methods are directed to optimizing memory access to constants in heterogeneous parallel computers, including OpenCL-enabled systems. This is implemented in an optimizing compiler that converts program-scoped constants and constants scoped to the outermost level of a kernel to implicit constant pointer parameters. The optimizing compiler also attempts to determine access patterns for constants at compile time and places the constants in various memory types available in the compute device architecture based on these access patterns.

The application provides a pointer recycling method, system and device, the method comprising: scanning source code or an abstract syntax tree through a compile-time automatic instrumentation module, identifying a resource reference entry and a target variable to be managed, inserting a cleanup attribute and ownership transfer semantics for the target variable, and generating a resource description table; the resource reference entry comprises a naked pointer; the naked pointer is wrapped using a lightweight proxy structure, and metadata is associated through the lightweight proxy structure; a resource in the resource description table is registered, reference count management is performed, cross-function transfer migration is performed, and a unified cleaning operation is performed through a runtime resource manager, to obtain a pointer life cycle state; system memory occupation information is collected in real time at runtime, memory recycling frequency and strategy are dynamically adjusted according to the memory occupation information, and resource recycling is performed according to the pointer life cycle state. The scheme improves the stability of long-term system operation, and improves the stability, reliability and development efficiency of C language software development.

The present application relates to the technical field of software security detection and compiler optimization, and particularly relates to a memory security detection optimization method, system, device and medium based on static risk grading and dynamic gradient instrumentation. Four types of features, including alias analysis, cross-process data flow, variable escape and boundary determinacy, of memory access instructions are extracted in the compilation period, and a static risk level is generated by weighted aggregation and written into an instrumentation metadata section; a full detection, sampling detection and exempted skipping three-level intensity instrumentation template library is bound in the linking period; and detection intensity gradient redirection is implemented in the running period according to the risk level in the form of atomic instruction hot patching; and the compilation period feature weight is corrected reversely according to the running period exception, so as to form a closed loop. The present application retains the full detection capability of high-risk instructions under high load, while reducing the overall runtime overhead.

A compile-time link type manager is defined to facilitate development of source code with disciplined link type object management at runtime. In one aspect, the link type manager ensures that all link type object management constructs have associated event handlers. Additionally, an event handler can be evaluated at compile time to ensure that it meets certain conditions for the particular link type, referred to as link-type criteria.

The application provides a software application generation method and device, electronic equipment and storage medium. The method comprises the following steps: in response to a construction request for a target version, determining a set of differentiated elements associated with the target version; in a software construction stage, performing compile-time differentiated processing on a common code library based on the set of differentiated elements to generate an application package carrying static features of the target version; in a running stage of the application package, performing runtime differentiated processing on the application package based on the set of differentiated elements to provide dynamic functions of the target version; wherein, through the combination of the compile-time differentiated processing and the runtime differentiated processing, a software application with complete functions of the target version is generated from the common code library. Through the present scheme, all customized versions can generate complete function applications based on the same set of common code libraries, eliminating synchronization and merging conflicts in multi-branch development.

This invention relates to the field of Windows kernel driver technology, specifically to a kernel hardware access driver system based on a signature verification script virtual machine. It includes a driver framework module, a bytecode integrity verification module, a script virtual machine module, and a hardware access primitive module. The bytecode integrity verification module performs a byte-by-byte constant-duration comparison of the message authentication code signature of the loaded bytecode to resist timing side-channeling. The hardware access primitive module, during compilation for the ARM64 architecture, stores a first stub array and a second stub array generated by compiling constant expression functions in a read-only executable section, and directly uses the instruction word bit field as the array subscript index for access. This invention supports hot-swapping of driver functions and dynamic access to any ARM64 system register under the constraints of non-writable and executable memory protection.

The application is suitable for the field of computer programming and provides a Java language LINQ expression implementation method based on chain calling, which comprises the following steps: providing a LinqQuery interface, the LinqQuery interface defines a chain operator where operator and select, and type safety is provided through a generic T; a user generates an operator tree through calling the chain operator of the LinqQuery interface, the operator tree is used for recording query logic; the operator tree is parsed, query is executed in layers, and a result set is returned; the application has the beneficial effects that compared with traditional loop and conditional branch implementation, the number of code lines is reduced by about 40%, the readability is significantly improved, through an open operator interface, a developer can easily extend query functions, through generic constraints, type checking of query logic is completed at the compilation stage, runtime errors are reduced, and unified query of various scenes such as memory collection, database query and file reading is supported.

Embodiments of the present application provide a kind of compiling task scheduling method, device, electronic equipment and computer readable storage medium, involve task scheduling field.The method comprises: receiving to-be-compiled task information;Determine whether there is candidate idle compiling machine in current time compiling machine, if there is, obtain the compiling record of each candidate idle compiling machine, according to to-be-compiled task information and the compiling record of candidate idle compiling machine, from candidate idle compiling machine, determine the compiling machine of executing to-be-compiled task.The present application is determined by to-be-compiled task information and the compiling record of candidate idle compiling machine, from candidate idle compiling machine, to determine the compiling machine of executing to-be-compiled task.Thereby it is based on to-be-compiled task information and the compiling record of candidate idle compiling machine, to reasonably allocate the compiling machine of executing compiling to-be-compiled task, to reduce the compiling time of to-be-compiled task and the waiting time of to-be-compiled task, improve compiling efficiency.

The application provides a black-box fuzz testing method and system for numerical calculation program runtime exception awareness, wherein, without source code and without compilation period plugging, execution information is obtained through a runtime dynamic monitoring mechanism, runtime instruction execution state and numerical operation state are jointly monitored, an abnormal state occurring in a numerical calculation process of a program is captured and identified, real-time awareness, classification and feedback guidance of numerical calculation exceptions are realized, the awareness process is oriented to an instruction level and an operation level, potential numerical instability behaviors can be identified without program crash, thereby, the technical limitation that traditional black-box fuzz testing can only perceive 'process level exceptions' is broken, and the black-box fuzz testing can perceive not only crashes but also numerical calculation exceptions such as floating point exceptions and integer overflow.

Apparatuses, systems, and techniques to generate a memory allocation plan for a set of tensors. In at least one embodiment, tensor data corresponding to the set of tensors is stored into memory locations at run time based, at least in part, on the memory allocation plan generated at a compile time.

A data processing system includes compile time logic configured to generate configuration files for applications executing on reconfigurable processors, and execution flow logic configured to manage execution with conditional breakpoint capabilities. The system provides state inspection interfaces for examining processor state, memory contents, and application variables during stopped execution. Runtime logic executes configuration files with support for conditional breakpoints triggered by runtime data values, performance metrics, or error conditions. The system enables multi-processor synchronization with coordinated breakpoint handling across processor arrays, dynamic reconfiguration of processor configurations during stopped execution, and performance profiling at breakpoint locations. Breakpoint conditions can be defined at multiple granularity levels for computational graphs and dataflow applications. The system supports interactive debugging with step-through execution control and real-time modification of execution parameters.