93 results about "Cache locality" patented technology

Apparatuses, systems, and techniques to cause information to be invalidated in a second cache location after information is stored in a first cache location. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be invalidated in a second cache location after information is stored in a first cache location.

The invention relates to the technical field of edge computing, and discloses a network data efficient caching method and system based on edge computing, which realize dynamic identification of hotspot data and optimal caching position decision by analyzing edge node data flow characteristics and network topology states in real time. Firstly, data packet meta-information is extracted from an edge node, a content feature vector is generated, and data popularity is evaluated; secondly, analyzing a network topology structure and a link state, and screening candidate cache nodes; then, factors such as service priority, network reliability and topology stability are fused, and an optimal cache position is determined by adopting a reinforcement learning algorithm; and finally, the cache content is updated, the cache state is synchronized between the edge nodes, and the cache distribution is optimized. The data access efficiency and the resource utilization rate of the edge network can be effectively improved, and the method adapts to dynamically changing network environments and user requirements.

The invention provides a multi-tenant large model reasoning service architecture and an operation method thereof, and the architecture comprises a multi-level cache module which is used for managing the storage of a LoRA model in a video memory, an internal memory, a disk and a remote memory according to the priority; the route registration module is used for recording the model cache position and the load state of each server; the dynamic routing module is used for allocating requests according to the tenant identifiers and the server states; and the parameter fusion module is used for superposing the LoRA model and the basic model to generate a personalized inference model. According to the method, efficient resource utilization and low-delay service are realized through multi-stage cache management, a dynamic routing strategy and a load balancing mechanism. The framework supports on-demand loading and parameter fusion of the tenant personalized LoRA model, and the reasoning service efficiency in a multi-tenant scene is remarkably improved.

The embodiment of the invention provides a robot tallying method and system, a server and a storage medium, and relates to the technical field of intelligent warehousing, and the method comprises the steps: obtaining a tallying task of carrying a target material box in a warehouse from a first storage position in a first goods shelf to a second storage position in a second goods shelf; determining a first cache position of the target material box according to the first storage position, and controlling the first robot to carry the target material box from the first storage position to the first cache position; the first cache position belongs to a first cache area in the same column as the first goods shelf; according to the second storage position and the first caching position, a second caching position of the target material box is determined, and a second robot is controlled to carry the target material box from the first caching position to the second caching position; the second cache position belongs to a second cache region which is in the same column as the second goods shelf and in the same layer as the first cache region; and the third robot is controlled to carry the target material box from the second cache position to the second storage position, and the tallying efficiency is improved.

The invention relates to the technical field of computer data storage and distributed systems, in particular to a distributed read-write method for large model training, which comprises the following steps of: constructing a hierarchical structure of local cache, distributed shared cache and persistent storage, and maintaining a global cache table copy at each client to register file blocks and cache positions. And during writing, firstly writing in a local cache and copying to other client nodes, and submitting persistent storage after registration is completed. During reading, the file blocks are obtained from the local cache and the distributed shared cache in sequence, if the file blocks are not hit, the file blocks are obtained from the persistent storage, meanwhile, the effective file blocks are written back to the local, and table items are supplemented. Unified visibility is achieved through position mapping and version constraint, nearby reading and fault recovery are achieved, back-end pressure and access delay are reduced, and the method is suitable for large-scale training and batch processing scenes.

The invention relates to a data reading and writing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: receiving a data reading request; if the resource type corresponding to the data reading request is a pixel buffer object, aligning the horizontal offset of the pixel buffer object with a target buffer position to obtain a first mapping logic address; and converting the first mapping logic address into a first physical address, reading first target data from the pixel buffer object according to the first physical address, and storing the first target data to the target cache. By adopting the method, the data reading efficiency can be improved.

The invention discloses a system operation state monitoring method and system for battery management system fault occurrence. The method comprises the following steps: constructing a linked list D data structure comprising M data cache positions; constructing a system state cache data structure comprising N data areas; updating the system operation state data in the data area regularly and sequentially; when monitoring that a fault occurs, recording a fault ID and a fault occurrence timestamp and storing the fault ID and the fault occurrence timestamp to a blank data cache position, and storing all system operation state data in a system state cache data structure corresponding to a fault occurrence time point to the blank data cache position; cyclically traversing the linked list, and judging whether a fault occurrence timestamp exists in the current data cache position or not and whether preset delay fixed time from the fault occurrence timestamp is met or not; if yes, storing all the system running state data in the system state cache data structure corresponding to the time point when the preset delay fixed time reaches to the current data cache position, transferring the data in the current data cache position together, and judging the next data cache position.

The invention discloses a convolution weight gradient calculation method and device, a medium, equipment and a product, and the method comprises the steps: carrying out the role distribution of an input feature map and a corresponding output gradient map in a global memory, and determining a dynamic sliding map and a static fixed map; respectively extracting a sliding part and a corresponding fixed part from the dynamic sliding graph and the static fixed graph, and enabling each thread to hold a data row and a corresponding aligned data block in the sliding part; and in each thread, carrying out synchronous sliding and point multiplication operation on the held data row and the aligned data block to obtain a local calculation result of a current sliding position, accumulating the local calculation result to a cache position of the weight gradient matrix, and after synchronous traversal calculation of all sliding parts and corresponding fixed parts is completed, obtaining the weight gradient matrix of the convolution kernel. According to the method, data multiplexing in the sliding direction can be effectively realized, and the data volume read repeatedly is reduced, so that the calculation efficiency of the weight gradient is improved.

The invention provides a data processing method and device of a processor, equipment, a medium and a program product. The method comprises the steps of loading an mth data block in a first matrix to a first cache position of an internal memory through a first thread in a thread group of a processor, and loading an nth data block in a second matrix to a second cache position of the internal memory; loading the (n + 1) th data block in the second matrix from the external memory to a third cache position of the internal memory through the first thread, and performing multiplication operation on the data blocks in the first cache position and the data blocks in the second cache position through the second thread; and loading the (n + 1) th data block in the second matrix from the internal memory to a second cache position of the internal memory through the first thread, and performing multiplication operation on the data block in the first cache position and the data block in the third cache position through the second thread. According to the invention, the calculation speed of multiplication in the processor can be improved.

The embodiment of the invention relates to a text processing method and device, computer equipment and a storage medium, and the method comprises the steps: carrying out the fragmentation processing of a semantic unit contained in an input text, and obtaining a plurality of semantic fragments; calculating an importance score for each semantic fragment; according to the attribute information and the importance score of each semantic fragment, determining a cache position corresponding to the semantic fragment; and storing each semantic fragment to a corresponding cache position. Therefore, the text can be fragmented through the semantic unit, semantic segmentation is avoided, semantic continuity is guaranteed, meanwhile, each semantic fragment is stored to the corresponding cache position according to the attribute and importance, and the utilization efficiency of calculation and storage resources is improved.

The invention relates to a page data acquisition method and device, communication equipment, a storage medium and a program product, and the method comprises the steps: receiving a geographic cache pre-request sent by a client, the geographic cache pre-request being used for requesting page cache data of a target page of a target application; in response to the geographic cache pre-request, determining a target cache position matched with the position of the client and target page cache data corresponding to the target cache position from the geographic cache data based on a target query strategy; the target query strategy comprises a target query radius, and the distance between the target cache position and the position of the client is smaller than or equal to the target query radius; the geographical cache data comprises a plurality of cache positions and a plurality of pieces of page cache data corresponding to the plurality of cache positions respectively; the page cache data is real page data of a target page displayed by a client at a corresponding cache position before the geographical cache pre-request; and returning the target page cache data to the client.

The invention discloses a data caching method and device, equipment and a medium. The method comprises the following steps: acquiring metadata of to-be-cached data; the metadata comprises an index key, a data value and a data recent calling frequency; according to the recent data calling times of the to-be-cached data, calculating a heat value of the to-be-cached data; comparing the popularity value with a popularity threshold value, and determining a popularity comparison result; determining a data type of the to-be-cached data according to a popularity comparison result; according to the data type, determining a cache position corresponding to the to-be-cached data; and caching the to-be-cached data to the corresponding caching position according to the caching position of the to-be-cached data and the metadata. According to the embodiment of the invention, the data caching efficiency can be improved.

The invention discloses a PCIe-based multi-channel DMA task management system and method, and relates to the technical field of data transmission, and the method comprises the steps: employing a DMA task reading control module and a mark number management module to apply for a unique mark number for each reading request, so as to distinguish the DMA task of each channel, and a DMA task storage control module and a cache management module are utilized to manage cache position numbers corresponding to the mark numbers, the DMA tasks of the channels are read according to the mark numbers, and the DMA tasks are written into corresponding cache positions, so that the DMA tasks of the channels are prevented from being executed out of order. The technical problems that the DMA task reading efficiency is low and extra cache resources are occupied when the DMA tasks of the multiple channels are executed in an order-preserving mode are solved, and the technical effects that the DMA task reading efficiency is improved, and meanwhile the cache resources are saved are achieved.

The invention provides a communication method, communication node equipment, a computer readable medium and a product, and relates to the technical field of communication, and the communication method comprises the steps: receiving a first information transmission frame sent by a first opposite-end communication node; in response to retransmission indication information generated according to a sending sequence number of the first information transmission frame, sending a first retransmission indication frame to the first opposite-end communication node, the first retransmission indication frame comprising the retransmission indication information and a first receiving sequence number, the first receiving serial number is the receiving serial number of the information transmission frame sent by the first opposite-end communication node confirmed to be correctly received at the last time by the local-end communication node; the first retransmission indication frame is used for the first opposite-end communication node to start reading the cached information transmission frame from a cache position corresponding to a first receiving serial number in a pre-configured retransmission cache region corresponding to the local-end communication node in response to the retransmission indication information, and retransmission operation is carried out.

The application provides a resource refreshing method and system. When it is needed to refresh a resource file, the application does not need to perform a refreshing operation on an edge device, but deletes a cache location record corresponding to the resource file in a database associated with a scheduling server, and then sets a first domain name for a resource file that does not need to be updated and checked when a resource access request sent from a client is received, so as to directly return the resource file in a case where the target edge device locally caches the resource file, and sets a second domain name for a resource file that needs to be refreshed, so as to perform an update check on the resource file in a case where the edge device locally caches the resource file, and obtain the latest resource file. Through the above scheme, unified refreshing operations on the edge device are not needed, and the latest resource file can also be ensured to be obtained by the client, and the performance occupation of the edge device is reduced.

The invention relates to the field of data lookup, and discloses a locality perception lookup table lookup method, which comprises the following steps of: S1, reordering between rows: clustering and reordering the rows of an input vector and a weight matrix according to the same quantized value to enable elements with the same quantized value to be continuously distributed; for a common matrix GeMV scene, cache locality is improved through rearrangement and subsequent blocking operation, and repeated loading of a lookup table LUT is reduced. And the data locality of the GeMV scene is remarkably improved through inter-line reordering and a virtual mapping strategy. On the basis of reordering of input vector element values, elements with the same value are aggregated, so that the LUT line loading times are reduced to 256 times at most from being in direct proportion to the input dimension d, and frequent replacement of the LUT lines in the WRAM is avoided; meanwhile, a weight matrix is divided into BR * BC sub-matrixes, the characteristic that vertical adjacent rows share an accumulator is utilized, multi-row sub-matrix calculation is loaded at a time, and virtual rearrangement maintains the row matching relation between an input vector and the weight matrix through index mapping.

The present invention relates to the field of machine learning technology, specifically comprising a matrix multiplication systolic array device and an interval configuration accumulation method, comprising a matrix-arranged operation core, a northbound data loader, a westbound data reshaper and loader, an accumulation buffer, an accumulator buffer controller, a result write-back controller, and a local local memory. The accumulation result write-back controller is connected to the accumulation buffer. The operation core comprises a multiplier, an adder, and an accumulation data register. The multiplier receives northbound data and westbound data, and calculates the product of the northbound data and the westbound data. The adder is connected to the multiplier and the accumulation data register, and calculates the sum of the multiplier output value and the accumulation data register value. The beneficial technical effects of the present invention include: improving the efficiency of matrix multiplication operations, enabling flexible configuration of the cache location of the result, and facilitating the write-back of the result.

The invention discloses an unpacking method and device, electronic equipment and a storage medium, and the unpacking method comprises the following steps: receiving plate demand information sent by an MES system, and determining target plates and a target number corresponding to the target plates based on the plate demand information; when the sum of the unpacked number and the non-unpacked number is larger than or equal to the target number, the following unpacking operation is executed, specifically, the target position of the non-unpacked target board in the warehouse is obtained, the stacker is used for conveying the non-unpacked target board to the RGV, and the RGV conveys the non-unpacked target board to the cache position; the non-unpacked target boards at the temporary storage position are conveyed to an unpacking station; and the non-unpacked target plates are grabbed to the plate storing and taking position one by one through the mechanical arm till all the non-unpacked target plates are grabbed to the plate storing and taking position. Manual intervention of unpacking operation is reduced, the automation level and efficiency of a production line are improved, and the efficient production requirement of intelligent manufacturing is met.

The invention provides a BMC bus data buffering device, a BMC bus and a baseboard management controller, the BMC bus data buffering device comprises a preprocessing module, an address register module and a plurality of chain type buffering structures, each chain type buffering structure comprises a plurality of chain type buffering modules, each chain type buffering module comprises a chain type buffering area and a buffering processing module, chained buffer areas of chained buffer modules in the chained buffer structure form a chained storage structure; the preprocessing module is used for distributing data packets to the chained buffer structure according to the occupation condition of the BMC bus; and the address register module is used for acquiring address storage information of the data packet address in the address storage space corresponding to the chained buffer module, so that the buffer processing module determines the cache position of the data packet in the chained buffer area and performs cache processing, and the data packets of the same data source are close to each other. According to the invention, the processing speed of the data packet is improved, the jamming phenomenon of the BMC system in operation is effectively reduced, the response capability and stability of the system are enhanced, and moreover, as each channel can be coordinated to process the data packet, the continuous high-frequency operation of the processor is avoided, and the power consumption of the processor is reduced.

The present application provides a point cloud data processing method, an apparatus, and a point cloud data processing circuit. The point cloud data processing method includes: when processing current point data by an i-th level algorithm, reading current sliding window data centered on the current point data, the current sliding window data including at least two cached data, each cached data being stored in a corresponding cache location, each cached data comprising point data and tag information identifying row number information of the point data, where i is an integer greater than 1; determining target point data based on the tag information, and determining corresponding cached data based on the target point data; and updating the current sliding window data based on the cached data that has been determined, and performing the i-th level algorithm processing on the current sliding window data.

The invention provides a content resource cache position updating method and device, equipment, a medium and a product, and belongs to the technical field of artificial intelligence, and the method comprises the steps: determining accessed path information of a target content resource in a preset time period in response to an acquisition request of the target content resource initiated by a terminal user; inputting the visited path information into a pre-trained anomaly detector, and judging whether the visited path information is abnormal or not by the anomaly detector and outputting a detection result; if the detection result is abnormal, obtaining a structure topological graph of cache nodes used for caching the content resources, and determining a feature matrix and an adjacent matrix of the structure topological graph; and obtaining a cache position updating result of the target content resource according to the feature matrix, the adjacent matrix and the accessed path information. Compared with a mode of maintaining manual configuration of an administrator, the cache position updating speed is higher, errors are not prone to occurring, and the requirement of a terminal user for application experience and increasing internet application flow can be met.

A data processing service receives a request from a user to execute code in a notebook. The service initiates a first VM for execution of the code in the notebook based on the request. The first VM may be set up with a virtual environment with configurations for executing the code. The service automatically caches the virtual environment with the configurations in a data store and automatically caches metadata associated with the virtual environment in a metadata store. The metadata may include a location identifier for identifying a caching location of the virtual environment in the data store. The metadata may include an expiration condition. When the virtual environment meets the expiration condition, the virtual environment will be invalidated in the data store. The service executes the code in the notebook in the virtual environment.

This application provides an IP address network partitioning method, apparatus, device, and storage medium, belonging to the field of asset management technology. The method includes: converting a target IP address into an integrated IP address block, wherein the target IP address belongs to either IPv4 or IPv6; determining the host bit width based on a variable-length subnet mask, and logically right-shifting the tail address block within the IP address block according to the host bit width to obtain a bit value; comparing the bit value of the tail address block with a reference bit value of the tail address block in a preset network partitioning rule to determine whether the target IP address matches the network partitioning rule. This method eliminates code redundancy and branch prediction failures. It significantly improves cache locality and instruction pipeline efficiency, thereby enhancing the adaptability of the solution.

A computer system comprises a processor core and a memory system for signal data transmission to the processor core. The memory system includes a first cache and a second cache. The first cache is located at the first level of a hierarchy within the memory system and is configured to store multiple entries of the first cache. The second cache is located at a second level of the hierarchy, lower than the first level, and stores multiple entries of the second cache. The first cache maintains a directory containing information for each of the entries in the first cache. The second cache maintains a Shadow Pointer Directory (SPD), which contains one or more SPD entries that map each entry of the first cache to a corresponding entry in the second cache at a lower-level cache location.

The invention relates to the field of GPGPUs (General Purpose Graphics Processing Unit), and particularly provides a method and a device for enhancing a cache flag bit in a GPGPU, after data or an instruction enters a cache unit in a Thread form, the Thread firstly needs to find a corresponding cache position according to a corresponding index, and after the corresponding position is found, Tag and Data are stripped, so that the cache flag bit in the GPGPU is enhanced. After stripping is completed, CRC coding and matrix storage are carried out respectively for storage and comparison; and if the error is correct, the next operation is carried out on the data, and if a problem occurs during the comparison, an error signal is pulled up, so that the flow line stops the current work, and the flow line can continue to work after the corresponding Error is repaired. Compared with the prior art, the stability of the cache unit in the GPGPU can be enhanced by enhancing the marking means of the flag bits, and then the working level of the whole GPGPU is improved.

The present invention discloses a multi-layer embedded table update method, device, equipment and medium based on a hash table. The method includes: receiving a current request instruction containing current access information sent by the current user based on a target application; determining the base address corresponding to the current access information based on a pre-stored global mapping table, and determining the target embedded entry corresponding to the current access information and the current cache level corresponding to the target embedded entry based on the base address; determining the target cache position and target cache level corresponding to the target embedded entry based on the level type of the current cache level and the preset level division rule, and updating the target embedded entry from the current cache level to the target cache position in the target cache level according to the target cache position and the target cache level. Through the technical solution of the present invention, real-time updating of the embedded table can be achieved, the memory access performance of the embedded table is improved, and the consumption of computing resources is reduced.

A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arrange

Embodiments of the present application provide a robot order-picking method, system, server and storage medium, and relate to the technical field of intelligent warehousing. The method comprises: obtaining an order-picking task of moving a target bin in a warehouse from a first storage position in a first rack to a second storage position in a second rack; determining a first cache position of the target bin according to the first storage position, and controlling a first robot to move the target bin from the first storage position to the first cache position; the first cache position belongs to a first cache area in the same column as the first rack; determining a second cache position of the target bin according to the second storage position and the first cache position, and controlling a second robot to move the target bin from the first cache position to the second cache position; the second cache position belongs to a second cache area in the same column as the second rack and in the same layer as the first cache area; and controlling a third robot to move the target bin from the second cache position to the second storage position, thereby improving order-picking efficiency.

The present application relates to the technical field of integrated circuit design, in particular to a kind of 1553B bus protocol chip's interrupt control and data packing method, comprising the following steps: in 1553B bus message transmission, interrupt event information, command word, status word, data word length, error state and cache index are collected, package description item is generated and is bound with corresponding data word, data word range and cache reading position are determined according to package description item, and then write in package queue, according to interrupt event information, error state and package queue state, interrupt arbitration is carried out, after host processor reads package description item and corresponding data word, interrupt confirmation and cache release are executed.The present application associates interrupt reason, message boundary, cache position and data word packing relationship on chip side, so that host processor reads message data according to package, and makes interrupt output, data reading and cache release keep corresponding relationship.

The present invention relates to the field of GPGPU, and specifically provides a method and device for enhancing cache mark bits in GPGPU. After data or instructions enter the cache unit in the form of Thread, Thread first needs to find the corresponding cache position according to the corresponding index. After finding the corresponding position, Tag and Data will be stripped. After stripping, they will enter their respective CRC encoding and matrix storage for storage comparison. Only when the comparison is correct will the data be processed for the next step. If there is a problem during the comparison, the error_end signal will be pulled high, so that the pipeline will suspend the current work, and the corresponding Error can be repaired before continuing to work. Compared with the prior art, the present invention can enhance the stability of the cache unit in GPGPU by enhancing the marking means of the mark bit, thereby improving the overall working level of GPGPU.