128 results about "Atomic operations" patented technology

The invention relates to a memory shader. The programmable atomic memory shader execution circuitry is a seamless component of the hierarchical memory system, and can receive and execute programmable atomic operation calls from any number of processors. Programmable atomic memory shader execution circuitry close to memory allows execution circuitry to access shader programs stored in memory, thereby eliminating latency that may occur when an upstream processor exchanges shader instructions, data, and memory lock / unlock commands with the execution circuitry. The locked / unlocked state of the programmable atomic memory shader execution circuitry (e.g., in the L2 or L3 cache memory) allows the system to quickly lock the memory resources, perform one or more operations in an atomic manner over one or more cycles, and then quickly unlock the memory resources.

The invention relates to the technical field of intelligent ship control, and particularly discloses an area control integration method and system based on an intelligent ship engine room, original operation data and multi-source communication data of equipment in each area of the engine room are collected, a unified real-time state vector is generated through protocol analysis and standardization processing, and a plurality of redundant processing nodes are processed in a unified mode. Synchronizing and verifying state data through a high-speed channel, constructing a global consistent state synchronization set, disassembling composite logic into atomic operation units with state constraints according to an upper-layer instruction and the synchronization set, packaging the atomic operation units into a private instruction sequence bound with the state, executing the instruction sequence by a main node, and executing the state synchronization set by a slave node; seamless switching to a standby node is realized through independent hardware monitoring when a fault occurs, and the standby node continuously executes based on the continuity of a state synchronization set, so that high-reliability uninterrupted operation of area control is realized; according to the method, the problems of instruction semantic distortion and single-point fault risk in heterogeneous equipment integration are solved, and the control accuracy and the intelligent level are improved.

The invention discloses a real-time data receiving and transmitting system and method based on a kernel bypass, and the method comprises the steps: processing the received data when the data receiving and transmitting system receives the data, and achieving the high-level data with complete semantics; updating a write pointer through atomic operation, and writing high-level data into a lockless annular queue in the shared memory module; the upper-layer application module reads the lock-free annular queue in the shared memory; when the data receiving and transmitting system transmits data, upper-layer data to be transmitted is transmitted to the shared memory module, and a write pointer is updated; the upper layer data in the shared memory is read in a polling or interruption mode, a read pointer is updated, the upper layer semantic data is segmented according to the format, a UDP data packet is obtained, the UDP data packet is written into a network card in the polling or interruption mode, and data sending is achieved. Through the data receiving and transmitting system disclosed by the invention, microsecond-level ultra-low delay of data certainty is realized, and efficient decoupling and stable throughput are realized.

The invention provides a database concurrency control and memory access optimization method which can be applied to the technical field of computer system software performance optimization. According to the method, multi-level instruction-level reconstruction is carried out on an execution path of a database kernel through the characteristics of an underlying hardware instruction set of a collaborative application processor platform, and the method comprises the following collaborative implementation optimization dimensions: based on a register file and a cache hierarchical structure of the processor platform, an access mode of a database core data structure is optimized; the number of memory access instructions is reduced; the data locality is improved; on the basis of atomic instruction set extension of a processor platform, instruction-level reconstruction is carried out on key primitives in a database multi-thread synchronization mechanism so as to reduce the overhead and contention of synchronization operation; on the basis of single-instruction multi-data-stream extension of a processor platform and a vector atomic operation instruction of the single-instruction multi-data-stream extension, parallel acceleration is carried out on batch life cycle management operation of objects in a database.

The invention discloses an operation automation generation method and device and a storage medium, and relates to the technical field of automatic operation, and discloses an operation automation generation method, which comprises the following steps: generating a skill model based on an operation behavior sequence of a user in a business system, the skill model comprising a plurality of atomic operations, the execution condition and the sequence dependency relationship of the atomic operation are determined; in response to the automatic execution request, obtaining a current interface of the target service system, and comparing the current interface with a historical interface associated with the corresponding atomic operation in the skill model; according to a comparison result, performing adaptive adjustment on the corresponding atomic operation in the skill model to obtain an adjusted skill model; and based on the adjusted skill model, executing automatic operation in the target business system. Through an adaptive adjustment mechanism, the automatic process can dynamically adapt to the interface change of the target business system, and the maintainability of cross-system operation automation is effectively improved.

The invention discloses a Qt4 cross compiling environment construction method and system oriented to an aarch64 architecture, and the method comprises the steps: installing a dependency library in a host machine, which comprises a dependency library used for development under a host machine architecture and a runtime dependency library in a target machine operating system, a proper cross compiling chain is installed, a libc library in a target machine is used for replacing a corresponding library in the cross compiling chain, Qt4 source codes are modified, support of atomic operation of an aarch64 architecture processor is added, compiling parameter configuration and compiling are carried out, and generated Qt4 components are installed and deployed in a host machine and the target machine respectively. According to the method, the problem of compiling and deploying a large project constructed by using Qt4 in an aarch64 architecture processor is solved, meanwhile, the programs can be debugged and compiled in a PC (Personal Computer) of a host machine architecture, a target is stacked in a target machine of the aarch64 architecture to run, and great convenience is provided for debugging and running of the programs.

The invention relates to a distributed file system recycle bin performance optimization method, which comprises the following steps: in the execution process of an unlink interface of a Linux file system, sequentially completing recycle bin function starting judgment, file deletability verification and recycle bin storage suitability judgment, and obtaining metadata of a target deleted file parent directory from a server; when a file system is created, a global unified root recycle bin directory is synchronously generated, and when a file is deleted, a corresponding recycle bin subdirectory is created in a target MDS based on a parent directory inode number; an atomic operation is executed through a Linux standard rename interface, the file is moved to a corresponding recycle bin subdirectory, and the operation is limited to the interior of a single MDS; when the file is recovered, extracting an inode number of a parent directory, and iteratively querying metadata to restore an original complete path; and during batch recovery, if the original catalogue does not exist or needs to be recovered to a new catalogue, directly and integrally moving the catalogue corresponding to the recycle bin, otherwise, executing recovery operation one by one. The file deletion and recovery performance is remarkably improved, the resource overhead is reduced, and the data consistency is guaranteed.

The invention relates to the field of computer software and information system engineering, in particular to a multi-account asynchronous bookkeeping data consistency collaboration system based on instruction driving, which comprises the following steps of: packaging a request into a standard instruction and routing according to an account to ensure ordered processing of the request and improve the processing efficiency and expandability of the system; repeated requests are avoided through idempotent verification, business is mapped into atomic operation through rule analysis, and the accuracy of business logic and data consistency are guaranteed; atomic operation is executed in a single transaction, asynchronous retry is performed during conflict, the atomicity of cross-account operation is ensured, and the concurrent processing capacity is improved; by buffering high-frequency account change and batch aggregation updating, write conflicts are reduced, the system performance is stabilized, and the throughput is improved; through account checking based on daily switching snapshots, pipeline playback and reverse account flushing are supported, and a rapid repair capability is provided; through dynamic configuration and versioned management of the bookkeeping rule, visual monitoring is provided, the operation and maintenance complexity is reduced, and the system flexibility is enhanced.

The invention relates to an end-to-end process construction and execution method and related equipment based on a standardized component, and the method comprises the steps: obtaining the process design data of an end-to-end process project of a power enterprise, which comprises a value stage, a key business activity, an atomic operation sequence, an operation main body and an output object; packaging the atomic operation into a standardized component, configuring an execution role for the standardized component, reserving an element slot, and storing the element slot into a process component library; responding to the arrangement instruction, selecting a plurality of components corresponding to the target business scene from a component library, establishing control flow logic among the components, generating an end-to-end process model, and establishing a metadata association relationship between each component and an execution role, a digital system, a business rule, a business form and a system standard; and associating and deploying the model and the metadata to a process execution platform. According to the method, the construction efficiency, the component reusability and the executable performance of the end-to-end process are improved.

The invention relates to the technical field of PLC control, in particular to a PLC communication expansion system and method supporting modular dynamic reconfiguration, and the system adopts a physically isolated biplane bus architecture, and comprises a process interaction unit for maintaining a deterministic interpolation period containing a preset fixed bit wide shadow time slot, the configuration management unit is used for acquiring parameters through an independent serial bus, the motion resolving unit verifies data suitability and loads drive in the background, meanwhile, coordinate system zero point offset vectors of new and old models are resolved in parallel based on real-time position feedback, the undisturbed switching unit responds to a ready signal, atomic operation is executed in an inter-frame protection gap, and a new and old model is obtained. The shadow time slot is mapped to the new module, and the offset vector is used as a feedforward injection motion instruction. According to the invention, zero-jitter undisturbed dynamic reconstruction is realized through dual-plane and atom switching.

The application provides a CAN frame data transmission method and device, equipment and a storage medium, relates to the technical field of data communication, solves the problem of system throughput decline and low network transmission efficiency of CAN frame data transmission in a high concurrency scene in the related art, the scheme realizes the atomic operation of quasi-lock-free through the construction of three buffer zone architecture and the separation of the lock mechanism, and the reduction of lock competition based on the separation mechanism of each buffer zone, which can maintain high throughput and low lock waiting time in different load scenarios, so that the system can respond in real time, and still meet the real-time requirements in the high concurrency and large data industrial application scene, and effectively improve the network transmission efficiency.

The application discloses a kind of high concurrency time series data processing method and device for anti-UAV system.The application uses lock-free hash table to cache time series data in cache space, lock-free cache design and CAS atomic operation reduce lock overhead, batch write throughput is high, conflict probability is low, support multi-thread high concurrency read-write, completely eliminate thread competition and blocking caused by traditional cache mechanism, improve concurrent processing capability;At the same time, batch write reduces the overhead of dynamic memory allocation, improves memory utilization;Through composite key fast positioning, hot data index structure priority query and lock-free reading mechanism, the query delay of hot data is extremely low, data preloading mechanism further reduces the delay of future related query, improves real-time response capability;Based on the dynamic elimination mechanism of elimination score, hot data / recent data can be preferentially retained, ensure resource utilization, significantly improve cache hit rate, greatly reduce access frequency to TSDB.

This application discloses an information processing method, apparatus, device, storage medium, and computer program. The method includes: when a collaborative document in a first state contains a first atomic operation and a second atomic operation, obtaining the tree structure corresponding to the collaborative document; updating the collaborative document from the first state to a second state based on the tree structure according to the operation intent expressed by the first atomic operation; wherein the first atomic operation includes a first type of operation among N predefined atomic operations in the tree structure, and the first type of operation is an operation that can be split into two or more atomic operations; performing intent restoration transformation on the operation intent expressed by the second atomic operation according to the operation intent expressed by the first atomic operation to obtain a transformed operation intent; and updating the collaborative document from the second state to a third state based on the tree structure according to the transformed operation intent. Using this application embodiment can improve the accuracy of conflict handling.

The invention discloses a concurrent data processing method and a related device, and the method comprises the steps: responding to a deletion request for an original data record in a memory stable region, and enabling an Owner Entity to use a write instruction of a preset mechanism to carry out the state marking of whether the original data record is in a deletion state or not on the original data record; the Sharing Entity reads the original data record in the memory stable region by using a read instruction of a preset mechanism, and the read original data record is preprocessed and then sent to the Owner Entity; and the Owner Entity finds out an original data record corresponding to each preprocessed data record in the memory stable area according to the data record identifier, and rechecks a state marking result of the found original data record. Wherein the read-write instruction does not use any synchronous primitive, atomic operation and the like according to a preset mechanism, so that the cache consistency flow generated by the read operation can be avoided from the source, the problems of pipeline pause and blockage on a read-write path are eliminated, and the business processing efficiency and the data synchronous updating effect are improved.

The invention relates to a program analysis method and device, electronic equipment, a storage medium and a computer program product, and the method comprises the steps that before a target program runs, a sampling buffer area is allocated to the target program, and the sampling buffer area comprises sampling buffer partitions allocated for each instruction in the target program; when any sampling moment is reached in the running process of the target program, instruction counter sampling is carried out, a sampling instruction of this time is determined, and a sampling counter in a target sampling buffer partition corresponding to the sampling instruction of this time is updated through atomic operation; after the operation of the target program is finished, determining the total sampling frequency of each instruction in the target program according to the sampling buffer area; and according to the total sampling frequency of each instruction in the target program, performing performance analysis on the target program to obtain a performance analysis result. According to the embodiment of the invention, the operation of the target program is not influenced under the condition that the sampling precision is ensured, and the performance analysis of the target program is effectively realized.

The invention discloses a software and hardware collaborative RDMA atomic operation acceleration method, which comprises the following steps: dynamically collecting and reporting atomic operation target address popularity through a client, and dynamically formulating a table locking slot scheduling strategy by a server in combination with a CPU load according to the popularity so as to realize a fine-grained unloading decision; the client carries out real-time scheduling according to a strategy; a low-heat slot is executed by a network card hardware atomic instruction, and a high-heat slot is redirected to an RPC to be processed by a server CPU; the switching process depends on a client side consensus and a global consensus; and the RPC thread of the server side verifies the strategy identifier and the consensus state before execution, and rejects an inconsistent request. According to the method, performance optimization of RDMA atomic operation is realized through heat perception, dynamic scheduling, network card and CPU collaborative execution and a two-stage consensus mechanism.

A processor executes an instruction to perform a comparison between a source value and a value stored in memory at a specified address. If the comparison passes, the processor writes the source value to memory at the specified address and writes a payload to a payload destination address in an atomic operation. The instruction includes an opcode indicating the comparison and fields specifying the source value, addresses, and payload. The payload may have arbitrary length. A Test-And-Update (TAU) operation associates the payload with the atomic operation while maintaining native bit-width for the comparison. This enables efficient handling of larger payloads without compromising performance of existing comparison logic, providing enhanced functionality for graphics and general-purpose computing applications.

The invention provides an API service orchestration method and device, equipment, a medium and a product, and the method comprises the steps: obtaining a demand text which reflects an API service orchestration demand of a user; the demand text is input into an intention recognition model, at least one atomic operation entity output by the intention recognition model is obtained, and the atomic operation entity comprises an operation intention and operation parameters; based on the atomic operation entities, retrieval is conducted in the API information knowledge base, at least one candidate API set is obtained, and each candidate API set corresponds to one atomic operation entity; at least one API calling chain is constructed on the basis of the dependency relationship between the APIs in the candidate API set, and the API calling chain comprises API information of the multiple APIs and calling sequence constraints between the APIs; and determining at least one API orchestration result based on the API call chain and the demand text. According to the invention, the operation burden of a user in API service orchestration can be reduced.

The invention relates to an interrupt controller isolation access control method based on a virtual machine monitor, and the method comprises the steps: analyzing an access instruction of a virtual machine to an interrupt controller, so as to obtain an operation attribute and a target address; querying a predefined mapping relationship based on the virtual machine identifier, the processor core information and the target address, and generating an interrupt nucleophilicity parameter; dynamically generating a register operation mask according to the interrupt nucleophilicity parameter and interrupt register configuration information corresponding to the target address; verifying the access authority of the virtual machine to the target address based on the register operation mask; and in response to the fact that the access permission passes the verification, executing the access of the access instruction to the interrupt controller in an atomic operation mode by applying the register operation mask.

The control method for the automation process comprises: acquiring a task operation instruction in the automation process (S110); performing task deduction on a corresponding task operation according to parameters in the task operation instruction to obtain a task deduction result, wherein the task deduction result comprises execution parameters of a plurality of atomic operations in the task operation (S120); and according to the task deduction result, determining whether to execute the task operation (S130). According to the control method for the automation process, before the task operation instruction is executed, task deduction can be performed on the task operation instruction firstly, the task operation is then executed according to the task deduction result, and a complex task operation is split into a plurality of simple atomic operations according to the task deduction, such that the automation process is clearer.

The invention provides a parasitic parameter extraction method and system for Socket interface multi-task coordination, and belongs to the technical field of parasitic parameter extraction. The method comprises the following steps: acquiring and analyzing an initial configuration file, and creating a read-write lock mechanism of a process pool and a global task coordination table; establishing non-blocking transmission control protocol monitoring, and mapping a Socket connection handle established by the sub-process and the host process to a global task coordination table; executing parasitic parameter extraction by utilizing the screened sub-processes, and generating a parasitic parameter result data packet after the extraction is completed; and performing Hash abstract verification, and if the Hash abstract verification is passed, marking the task corresponding to the parasitic parameter result data packet as completion and recording the extracted parasitic parameter. According to the method, a traditional file synchronization mechanism is replaced based on non-blocking Socket communication and an event-driven model, so that the inter-process communication efficiency is remarkably improved; and by adopting read-write lock hierarchical control and atomic operation, the utilization rate of hardware resources is effectively improved.

This invention discloses an AI inference resource decoupling scheduling method and system based on a two-dimensional orthogonal state space. User AI service rights are decomposed into storage rights dimension σ and computing power rights dimension φ, constructing an orthogonal state space S=(σ,φ), where σ and φ change independently and have no causal dependency. Four service modes are derived from the state space: full service, read-only memory, temporary session, and guided recovery. State transitions in the computing power rights dimension are triggered by critical conditions of discrete quota counting: the cost r for a single token generation is defined as the lower limit of physical resources required for a single forward propagation of the model decoder. When the remaining quota Q(t) is less than r, the physical system cannot complete the next calculation, and the state will inevitably transition and terminate the computation flow. State switching is achieved through metadata-level atomic operations, and the execution time is independent of the user data scale. This invention clarifies the inevitability of the technical effect through logical deduction, is applicable to software or hardware-software co-implementation, and solves the problems of resource deadlock, switching latency, and service interruption under subscription systems.

The requesting device of the present invention is capable of transmitting multiple prompt messages simultaneously, and enables the responding device to optimize various aspects through memory prefetching, cache warming, and multiple atomic operations. These operations are used to enable the responding device to begin prefetching memory regions in advance (if necessary), or to prepare to receive incoming data packets in an efficient manner.

The application discloses a configurable read-write priority strategy read-write lock implementation method of an MMU-free embedded real-time operating system, and comprises the following steps: S1, performing strategy binding in a read-write lock creation stage; S2, realizing atomic operation in a middle-off mode; S3, actively eliminating writer starvation in a write priority mode; S4, performing priority inheritance when a write lock is applied; S5, adopting a double-waiting queue separation design; S6, adopting static memory pool zero dynamic allocation; and S7, adopting single-field tri-state encoding to mark a lock state. The configurable read-write priority strategy read-write lock implementation method of the MMU-free embedded real-time operating system realizes lightweight configurable read-write locks of the MMU-free embedded real-time operating system, can support flexible configuration of read / write priority strategies and has zero runtime switching overhead in the whole process, does not need special hardware instructions and MMU context support, and is perfectly compatible with low-end MCUs without exclusive access capability, such as Cortex-M0 / M0+.

The invention relates to a kernel-level lock-free bounded MPMC queue structure, a data processing method, electronic equipment and a storage medium, which are used for reducing tail delay and improving the portability of a queue. The MPMC queue structure can run in hardware which does not support double-word atomic operation or in hardware which supports double-word atomic operation; the MPMC queue structure comprises an annular buffer area; the annular buffer area is composed of a plurality of grooves, and each groove stores a groove serial number and data information; the slot serial number is used for being matched with a reading position / writing position to verify the reading and writing authority, and the reading position / writing position is obtained based on a global index and through single-word atomic operation; if the MPMC queue structure runs in hardware which does not support double-word atomic operation, the slot serial number follows a first slot serial number rule; if the MPMC queue structure runs in hardware supporting double-word atomic operation, the slot serial number follows a second slot serial number rule; and the queue capacity of the annular buffer area is integer power of 2.

The application relates to a virtual resource state synchronization control method and device, equipment and a medium, the method comprising: in response to a service instruction for synchronizing the state of a target user's virtual resource, generating a global transaction identifier and an associated transaction context; based on the cross-application shared virtual resource information of the target user, determining an operation sequence composed of atomic operations corresponding to at least two different virtual resources specified by the service instruction; sequentially executing each atomic operation using the transaction context, and before executing any atomic operation, registering corresponding reverse operation information in the transaction context according to a corresponding preset reverse operation executor and execution parameter; and updating corresponding state records in the global state snapshot of the target user according to the execution result of the operation sequence, the global state snapshot being used to provide a unified query interface for the execution result for different applications. The application can guarantee strong consistency and global observability of cross-application virtual resource state synchronization.

The invention provides a data operation authority management and control method and device, electronic equipment and a storage medium. The method comprises the steps of obtaining a function tag matched with a to-be-operated object; splitting the function label into a plurality of atomic operation permissions, and performing permission hydration on the plurality of atomic operation permissions, a first baseline permission of the data model and a second baseline permission of the metadata according to a preset permission hydration strategy to obtain a final snapshot of the atomic operation permissions; serializing, signing and compressing the snapshots through a rear end to generate a model-level token and an instance-level token; sending the snapshot, the model-level token and the instance-level token to a front end, determining a token corresponding to the target operation, and sending the token to a rear end for verification; and under the condition that the token is successfully verified, performing interface rendering on the user interface according to the target data model and the execution operation result of the target instance. The operation and maintenance cost of authority management can be reduced, the validity of authority management is improved, and front-end and back-end integration is realized.

The invention provides a heterogeneous computing system, a server and a heterogeneous computing method. The system comprises a server and a computing device, the server and the computing device share a data queue, and a shadow variable is arranged in the server; the server comprises n threads; when K threads in the n threads concurrently add messages to the data queue, the K threads are configured as follows: the K threads seize shadow variables through atomic operation respectively, when any one thread in the K threads successfully seize the shadow variables through the atomic operation, the shadow variables are updated, and when the shadow variables are not successfully seized through the atomic operation, the shadow variables are updated; the thread which successfully preempts the shadow variable can write the message into a sequence queue, and after the message is written into the data queue, the value of a write pointer of the data queue is updated according to the updated shadow variable; a thread in a computing device is configured to read a message from a data queue for processing, and after reading the message, update a value of a read pointer of the data queue. The performance of the heterogeneous computing system can be improved.

The invention provides an SQL (Structured Query Language) generation method and system for complex query, electronic equipment and a program product. The method comprises the steps that a natural language query request is received, and the complexity of the natural language query request is evaluated; if the complexity is higher than a preset threshold value, disassembling the natural language query request into a plurality of atomic operations; aiming at each atomic operation, generating a corresponding SQL (Structured Query Language) fragment; performing dynamic verification on each SQL fragment; and in response to the fact that all the SQL fragments pass the verification, integrating the SQL fragments into a complete SQL statement and executing the complete SQL statement.

Embodiments of the present application provide a processing method, device and apparatus of atomic operation, and a storage medium. In the embodiments of the present application, when a memory exclusive event occurs in a computing device, a target memory address corresponding to the memory exclusive event is located, and in a case where the memory exclusive event occurring at the target memory address satisfies a triggering condition, a cache corresponding to the target memory address is dynamically closed to guide an atomic operation carried by the target memory address to directly access the memory instead of via the cache. In this way, the atomic operation carried by the target memory address can read and write the required data through the memory, which ensures the normal execution of the atomic operation, and since the atomic operation that may cause the memory exclusive event is guided to the memory and no longer accesses the cache, the memory exclusive event caused by the atomic operation accessing the cache can be effectively alleviated.