175 results about "Atomic operations" patented technology

The invention belongs to the field of parallel computing architecture optimization, and relates to a matrix multiplication acceleration method and system based on dynamic computing resource mapping, and the method comprises the steps: constructing a dynamic topology model driven by tensor dimension features, and generating a thread block distribution mode according to matrix parameters and GPU hardware information; constructing a multi-dimensional resource scheduling strategy library, dynamically selecting an optimal thread block distribution strategy from the multi-dimensional resource scheduling strategy library, and generating a binding relationship between the thread blocks and the data blocks; calculating collaborative access logic of thread blocks and storage hierarchies based on block parameters and dynamic mapping function optimization; distributed calculation is carried out, calculation and data transmission are parallelized through pipelining and a double-buffering mechanism, and result aggregation across calculation units is completed synchronously through atomic operation and a barrier. According to the method, discontinuous memory access conflicts can be effectively reduced, the execution efficiency of the calculation instruction and the utilization rate of the cache space are improved, the parallel calculation process of accelerating and optimizing the general matrix multiplication is realized, and the data processing efficiency is improved.

The invention relates to a long-range task-oriented VLA model method for a humanoid robot, which comprises the following steps of: S01, analyzing a natural language instruction through a space-time semantic analyzer to generate an atomic operation sequence with a space-time dependency relationship; s02, maintaining a task state machine by using a dynamic memory network, and tracking the task execution progress in real time; s03, integrating vision, language and sensor data through a multi-modal perception fusion engine; s04, calling a predefined action primitive based on an adaptive execution system and optimizing a motion track; and S05, performing online updating and optimization on the model through a continuous learning mechanism. According to the method, a natural language instruction is analyzed into a structured task sequence with space-time dependence through a space-time semantic analyzer, an execution sequence and preconditions are defined, the semantic understanding ability and the structuring degree of task planning are improved, and task decomposition and replanning in a dynamic environment are supported; according to the method, the LSTM and the knowledge graph are combined, and the task state is maintained in real time.

The invention provides a multi-modal basic model convolution operation optimization framework method suitable for a GPU / DCU. The method is used for solving the technical problems that the optimization process of an existing convolution operator optimization method is time-consuming and cross-layer operator fusion is difficult to capture. The method comprises the following steps: receiving a convolution operator through a parameterized input interface; collecting shape features of each convolution operator in the structured parameter set by using a shape analyzer to realize convolution feature analysis; judging whether batch normalization and nonlinear activation function fusion calculation is started or not; a heuristic optimizer dynamically selects a calculation graph optimization strategy based on convolution parameter characteristics; a calculation task is adapted to a physical architecture of the GPU / DCU, so that hardware resources are utilized to the maximum extent; a convolution calculation kernel function oriented to DCU / GPU architecture optimization is generated based on the convolution parameter features; kernel function assembly line execution is achieved through a DCU / GPU hardware task queue; gradient synchronization among multiple computing units is realized by adopting atomic operation at an equipment end. According to the method, the execution efficiency of the convolution operation in the multi-modal basic model can be remarkably improved.

The invention discloses a concurrency control method and device, electronic equipment, a storage medium and a product. The method is applied to a concurrency control system comprising a processor and a bus controller, and comprises the steps that the processor responds to an atomic operation request of a target thread and sequentially sends a storage area switching instruction and a register operation instruction to the bus controller; the bus controller responds to the storage area switching instruction and the register operation instruction, executes storage area switching operation, generates a bus occupation maintaining signal and continuously executes register read-write operation in a target storage area; the processor sends a scheduling request to an operating system, so that the operating system improves the priority of the target thread to be a first priority; and the bus controller generates a bus release signal after the atomic operation of the target thread is finished. According to the scheme, through cooperation of the processor and the bus controller, atomized execution of thread Bank switching and register reading and writing is achieved, and the concurrency performance is improved while the reliability and consistency of data are ensured.

The invention relates to a memory shader. The programmable atomic memory shader execution circuitry is a seamless component of the hierarchical memory system, and can receive and execute programmable atomic operation calls from any number of processors. Programmable atomic memory shader execution circuitry close to memory allows execution circuitry to access shader programs stored in memory, thereby eliminating latency that may occur when an upstream processor exchanges shader instructions, data, and memory lock / unlock commands with the execution circuitry. The locked / unlocked state of the programmable atomic memory shader execution circuitry (e.g., in the L2 or L3 cache memory) allows the system to quickly lock the memory resources, perform one or more operations in an atomic manner over one or more cycles, and then quickly unlock the memory resources.

The invention relates to the technical field of intelligent ship control, and particularly discloses an area control integration method and system based on an intelligent ship engine room, original operation data and multi-source communication data of equipment in each area of the engine room are collected, a unified real-time state vector is generated through protocol analysis and standardization processing, and a plurality of redundant processing nodes are processed in a unified mode. Synchronizing and verifying state data through a high-speed channel, constructing a global consistent state synchronization set, disassembling composite logic into atomic operation units with state constraints according to an upper-layer instruction and the synchronization set, packaging the atomic operation units into a private instruction sequence bound with the state, executing the instruction sequence by a main node, and executing the state synchronization set by a slave node; seamless switching to a standby node is realized through independent hardware monitoring when a fault occurs, and the standby node continuously executes based on the continuity of a state synchronization set, so that high-reliability uninterrupted operation of area control is realized; according to the method, the problems of instruction semantic distortion and single-point fault risk in heterogeneous equipment integration are solved, and the control accuracy and the intelligent level are improved.

The invention discloses a real-time data receiving and transmitting system and method based on a kernel bypass, and the method comprises the steps: processing the received data when the data receiving and transmitting system receives the data, and achieving the high-level data with complete semantics; updating a write pointer through atomic operation, and writing high-level data into a lockless annular queue in the shared memory module; the upper-layer application module reads the lock-free annular queue in the shared memory; when the data receiving and transmitting system transmits data, upper-layer data to be transmitted is transmitted to the shared memory module, and a write pointer is updated; the upper layer data in the shared memory is read in a polling or interruption mode, a read pointer is updated, the upper layer semantic data is segmented according to the format, a UDP data packet is obtained, the UDP data packet is written into a network card in the polling or interruption mode, and data sending is achieved. Through the data receiving and transmitting system disclosed by the invention, microsecond-level ultra-low delay of data certainty is realized, and efficient decoupling and stable throughput are realized.

The invention provides a CAN (Controller Area Network) frame data transmission method and device, equipment and a storage medium, relates to the technical field of data communication, and solves the problems that the system throughput is reduced and the network transmission efficiency is low when CAN frame data transmission is performed in a high-concurrency scene in related technologies. And the quasi-lock-free atomization operation is realized through buffer area exchange, and the lock competition condition is reduced based on the separation mechanism of each buffer area, so that high throughput and lower lock waiting time can be kept in different load scenes, the system can respond in real time, and the system performance is improved. The real-time requirement can still be met in a high-concurrency and large-data-volume industrial application scene, and the network transmission efficiency is effectively improved.

Systems and methods are provided to improve the memory throughput for storing and reading intermediate data computed by layers of a neural network during a training process. A compression operation can be performed by removing the zeros from the intermediate data and storing locations of the zeros before storing the intermediate data in the memory for a forward pass of the training process. The compressed data can be read from the memory for a backward pass of the training process and de-compressed by inserting zeros based on the stored locations. Additionally, a transpose operation can be performed before compression as a first atomic operation, or after de-compression as a second atomic operation.

The invention provides a database concurrency control and memory access optimization method which can be applied to the technical field of computer system software performance optimization. According to the method, multi-level instruction-level reconstruction is carried out on an execution path of a database kernel through the characteristics of an underlying hardware instruction set of a collaborative application processor platform, and the method comprises the following collaborative implementation optimization dimensions: based on a register file and a cache hierarchical structure of the processor platform, an access mode of a database core data structure is optimized; the number of memory access instructions is reduced; the data locality is improved; on the basis of atomic instruction set extension of a processor platform, instruction-level reconstruction is carried out on key primitives in a database multi-thread synchronization mechanism so as to reduce the overhead and contention of synchronization operation; on the basis of single-instruction multi-data-stream extension of a processor platform and a vector atomic operation instruction of the single-instruction multi-data-stream extension, parallel acceleration is carried out on batch life cycle management operation of objects in a database.

The invention discloses an operation automation generation method and device and a storage medium, and relates to the technical field of automatic operation, and discloses an operation automation generation method, which comprises the following steps: generating a skill model based on an operation behavior sequence of a user in a business system, the skill model comprising a plurality of atomic operations, the execution condition and the sequence dependency relationship of the atomic operation are determined; in response to the automatic execution request, obtaining a current interface of the target service system, and comparing the current interface with a historical interface associated with the corresponding atomic operation in the skill model; according to a comparison result, performing adaptive adjustment on the corresponding atomic operation in the skill model to obtain an adjusted skill model; and based on the adjusted skill model, executing automatic operation in the target business system. Through an adaptive adjustment mechanism, the automatic process can dynamically adapt to the interface change of the target business system, and the maintainability of cross-system operation automation is effectively improved.

The invention discloses a Qt4 cross compiling environment construction method and system oriented to an aarch64 architecture, and the method comprises the steps: installing a dependency library in a host machine, which comprises a dependency library used for development under a host machine architecture and a runtime dependency library in a target machine operating system, a proper cross compiling chain is installed, a libc library in a target machine is used for replacing a corresponding library in the cross compiling chain, Qt4 source codes are modified, support of atomic operation of an aarch64 architecture processor is added, compiling parameter configuration and compiling are carried out, and generated Qt4 components are installed and deployed in a host machine and the target machine respectively. According to the method, the problem of compiling and deploying a large project constructed by using Qt4 in an aarch64 architecture processor is solved, meanwhile, the programs can be debugged and compiled in a PC (Personal Computer) of a host machine architecture, a target is stacked in a target machine of the aarch64 architecture to run, and great convenience is provided for debugging and running of the programs.

The invention relates to a distributed file system recycle bin performance optimization method, which comprises the following steps: in the execution process of an unlink interface of a Linux file system, sequentially completing recycle bin function starting judgment, file deletability verification and recycle bin storage suitability judgment, and obtaining metadata of a target deleted file parent directory from a server; when a file system is created, a global unified root recycle bin directory is synchronously generated, and when a file is deleted, a corresponding recycle bin subdirectory is created in a target MDS based on a parent directory inode number; an atomic operation is executed through a Linux standard rename interface, the file is moved to a corresponding recycle bin subdirectory, and the operation is limited to the interior of a single MDS; when the file is recovered, extracting an inode number of a parent directory, and iteratively querying metadata to restore an original complete path; and during batch recovery, if the original catalogue does not exist or needs to be recovered to a new catalogue, directly and integrally moving the catalogue corresponding to the recycle bin, otherwise, executing recovery operation one by one. The file deletion and recovery performance is remarkably improved, the resource overhead is reduced, and the data consistency is guaranteed.

The invention belongs to the technical field of cloud computing heterogeneous resource scheduling, and particularly provides a multi-architecture virtualization environment integration and unified operation and maintenance method and system, and the method comprises the steps: detecting the underlying hardware characteristics of a source architecture and a target architecture; generating a hardware semantic abstract model based on the underlying hardware characteristics; carrying out compatibility analysis on the cross-architecture virtual machine instruction stream, and identifying atomic operation semantic conflicts and interrupt routing logic conflicts; generating an instruction translation rule and a micro-architecture cleaning strategy; converting an instruction stream and cleaning a branch predictor of a source architecture and a residual state of an out-of-order execution buffer area; and synchronizing the cleaned micro-architecture state and the conversion instruction stream to the target virtual machine. According to the method and the system, instruction stream conversion in a virtual machine migration process can be dynamically matched with micro-architecture characteristics of a target architecture, seamless connection of execution environments in a cross-architecture migration process is realized, cross-architecture conflicts can be prevented, and the problems of migration conflicts and performance degradation of the virtual machine of a virtualization platform are solved.

The invention relates to the technical field of computer software and system performance optimization, in particular to a high-performance software operation log storage method and device. The high-performance software operation log storage method comprises the following steps: monitoring an available memory of a system and a resource state of a concurrent thread number in real time; dynamically initializing parameters of a lockless ring buffer based on the resource state; concurrently writing log information generated by a service thread into the lockless annular buffer area through atomic operation; before or after the log information is written into the lock-free annular buffer area, multi-dimensional filtering based on keywords, date ranges and log levels is conducted on the log information through an intelligent log filtering engine; and through a self-adaptive file management subsystem, writing the log data output by the lock-free annular buffer into a log file, and dynamically managing rotation and archiving of the log file according to a system storage space state.

The invention provides a business instruction processing method, relates to the field of big data, and can be applied to the field of financial science and technology or other fields. The service instruction processing method comprises the following steps: receiving a service instruction; identifying the type of the service instruction; analyzing the business instruction according to the identified type, and extracting key business elements; determining an execution path of the service instruction based on the key service elements and the current decision parameters; disassembling the business instruction into a plurality of atomic operations; processing the plurality of atomic operations in parallel based on the execution path to obtain a processing result of the service instruction; wherein a transaction compensation mechanism is adopted in the process of parallel processing of the multiple atomic operations to ensure the final consistency of the operations; and feeding back a processing state based on a processing result of the service instruction. The invention further provides a service instruction processing device and equipment, a storage medium and a program product.

The invention relates to the field of computer software and information system engineering, in particular to a multi-account asynchronous bookkeeping data consistency collaboration system based on instruction driving, which comprises the following steps of: packaging a request into a standard instruction and routing according to an account to ensure ordered processing of the request and improve the processing efficiency and expandability of the system; repeated requests are avoided through idempotent verification, business is mapped into atomic operation through rule analysis, and the accuracy of business logic and data consistency are guaranteed; atomic operation is executed in a single transaction, asynchronous retry is performed during conflict, the atomicity of cross-account operation is ensured, and the concurrent processing capacity is improved; by buffering high-frequency account change and batch aggregation updating, write conflicts are reduced, the system performance is stabilized, and the throughput is improved; through account checking based on daily switching snapshots, pipeline playback and reverse account flushing are supported, and a rapid repair capability is provided; through dynamic configuration and versioned management of the bookkeeping rule, visual monitoring is provided, the operation and maintenance complexity is reduced, and the system flexibility is enhanced.

The invention relates to an end-to-end process construction and execution method and related equipment based on a standardized component, and the method comprises the steps: obtaining the process design data of an end-to-end process project of a power enterprise, which comprises a value stage, a key business activity, an atomic operation sequence, an operation main body and an output object; packaging the atomic operation into a standardized component, configuring an execution role for the standardized component, reserving an element slot, and storing the element slot into a process component library; responding to the arrangement instruction, selecting a plurality of components corresponding to the target business scene from a component library, establishing control flow logic among the components, generating an end-to-end process model, and establishing a metadata association relationship between each component and an execution role, a digital system, a business rule, a business form and a system standard; and associating and deploying the model and the metadata to a process execution platform. According to the method, the construction efficiency, the component reusability and the executable performance of the end-to-end process are improved.

Systems and methods for an eBPF general allocator for an eBPF program is provided. The method includes receiving, by a first eBPF program, a first entry based on an atomic operation. The first entry is from a number of entries in a free list that indicates available space in a buffer. The available space is indexed by the number of entries in the free list. The method further includes identifying, based on the first entry, a pointer to the buffer. The pointer is associated with an allocation of the available space in the buffer based on the first entry. The allocation of the available space is to the first eBPF program. The method further includes executing, by a processing device, the first eBPF program with exclusive access to the allocation of the available space in the buffer during an execution instance of the first eBPF program.

The invention discloses a high-concurrency time series data processing method and device for an anti-unmanned aerial vehicle system. According to the method, a lock-free hash table is adopted in a cache space to cache time sequence data, lock overhead is reduced through lock-free cache design and CAS atomic operation, the batch writing throughput is high, the conflict probability is low, multi-thread high-concurrency reading and writing are supported, thread competition and blocking caused by a traditional cache mechanism are thoroughly eliminated, and the concurrent processing capacity is improved; meanwhile, the expenditure of dynamic memory allocation is reduced through batch writing, and the memory utilization rate is increased; through quick positioning of a compound key, priority query of a hotspot data index structure and a lock-free reading mechanism, the query delay of hotspot data is extremely low, the delay of related query in the future is further reduced through a data preloading mechanism, and the real-time response capability is improved; based on a dynamic elimination mechanism of an elimination score, hotspot / recent data can be reserved preferentially, the resource utilization rate is ensured, the cache hit rate is remarkably improved, and the access frequency of the TSDB is greatly reduced.

The invention relates to a Redis-based asynchronous task security scheduling method and system, and the method comprises the steps: creating an asynchronous task, and storing the asynchronous task to a task queue for scheduling; scheduling the asynchronous tasks through atomic operation executed by the script, preferentially acquiring the overtime asynchronous tasks from the task execution set, or popping up the asynchronous tasks to be executed from the task queue, and recording the acquired asynchronous tasks to the task execution set to track a scheduling state; prolonging the maximum execution time of the asynchronous task by updating the expiration time of the asynchronous task in the task execution set; and after the asynchronous task is completed or failed, deleting the asynchronous task from the task execution set. Compared with the prior art, the scheme has the advantages that the task scheduling stability in a high-concurrency scene is remarkably improved, the task loss risk is reduced, non-blocking access and dynamic scheduling are supported, the scheme is suitable for high-reliability systems such as financial systems and industrial control systems, the system performance is optimized, and the implementation complexity is simplified.

The invention relates to the technical field of PLC control, in particular to a PLC communication expansion system and method supporting modular dynamic reconfiguration, and the system adopts a physically isolated biplane bus architecture, and comprises a process interaction unit for maintaining a deterministic interpolation period containing a preset fixed bit wide shadow time slot, the configuration management unit is used for acquiring parameters through an independent serial bus, the motion resolving unit verifies data suitability and loads drive in the background, meanwhile, coordinate system zero point offset vectors of new and old models are resolved in parallel based on real-time position feedback, the undisturbed switching unit responds to a ready signal, atomic operation is executed in an inter-frame protection gap, and a new and old model is obtained. The shadow time slot is mapped to the new module, and the offset vector is used as a feedforward injection motion instruction. According to the invention, zero-jitter undisturbed dynamic reconstruction is realized through dual-plane and atom switching.

The invention provides a cache consistency processing method and device, equipment and a storage medium, and the method comprises the steps: when a write operation or an atomic operation is carried out on a first copy in any first last-stage cache, forwarding the write operation or the atomic operation to a second last-stage cache, discarding the first copy in the first last-stage cache of the first copy, and storing the first copy in the second last-stage cache of the first copy; and performing write operation or atomic operation on the second copy in the second last-stage cache to obtain a processed second copy. In the technical scheme, write operations or atomic operations in other last-stage caches are all forwarded to the last-stage caches corresponding to the corresponding high-bandwidth memories, so that the last-stage caches are subjected to unilateral operations or atomic operations, tedious consistency steps in the prior art are avoided, the protocol and hardware implementation complexity is greatly simplified, and the implementation efficiency is improved. Therefore, the performance optimization is realized.

An apparatus comprises decoding circuitry to decode a compare-and-conditional-add command identifying a target address, compare data value, and addend data value. Processing circuitry is responsive to the compare-and-conditional-add command to trigger an atomic set of operations to: read a target data value from a storage location corresponding to the target address, and selectively write an updated data value to the storage location in dependence on whether the compare data value satisfies a comparison condition with respect to the target data value. The updated data value comprises a result of an addition of the target data value and the addend data value performed in response to the compare-and-conditional-add command. A comparison condition outcome indication is provided indicating whether the compare data value satisfied the comparison condition. The comparison condition outcome indication comprises at least one of the target data value and the updated data value.

The application discloses a big data legal supervision model atomic operation and assembly method, comprising: an atomic operation layer, which is used for realizing basic functions in a legal supervision process; a supervision model layer, which comprises a plurality of legal supervision models for different supervision targets; and an early warning push layer, which is used for sending early warning information. The application defines preconditions and postconditions of atomic operations, uses predicate logic to establish logical relationships between the atomic operations, and further constructs a complete legal supervision model. This method based on predicate logic makes the model have certain interpretability, and dynamic assembly of the atomic operations enhances flexibility and generalization of the model. The application uses formalization description capability of the predicate logic to establish logical correlations between legal thresholds, behaviors of supervision objects and supervision targets, realizes fine analysis and dynamic evaluation of the behaviors of the supervision objects, and displays visualization of an atomic operation path of reachable supervision targets.

The invention discloses an intelligent refreshing method, system and device for a Cocos Creator page and a medium. The method specifically comprises the steps that a file system change event is captured, change content is divided into atomic operation units, and the atomic operation units are subjected to type marking through a resource classification engine; dynamically reconstructing a local sub-graph of the resource dependence graph through a resource topology analysis engine based on a marking result; inputting the features of the atomic operation unit and the local subgraph into a pre-trained change influence prediction model, and generating an influenced component ID set; based on the affected component ID set, executing change influence simulation in the isolation sandbox, and generating a binary hot update patch according to a simulation result; and directionally pushing the binary hot update patch to a Cocos Creator rendering pipeline through a runtime injection interface, and triggering differential DOM update. According to the method, the code change can be monitored in real time, and the refreshing of the Cocos Creator page is automatically triggered, so that the manual operation of a developer is reduced, and the continuity and consistency of development are ensured.

The application provides a CAN frame data transmission method and device, equipment and a storage medium, relates to the technical field of data communication, solves the problem of system throughput decline and low network transmission efficiency of CAN frame data transmission in a high concurrency scene in the related art, the scheme realizes the atomic operation of quasi-lock-free through the construction of three buffer zone architecture and the separation of the lock mechanism, and the reduction of lock competition based on the separation mechanism of each buffer zone, which can maintain high throughput and low lock waiting time in different load scenarios, so that the system can respond in real time, and still meet the real-time requirements in the high concurrency and large data industrial application scene, and effectively improve the network transmission efficiency.

The application discloses a kind of high concurrency time series data processing method and device for anti-UAV system.The application uses lock-free hash table to cache time series data in cache space, lock-free cache design and CAS atomic operation reduce lock overhead, batch write throughput is high, conflict probability is low, support multi-thread high concurrency read-write, completely eliminate thread competition and blocking caused by traditional cache mechanism, improve concurrent processing capability;At the same time, batch write reduces the overhead of dynamic memory allocation, improves memory utilization;Through composite key fast positioning, hot data index structure priority query and lock-free reading mechanism, the query delay of hot data is extremely low, data preloading mechanism further reduces the delay of future related query, improves real-time response capability;Based on the dynamic elimination mechanism of elimination score, hot data / recent data can be preferentially retained, ensure resource utilization, significantly improve cache hit rate, greatly reduce access frequency to TSDB.

This application discloses an information processing method, apparatus, device, storage medium, and computer program. The method includes: when a collaborative document in a first state contains a first atomic operation and a second atomic operation, obtaining the tree structure corresponding to the collaborative document; updating the collaborative document from the first state to a second state based on the tree structure according to the operation intent expressed by the first atomic operation; wherein the first atomic operation includes a first type of operation among N predefined atomic operations in the tree structure, and the first type of operation is an operation that can be split into two or more atomic operations; performing intent restoration transformation on the operation intent expressed by the second atomic operation according to the operation intent expressed by the first atomic operation to obtain a transformed operation intent; and updating the collaborative document from the second state to a third state based on the tree structure according to the transformed operation intent. Using this application embodiment can improve the accuracy of conflict handling.

The invention relates to the technical field of industrial automation control, and discloses an auxiliary control workshop control system based on a DCS, and the system comprises a process topological graph construction module which is used for mapping a physical workshop into a dynamic graph containing an equipment digital object in real time; the task analysis module is used for converting the advanced task instruction into a quantitative target state set on a graph; the dynamic path planning module is used for automatically searching and generating an optimal atomic operation instruction sequence for reaching a target state based on the real-time state of the map; and the instruction execution and transaction management module and the exception handling and secure rollback module are used for ensuring atomic execution of the instruction sequence and secure rollback during failure. According to the method, a process control problem is converted into a graph theory path planning problem, so that the control system has the capabilities of dynamically avoiding faults and autonomously deciding, and the automation level, the reliability and the safety of the operation of the auxiliary control system are remarkably improved.