57 results about "Address decoder" patented technology

Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input / output (I / O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.

A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

The application discloses an address decoding control circuit for FLASH redundancy repair, which comprises a word line address decoding control circuit and a word line redundancy replacement repair circuit. The application realizes the shielding of standard word lines with defective storage units by increasing the circuit structure for controlling the word line address decoder, and simultaneously uses the redundant word lines for replacement repair. The repaired memory can be normally used, thereby significantly improving the yield of the FLASH memory.

Memory clock drivers, memory devices, and methods of operating memory devices, memory clock drivers are provided. A memory device includes two memory clock drivers disposed opposite each other across an array of memory cell rows. The memory clock drivers include decoders that decode addresses corresponding to one or more memory cell rows. The decoders are configured to decode the addresses to provide a plurality of word line signals to the corresponding memory cell rows. The memory device also includes a row selection circuit that receives a row selection address and activates a corresponding memory cell row. The memory device includes control circuitry to control the memory cell array at local and global levels, and includes I / O modules to send signals to different parts of the memory device and to integrate the memory device into external devices.

The application discloses a kind of support multi-mode convolution's memory computing integrated acceleration circuit, chip and equipment, the memory computing integrated acceleration circuit of the application includes input buffer (1), column address decoder (2) and 64 multiply-accumulate operation arrays (3), the multiply-accumulate operation array (3) includes: row address decoder (31), multi-mode adaptability controller (32), SRAM array (33), multiplier (34) and addition tree network (35), the 64 multiply-accumulate operation arrays (3) share one common column address decoder (2) and are connected to same input buffer (1).The application aims at using the flexibility and scalability inherent in digital CIM, without sacrificing the original CIM storage density, to design efficient control logic, to support various convolutions with minimal additional area cost and maintain high computing efficiency.

Disclosed herein are an asynchronous spike counting interface apparatus and an asynchronous spike counting method in a spike neural network. The asynchronous spike counting interface apparatus may include multiple counters, each counting the number of times each of neurons included in the spike neural network fires, and an address decoder for outputting an enable signal to the counter that counts the number of times the neuron corresponding to the address output from the spike neural network fires.

A memory device includes a memory cell array including a plurality of memory blocks, a plurality of pass transistors connected between a plurality of local lines included in the plurality of memory blocks, a plurality of selection signal lines connected to two or more local lines corresponding to an identical level among the plurality of local lines, and an address decoder configured to apply a block selection voltage to a block word line connected to a gate of each of the plurality of pass transistors, and the address decoder is configured to apply a first voltage to the block word line of an unselected memory block among the plurality of memory blocks.

An integrated circuit comprising multiple microvaults arranged adjacent to a first surface, each with a read periphery and a write periphery. The circuit includes bonding areas on the first surface. Microvaults feature programmable read and write clock cycle lengths, potentially based on different clocks. An interlock can be used to prevent simultaneous read and write operations. Read and write operations may use programmable voltages. The read / write periphery may be integrated, including address decoders and sense amplifiers. Microvaults can be arranged in chiplets with face-to-face bonding and through-silicon vias.

The invention provides a resistive random access memory architecture which can be applied to the technical field of circuits. The architecture includes: a resistive random access memory; the address decoder is used for converting the received address signal into a control signal; the word line driving module comprises a word line and a word line driver, and the word line driver is used for receiving the control signal and adjusting the level state of the word line based on the control signal so as to control the resistive random access memory to be in a conducting state; the control module comprises a level translator which is used for performing level conversion on the off-chip initial control voltage signal to obtain a target control voltage signal; the bit line transistor is used for controlling a bit line of the control module to be in a conducting state according to the target control voltage signal; the source line transistor is used for controlling a source line of the control module to be in a conducting state according to the target control voltage signal; the resistive random access memory in the on state adjusts a resistance state in response to the source line and bit line level signals, and executes a data write instruction based on the resistance state.

A memory device including a memory cell array having memory cells connected to a selected word line, a first voltage regulator configured to generate an underdrive voltage lower than an operating voltage, an address decoder including transistors, and configured to apply, to the selected word line, a voltage received during an underdrive period, a second voltage regulator configured to generate a well voltage to be applied to the transistors, a voltage transfer circuit configured to transfer the underdrive voltage or the well voltage to the address decoder, and a control logic configured, in response to the underdrive voltage being at a negative level, to control the second voltage regulator to set the well voltage to the negative level before the underdrive period, and to control the voltage transfer circuit to transfer the well voltage set to the negative level to the address decoder during the underdrive period.

The invention discloses an atomic operation execution method, which relates to the technical field of computers, and comprises the following steps: determining a target atomic register corresponding to an access request, a target address in the target atomic register and an operation type in a register file unit through an address decoder; and orderly executing atomic operation based on target atom register, the target address and the operation type through a control logic and sequencer, when it is determined that register value transformation information corresponding to the target address meets a preset interrupt condition through the interrupt control logic module, interrupt trigger information is sent to an interrupt signal generator; and generating a corresponding interrupt based on the interrupt trigger information through an interrupt signal generator, and sending the interrupt to a second target CPU corresponding to the interrupt trigger information. All atomic operations are realized in the module in a hardware mode, an atomic operation register and interrupt control logic are closely integrated on the hardware level, and atomic synchronization of a cross-CPU cluster is realized.

A system for controlling a quantum processor comprises a controller device having a plurality of input channels and output channels connected to qubit readout instruments and qubit control instruments. The controller device forms a register bank for receiving the data from the input channels, a feedback block for processing the data from the register bank, and an output interface for sending the results of the feedback block to the control instruments. For each input channel, the controller device comprises a mask generator with its own address decoder for processing the update messages on the input channels in parallel. Each update message comprises address data, data values for several registers and validity bits indicating if the data values are valid.

This application relates to the field of integrated circuit technology and discloses a writing circuit and method for configurable SRAM within an FPGA. It improves the write reliability of SRAM with a relatively low increase in design cost. The method includes: a configuration control module connected to a data controller; the data controller connected to a configuration memory cell array via multiple pairs of bit lines and negative bit lines, with each pair of bit lines and negative bit lines connected to a column of memory cells in the configuration memory cell array; the data controller connected to a buffer module via multiple pairs of bit lines and negative bit lines, a write enable signal line, and a data pull-down enable signal line, and connected to a pull-down control module via multiple pairs of bit lines and negative bit lines and the data pull-down enable signal line. The pull-down control module is used to turn on the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and turn off the N-type drive transistor switch of the other bit line or negative bit line; the configuration control module is connected to each of multiple address decoders via address enable signal lines.

A memory device includes; a memory cell array, and a command / address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command / address information, and a second decoding logic circuit configured to decrypt an address table. The command / address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

A memory includes a first command address decoder configured to decode a first chip selection signal and first command address signals and generate first control signals, a second command address decoder configured to decode a second chip selection signal and second command address signals and generate second control signals during a multi-channel mode and configured to decode the second chip selection signal and the first command address signals and generate second control signals during a multi-rank mode, a first memory core including first memory cells and being controlled by the first control signals, and a second memory core including second memory cells and being controlled by the second control signals.

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a memory block including a plurality of pages, a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to a selected memory cell and to apply a second bit line voltage to an unselected bit line during a de-capture operation, the second bit line voltage having a lower potential than a potential of the first bit line voltage, a voltage generation circuit configured to generate a first set voltage, a second set voltage, and a pass voltage during the de-capture operation, and an address decoder configured to apply the first set voltage to a selected word line corresponding to a selected page and to apply the second set voltage to an unselected word line during the de-capture operation, the second set voltage having a higher potential than a potential of the first set voltage.

An address decoder unit (30) for a memory cell array (10), the address decoder unit (30) including an address decoder (31) including an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33); and an address selection circuitry (32) connected to the address decoder (31) and including a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or beyond a memory address provided at the address input (33).

Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command / address decoder. The command / address decoders are configured to receive command and address signals from external contacts of the memory device. The command / address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command / address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command / address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

This disclosure provides a self-timing circuit, a shared self-timing circuit for SRAM read / write operations, and an SRAM memory. The self-timing circuit includes: two frequency multiplier circuits, each including a connected PMOS transistor, a rising-edge D flip-flop, and an inverter; each frequency multiplier circuit also has a first output and a second output that are inverted; a delay chain connected between the rising-edge D flip-flop and the inverter of one of the two frequency multiplier circuits; a complementary XOR gate, comprising two XOR gates, the input of each XOR gate connected to the first output of one of the two frequency multiplier circuits and the second output of the other; and a NAND gate, its input connected to the outputs of the two XOR gates, and its output outputting a PULSE signal. The technical solution of this application embodiment can accurately simulate the delay process of the address decoder and the read / write operation delay process of the SRAM cell to generate corresponding control signals, reducing the power consumption of the SRAM and improving its operating efficiency.

Embodiments of the present disclosure relate to systems and methods for an extensible data structure that aggregates BMC inputs and outputs through SERDES for data centers and server nodes. A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. The PCIe endpoint receives a packet, such as a TLP, from the BMC over a first communication interface, wherein a payload in the packet includes a transaction. The PCIe endpoint extracts transactions from the payload of the packet. An address decoder uses information in the transaction to decode an address of a memory space corresponding to a physical function of the PCIe endpoint and the second communication interface. The memory space stores transactions according to the decoded address. The second communication interface receives transactions from the memory space and sends the transactions to the HPM.

A flash memory includes a memory block connected to word lines, an address decoder that selects one or more of the word lines, a first pass transistor connected to the address decoder, a second pass transistor connected in series with the first pass transistor and connected to one word line among the word lines, a first driver circuit that controls a gate voltage of the first pass transistor based on a first enable signal, and a second driver circuit that controls a gate voltage of the second pass transistor based on a second enable signal. Based on the memory block being an unselected memory block during an erase operation, the first driver circuit controls the first pass transistor to be in a floating state, the second driver circuit controls a power voltage to be provided to a gate of the second pass transistor.

A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read / write command, a read command, and a write command that are input from outside of the semiconductor memory devide, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input / output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input / output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input / output driver without deserialization processing, and the read data is transmitted from the input / output sense amplifier to the read data pad without serialization processing. In some embodiments, the semiconductor memory device is electrically and physically coupled to a central processing unit by hybrid copper bonding.

A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

A trusted data random access storage device comprises a storage matrix which is used for storing data and determining the specific capacity of a memory and is composed of a plurality of storage units arranged in the form of a row-column matrix; the address decoder comprises a row address decoder and a column address decoder; the row address decoder is used for receiving a row address signal of external data and converting the row address signal into a corresponding word line selection signal; the column address decoder is used for processing a column address signal and completing data input or output through the read-write circuit; the read-write control module is used for executing read or write operation on the storage unit; the read-write input and output module is used for connecting the internal storage array and an external circuit and controlling input or output of data; and the identity authentication module is used for performing identity authentication between the storage device and the host end so as to determine whether the identity of the host end is safe and credible.

A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.

A system comprising a pre-compute storage memory comprising a plurality of pre-computed results that correspond to a neural network operation during inferencing or training, wherein the pre-compute storage memory is configured to provide the plurality of pre-computed results as output that is used in determining an activation of a next layer in a neural network; a memory array configured to store a plurality of weight activation sets; an address decoder configured to (i) generate an address in the pre-compute storage memory that matches an input operand, wherein the address corresponds to a weight activation set of the plurality of weight activation sets that matches the input operand and (ii) fetch a pre-computed result of the plurality of pre-compute results from the pre-compute storage memory based on the address.

A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

A memory device includes; a memory cell array, and a command / address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command / address information, and a second decoding logic circuit configured to decrypt an address table. The command / address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

A non-volatile memory device includes a first semiconductor layer, a second semiconductor layer, a control circuit, and a pad region, the first semiconductor layer including an upper substrate and an array of memory cells, word lines extending in a first direction and bit lines extending in a second direction disposed in the upper substrate. The array of memory cells includes vertical structures located on the upper substrate, and the vertical structures include memory blocks. The second semiconductor layer includes a lower substrate including an address decoder and a page buffer circuit. The vertical structures include via regions with one or more through-via vias disposed therein, and the via regions are spaced apart in the second direction. The array of memory cells includes pads corresponding to different ones of the bit lines. At least two of the pads include different numbers of the via regions according to a distance from the pad region in the first direction.

The invention discloses a large-scale MOS tube batch test circuit and system. The test circuit comprises a row address decoder, a column address decoder and a test unit array. The row address decoder is used for outputting row gating complementary signals, and the column address decoder is used for outputting column gating complementary signals. The test unit array comprises a plurality of test units arranged in rows and columns, and each test unit comprises a grid transmission gate, at least one drain transmission gate and at least one MOS tube to be tested. A grid electrode of the MOS tube to be tested is connected with the first bonding pad through the grid electrode transmission gate, a drain electrode is connected with at least one second bonding pad through the drain electrode transmission gate, a source electrode is connected with the third bonding pad, and a body electrode is connected with the fourth bonding pad. And the control ends of the drain transmission gate and the gate transmission gate are respectively connected with the corresponding row gating complementary signal and column gating complementary signal. According to the invention, manual needle insertion operation is abandoned, and high-efficiency and high-reliability testing of the large-scale MOS tube is realized through automatic site selection of the on-chip decoder.