625 results about "Address decoder" patented technology

A driver circuit for use in an active matrix display having switching devices at pixels. The driver circuit uses no shift registers. Random access to signal lines or scanning lines can be obtained. The display quality is improved. The production yield is improved. Also, lower electric power consumption and higher-speed operation can be accomplished. Data about gray levels assumes the form of digital values and is supplied to the driver circuit. The signal lines or scanning lines are selected by an address decoder circuit.

An electronic device that has an integrated central processing unit (CPU) including a pre-fetch stride analyzer and an out-of-order engine is provided. The electronic device also has a graphics engine, having graphics memory, that is coupled to the integrated CPU. A main memory that is coupled to a memory controller is provided. The memory controller is also coupled to the CPU and the graphics engine. The device has a host address decoder coupled to the integrated CPU. A front side bus (FSB) is provided that is coupled to the integrated CPU and the host address decoder. Also provided is a plurality of memory components. Accordingly, either the plurality of memory components or the graphics memory can be shared to perform alternate memory functions. Additionally, a method is provided that determines allocation availability between memory components in an integrated computer processing unit. The method also shares an available memory component as a pre-fetch buffer and another available memory component as a victim cache.

A cache memory device and method for operating the same. One embodiment of the cache memory device includes an address decoder decoding a memory address and selecting a target cache line. A first cache array is configured to output a first cache entry associated with the target cache line, and a second cache array coupled to an alignment unit is configured to output a second cache entry associated with the alignment cache line. The alignment unit coupled to the address decoder selects either the target cache line or a neighbor cache line proximate the target cache line as an alignment cache line output. Selection of either the target cache line or a neighbor cache line is based on an alignment bit in the memory address. A tag array cache is split into even and odd cache lines tags, and provides one or two tags for every cache access.

A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a block select circuit. In one embodiment, each CAM block includes a main CAM array having a plurality of rows of CAM cells each coupled to a corresponding word line, and a spare row of CAM cells coupled to a spare word line. Each spare row may be used to functionally replace a defective row in the same CAM block or in any other CAM block by programming the address of the defective row into the corresponding spare address decoder.

An information handling system includes a first node and a second node. Each node includes a processor and a local system memory. An interconnect between the first node and the second node enables a processor on the first node to access system memory on the second node. The system includes affinity information that is indicative of a proximity relationship between portions of system memory and the system nodes. A BIOS module migrates a block from one node to another, reloads BIOS-visible affinity tables, and reprograms memory address decoders before calling an operating system affinity module. The affinity module modifies the operating system visible affinity information. The operating system then has accurate affinity information with which to allocate processing threads so that a thread is allocated to a node where memory accesses issued by thread are local accesses.

A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.

A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus. Hot Plug Control Logic and Switch Control Logic in conjunction with the arbiter allows Hot Plug support along with the expanded slot environment.

In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may reduced. The reduction in this size of the memory cluster reduces the power needed for an address decoder to address sets within the bank.

The invention discloses a router and a transmission method thereof on a packet-circuit switching chip forming networks on chips. An input state device in the router controls the work state of an input channel and transmits received requisite signals to a priority encoder; the priority encoder encodes the request signals according to the set fixed priority and transforms input target node address signals to route direction signals by an address decoder to be output; an arbiter receives decoding results of the address decoder, outputs interconnected signals of an input port and an output port and occupation signals of the input port according the sequence of the fixed priority and the occupation condition of the ports until selecting a proper route to reach the target node; and a crossbar switch receives the interconnected signals output by the arbiter and realizes the correct interconnection between the input port and the output port. The invention has the advantages of little resource consumption and small transmission time delay. The invention is suitable for forming networks on chips with high performance, and can be applied to complicated systems on chips adopting on-chip network structure.

A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped structure; a DLB controller having a primary memory unit partitioned into a plurality of banks for controlling the state of the instruction memory system and accepting a program counter address as an input, the DLB controller outputs distinct signals. The system further comprises an address register located in the memory of the computing device, it is a staging register for the program counter address and an instruction fetch process that takes two cycles of the processor clock; and a bank select unit for serving as a program counter address decoder to accept the program counter address and to output a bank enable signal for selecting a bank in a primary memory unit, and a decoded address for access within the selected bank.

A pixel drive circuit includes a plurality of pixel circuits each including a photoelectric converting unit for converting an incident light into an electric charge and accumulating the converted electric charge, the plurality of pixel circuits being arranged in a matrix shape, an address decoder for selecting the pixel circuits to be controlled which are arranged on an identical line, a storage circuit for storing operation information to be executed by the pixel circuits selected by the address decoder, and a control circuit for controlling an operation of the pixel circuits selected by the address decoder in accordance with a storage state of the storage circuit. The control circuit controls a charge discharging operation of discharging an electric charge remaining in the photoelectric converting unit of each of the pixel circuits. The storage circuit holds the storage state until the charge discharging operation is completed.

A physical cache memory that is divided into one or more virtual segments using multiple circuits to decode addresses is provided. An address mapping and an address decoder is selected for each virtual segment. The address mapping comprises two or more address bits as set indexes for the virtual segment and the selected address bits are different for each virtual segment. A cache address decoder is provided for each virtual segment to enhance execution performance of programs or to protect against the side channel attack. Each physical cache address decoder comprises an address mask register to extract the selected address bits to locate objects in the virtual segment. The foregoing can be implemented as a method or apparatus for protecting against a side channel attack.

A Hamming neural network circuit which can be programmed and expanded is disclosed. The Hamming neural network includes an I/O circuit for inputting and outputting a plurality of standard patterns. A bi-directional transmission gate array is connected to the I/O circuit and controlled by a programming signal for transmitting the standard patterns. A plurality of standard pattern memory units is connected to the bi-directional transmission gate array for storing the plurality of standard patterns respectively. An address decoder is connected to the plurality of standard pattern memory units for addressing one of the plurality of standard pattern memory units. A plurality of pattern matching calculation circuit units are respectively connected to the plurality of standard pattern memory units for generating a plurality of matching rates between a to-be-recognized pattern and the plurality of standard patterns. An expandable matching rate comparing circuit is provided for comparing and sorting said plurality of matching rates.