83 results about "Address decoder" patented technology

Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input / output (I / O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.

An artificial intelligence acceleration system based on an 8T-SRAM calculation and storage integrated macro cell is provided with a digital-analog hybrid calculation array, the digital-analog hybrid calculation array is provided with m * n 8T-SRAM storage and calculation integrated units, and each 8T-SRAM storage and calculation integrated unit is provided with a 6T-SRAM unit, a transistor T7 and a transistor T8; the 6T-SRAM unit is provided with a storage unit, a transistor T5 and a transistor T6; the grid electrode of the T7 is connected with the output end Qb of the storage unit, the source electrode of the T7 is grounded, and the drain electrode of the T7 is connected with the source electrode of the T8; the grid electrode end of the T8 is connected with a read word line RWL, and the drain electrode of the T8 is connected with a read bit line RBL; one ends of the column calculation line BL and the column calculation line BLb are connected with the column address decoder, and the other ends are connected with the read-write calculation control unit; the word line WL and the read word line RWL are connected with the row address decoder; one end of the read bit line RBL is connected with a power supply, and the other end is connected with the column simulation accumulation unit which outputs a calculation result through the analog-to-digital converter. The device has the advantages of being simple and clear in structure, capable of achieving efficient on-chip multiply-accumulate operation, easy to control, low in power consumption, high in precision and the like.

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

The application discloses an address decoding control circuit for FLASH redundancy repair, which comprises a word line address decoding control circuit and a word line redundancy replacement repair circuit. The application realizes the shielding of standard word lines with defective storage units by increasing the circuit structure for controlling the word line address decoder, and simultaneously uses the redundant word lines for replacement repair. The repaired memory can be normally used, thereby significantly improving the yield of the FLASH memory.

Memory clock drivers, memory devices, and methods of operating memory devices, memory clock drivers are provided. A memory device includes two memory clock drivers disposed opposite each other across an array of memory cell rows. The memory clock drivers include decoders that decode addresses corresponding to one or more memory cell rows. The decoders are configured to decode the addresses to provide a plurality of word line signals to the corresponding memory cell rows. The memory device also includes a row selection circuit that receives a row selection address and activates a corresponding memory cell row. The memory device includes control circuitry to control the memory cell array at local and global levels, and includes I / O modules to send signals to different parts of the memory device and to integrate the memory device into external devices.

The invention relates to a phase change memory write circuit and method based on an SPI (Serial Peripheral Interface), and the circuit comprises an N-bit address register, a 2M-bit input data register, an N-K-bit phase change memory write address register, a K-bit write address decoder, a 2K-bit write mask register and a 2M + K-bit write data register. According to the invention, at most 2K data received by the SPI interface is merged and then written into the phase change memory at one time, so that the write-in delay of the phase change memory is utilized to the maximum extent, and the data transmission rate of the phase change memory based on the SPI interface is improved.

Memory clock drivers, memories, and methods of operating memory clock drivers are provided. A memory device contains two memory clock drivers disposed opposite each other across an array of rows of memory cells. The memory clock drivers contain decoders, which decode an address corresponding to one or more rows of memory cells. The decoders are configured to decode the address to provide a plurality of word line signals to the corresponding rows of memory cells. The memory device also includes a row select circuit, which receives a row select address and activates a corresponding row of memory cells. The memory device includes control circuitry to control the arrays of memory cells at a local and a global level, as well as I / O modules to send signals to different parts of the memory device and integrate the memory device into external devices.

The application discloses a kind of support multi-mode convolution's memory computing integrated acceleration circuit, chip and equipment, the memory computing integrated acceleration circuit of the application includes input buffer (1), column address decoder (2) and 64 multiply-accumulate operation arrays (3), the multiply-accumulate operation array (3) includes: row address decoder (31), multi-mode adaptability controller (32), SRAM array (33), multiplier (34) and addition tree network (35), the 64 multiply-accumulate operation arrays (3) share one common column address decoder (2) and are connected to same input buffer (1).The application aims at using the flexibility and scalability inherent in digital CIM, without sacrificing the original CIM storage density, to design efficient control logic, to support various convolutions with minimal additional area cost and maintain high computing efficiency.

Disclosed herein are an asynchronous spike counting interface apparatus and an asynchronous spike counting method in a spike neural network. The asynchronous spike counting interface apparatus may include multiple counters, each counting the number of times each of neurons included in the spike neural network fires, and an address decoder for outputting an enable signal to the counter that counts the number of times the neuron corresponding to the address output from the spike neural network fires.

The invention discloses a cross-application double-region real-time color contrast system and method based on dynamic region high-frequency sampling. According to the system disclosed by the invention, efficient operation is realized through cooperation of a modular hardware architecture and a data stream; the screen capture module transmits full-screen pixel data to the dynamic sampling module in real time through memory mapping and a hardware acceleration channel; the dynamic sampling module is combined with a boundary protection unit and a double-buffering technology to ensure data integrity; the high-frequency sampling controller drives an interrupt signal at the frequency of 60FPS to coordinate the time sequence of each module; the real-time comparison interface module dynamically updates an interface through a frame buffer and a graphic rendering pipeline; and the multi-DPI adaptive module realizes cross-screen accurate alignment through a configuration bus and an address decoder. According to the method, through hardware interruption, DMA transmission and graphic pipeline rendering, the color correction efficiency is further improved, and the method is suitable for film and television toning, game development and industrial simulation scenes.

Disclosed is a nonvolatile memory device which includes a first plane that includes a plurality of memory blocks, a second plane that includes a plurality of memory blocks, an address replacing circuit that receives a first input address from an external controller, the first input address corresponding to a first memory block of the plurality of memory blocks of the first plane from an external controller and outputs a replaced address based on the first input address and bad block information, and an address decoder that controls word lines connected with a second memory block based on the replaced address, the word lines corresponding to the replaced address from among the plurality of memory blocks of the second plane. The first memory block of the first plane is a bad block.

A method used in a flash memory controller includes: using an error correction code (ECC) circuit to perform an ECC operation upon data of a block of a flash memory chip / die of a flash memory device to generate an ECC result; when the ECC result indicates a failure, storing an access task corresponding to the block into a specific buffer; and, controlling a voltage generator of the flash memory device through a specific communication interface to control at least one address decoder of the flash memory device to access the block of the flash memory chip / die again according to at least one threshold voltage level of the voltage generator after the access task has been temporarily stored in the specific buffer for a specific default time.

A memory device includes a memory cell array including a plurality of memory blocks, a plurality of pass transistors connected between a plurality of local lines included in the plurality of memory blocks, a plurality of selection signal lines connected to two or more local lines corresponding to an identical level among the plurality of local lines, and an address decoder configured to apply a block selection voltage to a block word line connected to a gate of each of the plurality of pass transistors, and the address decoder is configured to apply a first voltage to the block word line of an unselected memory block among the plurality of memory blocks.

An integrated circuit comprising multiple microvaults arranged adjacent to a first surface, each with a read periphery and a write periphery. The circuit includes bonding areas on the first surface. Microvaults feature programmable read and write clock cycle lengths, potentially based on different clocks. An interlock can be used to prevent simultaneous read and write operations. Read and write operations may use programmable voltages. The read / write periphery may be integrated, including address decoders and sense amplifiers. Microvaults can be arranged in chiplets with face-to-face bonding and through-silicon vias.

The invention provides a resistive random access memory architecture which can be applied to the technical field of circuits. The architecture includes: a resistive random access memory; the address decoder is used for converting the received address signal into a control signal; the word line driving module comprises a word line and a word line driver, and the word line driver is used for receiving the control signal and adjusting the level state of the word line based on the control signal so as to control the resistive random access memory to be in a conducting state; the control module comprises a level translator which is used for performing level conversion on the off-chip initial control voltage signal to obtain a target control voltage signal; the bit line transistor is used for controlling a bit line of the control module to be in a conducting state according to the target control voltage signal; the source line transistor is used for controlling a source line of the control module to be in a conducting state according to the target control voltage signal; the resistive random access memory in the on state adjusts a resistance state in response to the source line and bit line level signals, and executes a data write instruction based on the resistance state.

A memory device including a memory cell array having memory cells connected to a selected word line, a first voltage regulator configured to generate an underdrive voltage lower than an operating voltage, an address decoder including transistors, and configured to apply, to the selected word line, a voltage received during an underdrive period, a second voltage regulator configured to generate a well voltage to be applied to the transistors, a voltage transfer circuit configured to transfer the underdrive voltage or the well voltage to the address decoder, and a control logic configured, in response to the underdrive voltage being at a negative level, to control the second voltage regulator to set the well voltage to the negative level before the underdrive period, and to control the voltage transfer circuit to transfer the well voltage set to the negative level to the address decoder during the underdrive period.

The invention discloses an atomic operation execution method, which relates to the technical field of computers, and comprises the following steps: determining a target atomic register corresponding to an access request, a target address in the target atomic register and an operation type in a register file unit through an address decoder; and orderly executing atomic operation based on target atom register, the target address and the operation type through a control logic and sequencer, when it is determined that register value transformation information corresponding to the target address meets a preset interrupt condition through the interrupt control logic module, interrupt trigger information is sent to an interrupt signal generator; and generating a corresponding interrupt based on the interrupt trigger information through an interrupt signal generator, and sending the interrupt to a second target CPU corresponding to the interrupt trigger information. All atomic operations are realized in the module in a hardware mode, an atomic operation register and interrupt control logic are closely integrated on the hardware level, and atomic synchronization of a cross-CPU cluster is realized.

A system for controlling a quantum processor comprises a controller device having a plurality of input channels and output channels connected to qubit readout instruments and qubit control instruments. The controller device forms a register bank for receiving the data from the input channels, a feedback block for processing the data from the register bank, and an output interface for sending the results of the feedback block to the control instruments. For each input channel, the controller device comprises a mask generator with its own address decoder for processing the update messages on the input channels in parallel. Each update message comprises address data, data values for several registers and validity bits indicating if the data values are valid.

This application relates to the field of integrated circuit technology and discloses a writing circuit and method for configurable SRAM within an FPGA. It improves the write reliability of SRAM with a relatively low increase in design cost. The method includes: a configuration control module connected to a data controller; the data controller connected to a configuration memory cell array via multiple pairs of bit lines and negative bit lines, with each pair of bit lines and negative bit lines connected to a column of memory cells in the configuration memory cell array; the data controller connected to a buffer module via multiple pairs of bit lines and negative bit lines, a write enable signal line, and a data pull-down enable signal line, and connected to a pull-down control module via multiple pairs of bit lines and negative bit lines and the data pull-down enable signal line. The pull-down control module is used to turn on the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and turn off the N-type drive transistor switch of the other bit line or negative bit line; the configuration control module is connected to each of multiple address decoders via address enable signal lines.

The technology disclosed herein provides a memory blade including a plurality of fabric switches configured to receive commands from a plurality of host clients, an address decoder and tracker circuit communicatively connected to the fabric switches and configured to determine the source of commands received at the fabric switches an aggregator crossbar configured to provide bandwidth aggregation between host clients and a plurality of memory modules; and a buffer module configured to couple the commands from the plurality of host clients with the plurality of memory modules.

A memory device includes; a memory cell array, and a command / address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command / address information, and a second decoding logic circuit configured to decrypt an address table. The command / address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

A memory includes a first command address decoder configured to decode a first chip selection signal and first command address signals and generate first control signals, a second command address decoder configured to decode a second chip selection signal and second command address signals and generate second control signals during a multi-channel mode and configured to decode the second chip selection signal and the first command address signals and generate second control signals during a multi-rank mode, a first memory core including first memory cells and being controlled by the first control signals, and a second memory core including second memory cells and being controlled by the second control signals.

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a memory block including a plurality of pages, a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to a selected memory cell and to apply a second bit line voltage to an unselected bit line during a de-capture operation, the second bit line voltage having a lower potential than a potential of the first bit line voltage, a voltage generation circuit configured to generate a first set voltage, a second set voltage, and a pass voltage during the de-capture operation, and an address decoder configured to apply the first set voltage to a selected word line corresponding to a selected page and to apply the second set voltage to an unselected word line during the de-capture operation, the second set voltage having a higher potential than a potential of the first set voltage.

An address decoder unit (30) for a memory cell array (10), the address decoder unit (30) including an address decoder (31) including an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33); and an address selection circuitry (32) connected to the address decoder (31) and including a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or beyond a memory address provided at the address input (33).

Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command / address decoder. The command / address decoders are configured to receive command and address signals from external contacts of the memory device. The command / address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command / address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command / address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.

In an I2C communication system, a dedicated address pin enables a primary device to individually address a plurality of secondary devices. When the first transmission is performed from the primary device, the logic level on each dedicated address pin can be stored in each secondary device. Address decoder circuitry within each secondary device can decode transmissions from the primary device using the saved address pin values. Then, since the logic level on the address pin has been saved, the dedicated address pin can be reused for separate functions.

This disclosure provides a self-timing circuit, a shared self-timing circuit for SRAM read / write operations, and an SRAM memory. The self-timing circuit includes: two frequency multiplier circuits, each including a connected PMOS transistor, a rising-edge D flip-flop, and an inverter; each frequency multiplier circuit also has a first output and a second output that are inverted; a delay chain connected between the rising-edge D flip-flop and the inverter of one of the two frequency multiplier circuits; a complementary XOR gate, comprising two XOR gates, the input of each XOR gate connected to the first output of one of the two frequency multiplier circuits and the second output of the other; and a NAND gate, its input connected to the outputs of the two XOR gates, and its output outputting a PULSE signal. The technical solution of this application embodiment can accurately simulate the delay process of the address decoder and the read / write operation delay process of the SRAM cell to generate corresponding control signals, reducing the power consumption of the SRAM and improving its operating efficiency.

The present invention proposes an on-chip storage multiplexing method, comprising: a universal bus control interface, a universal bus control decoder and a protocol converter, a tightly coupled control interface, a tightly coupled control interface address decoder, an SRAM control right hardware allocation module, and a control selector corresponding to each SRAM unit; wherein, an external master device accesses the SRAM unit through the universal bus control interface; when the universal bus initiates an access request, the universal bus control decoder and the protocol converter select the corresponding SRAM unit, convert the access request into an access timing of the SRAM unit, and initiate a read / write request to the corresponding control selector; an external dedicated device directly accesses the SRAM unit through the tightly coupled control interface; the tightly coupled control interface address decoder performs decoding and selects the corresponding SRAM unit; the SRAM control right hardware allocation module allocates the SRAM unit; and the control selector corresponding to the SRAM unit selects access from the universal bus control interface and from the tightly coupled control interface.

Embodiments of the present disclosure relate to systems and methods for an extensible data structure that aggregates BMC inputs and outputs through SERDES for data centers and server nodes. A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. The PCIe endpoint receives a packet, such as a TLP, from the BMC over a first communication interface, wherein a payload in the packet includes a transaction. The PCIe endpoint extracts transactions from the payload of the packet. An address decoder uses information in the transaction to decode an address of a memory space corresponding to a physical function of the PCIe endpoint and the second communication interface. The memory space stores transactions according to the decoded address. The second communication interface receives transactions from the memory space and sends the transactions to the HPM.