33 results about "Address decoder" patented technology

Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input / output (I / O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.

A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

Memory clock drivers, memory devices, and methods of operating memory devices, memory clock drivers are provided. A memory device includes two memory clock drivers disposed opposite each other across an array of memory cell rows. The memory clock drivers include decoders that decode addresses corresponding to one or more memory cell rows. The decoders are configured to decode the addresses to provide a plurality of word line signals to the corresponding memory cell rows. The memory device also includes a row selection circuit that receives a row selection address and activates a corresponding memory cell row. The memory device includes control circuitry to control the memory cell array at local and global levels, and includes I / O modules to send signals to different parts of the memory device and to integrate the memory device into external devices.

Disclosed herein are an asynchronous spike counting interface apparatus and an asynchronous spike counting method in a spike neural network. The asynchronous spike counting interface apparatus may include multiple counters, each counting the number of times each of neurons included in the spike neural network fires, and an address decoder for outputting an enable signal to the counter that counts the number of times the neuron corresponding to the address output from the spike neural network fires.

A memory device includes a memory cell array including a plurality of memory blocks, a plurality of pass transistors connected between a plurality of local lines included in the plurality of memory blocks, a plurality of selection signal lines connected to two or more local lines corresponding to an identical level among the plurality of local lines, and an address decoder configured to apply a block selection voltage to a block word line connected to a gate of each of the plurality of pass transistors, and the address decoder is configured to apply a first voltage to the block word line of an unselected memory block among the plurality of memory blocks.

The invention discloses an atomic operation execution method, which relates to the technical field of computers, and comprises the following steps: determining a target atomic register corresponding to an access request, a target address in the target atomic register and an operation type in a register file unit through an address decoder; and orderly executing atomic operation based on target atom register, the target address and the operation type through a control logic and sequencer, when it is determined that register value transformation information corresponding to the target address meets a preset interrupt condition through the interrupt control logic module, interrupt trigger information is sent to an interrupt signal generator; and generating a corresponding interrupt based on the interrupt trigger information through an interrupt signal generator, and sending the interrupt to a second target CPU corresponding to the interrupt trigger information. All atomic operations are realized in the module in a hardware mode, an atomic operation register and interrupt control logic are closely integrated on the hardware level, and atomic synchronization of a cross-CPU cluster is realized.

A system for controlling a quantum processor comprises a controller device having a plurality of input channels and output channels connected to qubit readout instruments and qubit control instruments. The controller device forms a register bank for receiving the data from the input channels, a feedback block for processing the data from the register bank, and an output interface for sending the results of the feedback block to the control instruments. For each input channel, the controller device comprises a mask generator with its own address decoder for processing the update messages on the input channels in parallel. Each update message comprises address data, data values for several registers and validity bits indicating if the data values are valid.

This application relates to the field of integrated circuit technology and discloses a writing circuit and method for configurable SRAM within an FPGA. It improves the write reliability of SRAM with a relatively low increase in design cost. The method includes: a configuration control module connected to a data controller; the data controller connected to a configuration memory cell array via multiple pairs of bit lines and negative bit lines, with each pair of bit lines and negative bit lines connected to a column of memory cells in the configuration memory cell array; the data controller connected to a buffer module via multiple pairs of bit lines and negative bit lines, a write enable signal line, and a data pull-down enable signal line, and connected to a pull-down control module via multiple pairs of bit lines and negative bit lines and the data pull-down enable signal line. The pull-down control module is used to turn on the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and turn off the N-type drive transistor switch of the other bit line or negative bit line; the configuration control module is connected to each of multiple address decoders via address enable signal lines.

A memory device includes; a memory cell array, and a command / address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command / address information, and a second decoding logic circuit configured to decrypt an address table. The command / address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

A memory includes a first command address decoder configured to decode a first chip selection signal and first command address signals and generate first control signals, a second command address decoder configured to decode a second chip selection signal and second command address signals and generate second control signals during a multi-channel mode and configured to decode the second chip selection signal and the first command address signals and generate second control signals during a multi-rank mode, a first memory core including first memory cells and being controlled by the first control signals, and a second memory core including second memory cells and being controlled by the second control signals.

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a memory block including a plurality of pages, a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to a selected memory cell and to apply a second bit line voltage to an unselected bit line during a de-capture operation, the second bit line voltage having a lower potential than a potential of the first bit line voltage, a voltage generation circuit configured to generate a first set voltage, a second set voltage, and a pass voltage during the de-capture operation, and an address decoder configured to apply the first set voltage to a selected word line corresponding to a selected page and to apply the second set voltage to an unselected word line during the de-capture operation, the second set voltage having a higher potential than a potential of the first set voltage.

An address decoder unit (30) for a memory cell array (10), the address decoder unit (30) including an address decoder (31) including an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33); and an address selection circuitry (32) connected to the address decoder (31) and including a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or beyond a memory address provided at the address input (33).

A flash memory includes a memory block connected to word lines, an address decoder that selects one or more of the word lines, a first pass transistor connected to the address decoder, a second pass transistor connected in series with the first pass transistor and connected to one word line among the word lines, a first driver circuit that controls a gate voltage of the first pass transistor based on a first enable signal, and a second driver circuit that controls a gate voltage of the second pass transistor based on a second enable signal. Based on the memory block being an unselected memory block during an erase operation, the first driver circuit controls the first pass transistor to be in a floating state, the second driver circuit controls a power voltage to be provided to a gate of the second pass transistor.

A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

A trusted data random access storage device comprises a storage matrix which is used for storing data and determining the specific capacity of a memory and is composed of a plurality of storage units arranged in the form of a row-column matrix; the address decoder comprises a row address decoder and a column address decoder; the row address decoder is used for receiving a row address signal of external data and converting the row address signal into a corresponding word line selection signal; the column address decoder is used for processing a column address signal and completing data input or output through the read-write circuit; the read-write control module is used for executing read or write operation on the storage unit; the read-write input and output module is used for connecting the internal storage array and an external circuit and controlling input or output of data; and the identity authentication module is used for performing identity authentication between the storage device and the host end so as to determine whether the identity of the host end is safe and credible.

A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.

A system comprising a pre-compute storage memory comprising a plurality of pre-computed results that correspond to a neural network operation during inferencing or training, wherein the pre-compute storage memory is configured to provide the plurality of pre-computed results as output that is used in determining an activation of a next layer in a neural network; a memory array configured to store a plurality of weight activation sets; an address decoder configured to (i) generate an address in the pre-compute storage memory that matches an input operand, wherein the address corresponds to a weight activation set of the plurality of weight activation sets that matches the input operand and (ii) fetch a pre-computed result of the plurality of pre-compute results from the pre-compute storage memory based on the address.

A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

The invention discloses a large-scale MOS tube batch test circuit and system. The test circuit comprises a row address decoder, a column address decoder and a test unit array. The row address decoder is used for outputting row gating complementary signals, and the column address decoder is used for outputting column gating complementary signals. The test unit array comprises a plurality of test units arranged in rows and columns, and each test unit comprises a grid transmission gate, at least one drain transmission gate and at least one MOS tube to be tested. A grid electrode of the MOS tube to be tested is connected with the first bonding pad through the grid electrode transmission gate, a drain electrode is connected with at least one second bonding pad through the drain electrode transmission gate, a source electrode is connected with the third bonding pad, and a body electrode is connected with the fourth bonding pad. And the control ends of the drain transmission gate and the gate transmission gate are respectively connected with the corresponding row gating complementary signal and column gating complementary signal. According to the invention, manual needle insertion operation is abandoned, and high-efficiency and high-reliability testing of the large-scale MOS tube is realized through automatic site selection of the on-chip decoder.

The application discloses an atomic operation execution method, and relates to the technical field of computers, and comprises the following steps: determining a target atomic register corresponding to an access request, a target address in the target atomic register and an operation type in a register file unit through an address decoder; sequentially executing the atomic operation based on the target atomic register, the target address and the operation type through control logic and a sequencer; if it is determined that register value transformation information corresponding to the target address meets a preset interrupt condition through an interrupt control logic module, sending interrupt trigger information to an interrupt signal generator; and generating a corresponding interrupt based on the interrupt trigger information through the interrupt signal generator, and sending the interrupt to a second target CPU corresponding to the interrupt trigger information. All atomic operations in the application are implemented in a hardware mode within a module, and the atomic operation register and the interrupt control logic are closely integrated at a hardware level, thereby realizing atomic synchronization across a CPU cluster.

The invention provides a data transmission circuit including a plurality of transmission libraries, an imaging system and a data transmission method. The data transmission circuit is used for the image sensor. Each transfer library is coupled to provide image data to a subsequent transfer library in a direction toward the functional logic in response to a clock signal. Each transport library includes an address decoder. The address decoder uses the first decoder to generate a first decoded signal to determine which of the plurality of channels is coupled to the plurality of word buses. The address decoder generates a second decoded signal using a second decoder. The second decoded signal is subjected to a first logical operation to generate a first judgment signal, the first judgment signal is used for determining whether the second decoded signal conforms to the address of the current transmission library, and the first judgment signal is used for generating a library switch control signal. The first decoding signal and the first judgment signal are used for generating a channel switch control signal.

The utility model discloses an image data analysis and storage system, which comprises an image input interface, a feature extraction module, a decision module, a data buffer module and a storage control module, the image input interface is connected with the video processor of the feature extraction module; the feature extraction module extracts image features through a feature detection circuit based on a comparator, and generates a control signal through the decision module; and the control signal controls an address decoder in the storage control module, so that a data stream is automatically guided to a solid-state memory or a disk memory through a data gating switch. According to the utility model, analysis and shunt storage of image data are realized through a hardware circuit, and the system has the advantages of determined delay, high efficiency and no need of software intervention.

Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

A non-volatile memory device based on a fuse type memory cell array includes an eFuse cell array including a plurality of unit cells in matrix form, each unit cell having a first switching element and an eFuse; an address decoder configured to activate, based on an address input from an external device, a word line used for program operation or read operation among a plurality of word lines; a current controller configured to supply a program current used for the program operation or a read current used for the read operation; a bit line sense amplifier configured to sense digital data output from the eFuse cell array and output the digital data; and a control logic configured to control the program operation or the read operation to be performed based on a control signal input from the external device.

This invention discloses a dedicated protocol conversion device and embedded system management circuit for the VME bus, comprising: a PCIe interface circuit, a protocol conversion core circuit composed of a domestic FPGA chip (JFM7K325T), a VME bus driver circuit composed of an MS8T245TP-I bus transceiver, and a backplane interface circuit. The device completes the hardware conversion from PCIe to VME bus protocol using a single chip through an address decoder, data buffer, control state machine, and interrupt management logic embedded within the FPGA. This invention also integrates an embedded system hardware monitoring circuit, which is fixedly connected to a domestic RTC clock chip, temperature sensor chip, and EEPROM chip via an I2C bus, and uses hardware timers and hardware address generation logic to achieve periodic automatic hardware recording of log data. This invention solves the technical problems of high hardware redundancy, reliance on imported chips, and poor signal integrity in existing VME bus interface solutions, achieving complete independent control from the chip level to the circuit level.

The present application relates to a computer readable storage medium, a virtualized register device and a method for accessing the device, the virtualized register device comprising: a register space, which is divided into a plurality of physical blocks, wherein each physical block comprises a plurality of register groups, and each register group comprises a plurality of registers; and an address decoder, which receives an address of a selected register group from a processing unit to activate the selected register group, wherein the register group is selected by the processing unit according to a virtual device which is about to send a request, from the plurality of physical blocks, a physical block corresponding to the virtual device, and according to information of the virtual device, one register group from a plurality of register groups in the determined physical block. The present application changes the access path by the above-mentioned division of register groups and dynamic execution of block selection and group selection, without the need to save and restore data previously stored in the registers, thereby improving the efficiency of register access.

The disclosure provides an improved pre-decoding scheme that uses pre-decoders with multiple decoders that generate clocked pre-decoded signals, which reduces address set-up time and hold. The ordering of the address bits processed by the multiple decoders is also arranged to advantageously allow sharing logic gates of the multiple decoders, sharing of nodes of the logic gates, or sharing a combination of both. In one example, a memory circuit is disclosed that includes: (1) an array of memory cells arranged in rows and columns, and (2) an address decoder for decoding a binary address to assert wordlines associated with the rows, wherein the address decoder has (2A) a row decoder for asserting one of the wordlines based on clocked-pre-decode signals, and (2B) a pre-decoder having multiple decoders that generate the clocked pre-decode signals from the binary address and provide the clocked pre-decode signals to the row decoder for the asserting.

A memory is provided having a plurality of banks. A shared redundancy address decoder decodes a redundancy address for each of the banks to provide a decoded redundancy address to each bank. A serializer serializes the decoded redundancy address into a serialized decoded redundancy address. The banks deserialize the serialized decoded redundancy address to recover their decoded redundancy address. Should one of the banks have a defect, the bank repairs the defect by reconfiguring its resources responsive to its decoded redundancy address.

A block selection circuit of a flash memory, includes: a first pass transistor connected to an address decoder; a second pass transistor connected in series with the first pass transistor; a first driver circuit configured to control a gate voltage of the first pass transistor based on a first enable signal; a second driver circuit to control a gate voltage of the second pass transistor based on a second enable signal; a first switch circuit to provide a first power voltage or a second power voltage to a gate of the first pass transistor through the first driver circuit based on a first switch signal; and a second switch circuit to share a plurality of memory blocks and provide the first power voltage or the second power voltage to the first switch circuit.

A memory access method comprises adding routing information to a memory page table, so that a memory management unit (MMU) queries, in a process of performing address translation on a virtual address (VA), the memory page table to obtain the routing information. After querying the memory page table and obtaining a physical address (PA), the MMU may directly route the PA based on the routing information, whereby a system address decoder (SAD) is not needed for further decoding the PA.