1467results about How to "Run at high speed" patented technology

It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor.

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

The present invention provides a semiconductor device which can be produced by simple and cheap processes and effectively achieve improved performances and a reduced electric power consumption. Further, the present invention provides a production method thereof and a display device including the semiconductor device or a semiconductor device produced by the production method. The present invention is a semiconductor device including a pixel part and an integrated circuit part on a substrate, the pixel part including a switching element having a gate electrode formed on a semiconductor thin film, the integrated circuit part including a semiconductor layer on a gate electrode, wherein a passivation film is formed on the gate electrode in the pixel part.

A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.

A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.

A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating region surrounds the at least one pair of elongate channel regions, and a gate electrode surrounds the gate insulating region and the at least one pair of elongate channel regions. Support patterns may be interposed between the semiconductor substrate and the source and drain regions. The elongate channel regions may have sufficiently small cross-section to enable complete depletion thereof. For example, a width and a thickness of the elongate channel regions may be in a range from about 10 nanometers to about 20 nanometers. The elongate channel regions may have rounded cross-sections, e.g., each of the elongate channel regions may have an elliptical cross-section. The at least one pair of elongate channel regions may include a plurality of stacked pairs of elongate channel regions.

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

A transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use, and a semiconductor device including the transistor are provided. In a transistor in which a semiconductor layer, a source electrode layer and a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order over an oxide insulating film, an oxide semiconductor stack composed of at least two oxide semiconductor layers having different energy gaps is used as the semiconductor layer. Oxygen and/or a dopant may be introduced into the oxide semiconductor stack.

A high-speed vision sensor includes: an analog-to-digital converter array 13, in which one analog-to-digital converter 210 is provided in correspondence with all the photodetector elements 120 that are located on each row in a photodetector array 11; a parallel processing system 14 that includes processor elements 400 and shift registers 410, both of which form a one-to-one correspondence with the photodetector elements 120; and data buses 17, 18 and data buffers 19 and 20 for data transfer to processing elements 400. The processing elements 400 perform high-speed image processing between adjacent pixels by parallel processings. By using the data buses 17, 18, it is possible to attain, at a high rate of speed, such calculation processing that requires data supplied from outside.

The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

A driver circuit for use in an active matrix display having switching devices at pixels. The driver circuit uses no shift registers. Random access to signal lines or scanning lines can be obtained. The display quality is improved. The production yield is improved. Also, lower electric power consumption and higher-speed operation can be accomplished. Data about gray levels assumes the form of digital values and is supplied to the driver circuit. The signal lines or scanning lines are selected by an address decoder circuit.

A high-speed shift register circuit is provided. The shift register circuit includes a first transistor supplying a clock signal to a first output terminal, a second transistor discharging the first output terminal, a third transistor supplying the above clock signal to a second output terminal, and a fourth transistor discharging the second output terminal. The gates of the first and third transistors are both connected to a first node, and the gates of the second and fourth transistors are both connected to a second node. The first node is charged by a fifth transistor which is connected between the first node and a first input terminal and which has a gate connected to a second input end.

A method and an apparatus for examining the subsurface microstructure of a sample are provided. Radiation from a plurality of optical radiation sources travels along a first optical path. In the first optical path, a device focuses the optical radiati n from each of the optical sources into a plurality of respective focal points along the first optical path to provide substantially continuous coverage of a selected portion of the first optical path. Then, a sample on the first optical path within the selected length extending into the sample is scanned along said selected portion of the first optical path.