26 results about "Junction leakage" patented technology

The invention provides a forming method of a metal silicide barrier layer and a semiconductor device, and belongs to the field of semiconductors. The forming method of the metal silicide barrier layer comprises the following steps: providing a semiconductor substrate; and forming a metal silicide barrier layer. Exposing and developing the photoresist layer to form a window which exposes the first gate structure and the source and drain regions on the two sides of the first gate structure and exposes the second gate structure and the source and drain regions on the two sides of the second gate structure; and carrying out dry etching on the exposed metal silicide barrier layer. And performing wet etching on the metal silicide barrier layer after the dry etching. By increasing the width of the metal silicide barrier layer along the transverse direction, the diffusion of NiSi to the second gate structure is effectively reduced, and the distance from the NiSi to the second gate structure is increased, so that the junction leakage current effect of the semiconductor device is inhibited, the interference generated by leakage current between memory cells of the semiconductor device is improved, and the reliability of the semiconductor device is improved. The performance of the semiconductor device is improved.

The application relates to the field of semiconductors and discloses a semiconductor device and a forming method of the semiconductor device. The semiconductor device comprises a substrate, a source region and a drain region, and a halo injection region. The halo injection region comprises a first halo injection sub-region for preventing direct channel penetration and a second halo injection sub-region for adjusting junction leakage current. The first halo injection sub-region covers the bottom and / or side of a preset region, the preset region comprising the source region and / or the drain region, and a depletion layer ends in the first halo injection sub-region. The second halo injection sub-region covers the bottom and / or side of the first halo injection sub-region, and a minority carrier diffusion layer ends in the second halo injection sub-region. The doping concentration of the second halo injection sub-region is greater than that of the first halo injection sub-region. The semiconductor device provided by the application can adjust the interface performance between the substrate and the source region and / or the drain region by setting the halo injection region, and can solve the contradiction between direct channel penetration and pn junction leakage.

A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

To provide a display device with a structure suitable as a protection circuit, and a method for stabilizing an operation by increasing a function of the protection circuit.SOLUTION: A protection circuit is formed using a nonlinear element 170a including a gate insulating layer 102 that covers a gate electrode 101, a first oxide semiconductor layer 103 that overlaps with the gate electrode 101 on the gate insulating layer 102, a channel protection layer that covers a region overlapping with a channel formation region in the first oxide semiconductor layer 103, and a pair of a first wiring layer 38 and a second wiring layer 39 in which an end part overlaps with the gate electrode on the channel protection layer and a second oxide semiconductor layer 104a and a conductive layer 105a are stacked. By forming a junction between the oxide semiconductor layers with different physical properties on the gate insulating layer 102, a stable operation becomes possible as compared to Schottky junction, junction leakage is reduced, and characteristics of the nonlinear element 170a can be improved.SELECTED DRAWING: Figure 5

The invention discloses a chip aging test system and method, and the method comprises the steps: constructing a main buried layer and a reference buried layer in a silicon substrate in a chip manufacturing stage, enabling a sensing structure and a transistor to share a substrate and the same technology, and eliminating the parasitic effect introduced by a probe from a physical level; zero offset voltage and a temperature drift compensation value are obtained through initial offset calibration, and sensing signals are continuously corrected in the aging process; extracting the source electrode-substrate junction leakage current of the spatially coupled target transistor through differential processing, completing multi-dimensional normalization according to the cavity temperature and the grid bias voltage, and finally generating a normalized leakage current sequence capable of directly representing the intrinsic degradation trend of the device; the sequence supports continuous central difference operation, so that the inflection point moment of the leakage current is accurately identified, the residual service life is predicted according to the inflection point moment, and a degradation fingerprint spectrum is generated; therefore, the method realizes undisturbed, synchronous, in-situ and quantitative sensing of the leakage current of the key node under the real aging stress.

The present invention discloses a transistor with low leakage current and a method for manufacturing the same. The transistor includes a substrate, a gate, multiple spacer layers, multiple liner dielectric layers, a source, and a drain. The gate has a first dielectric constant. The multiple spacer layers have a second dielectric constant. The multiple liner dielectric layers have a third dielectric constant. The source and the drain are adjacent to the multiple spacer layers and are arranged in opposite directions relative to the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other. Therefore, compared with the prior art, the present invention can more effectively reduce gate-induced drain leakage current, short channel effect, off current, or junction leakage current.

A p-GaN gate tunnel junction HEMT includes a nucleation layer, buffer layer, nitride-based channel layer, nitride-based barrier layer, p-type GaN layer, gate electrode, source electrode, drain electrode, and surface passivation layer. The nucleation and buffer layers are disposed on a substrate, with the nitride-based channel layer above. The nitride-based barrier layer is positioned on the nitride-based channel layer, creating a 2DEG channel between the channel and barrier layers. The p-type GaN layer is positioned on the nitride-based barrier layer. The gate electrode is positioned on the p-type GaN layer. The source electrode forms a tunnel junction with the 2DEG channel, and the drain electrode is placed on the nitride-based barrier layer. The passivation layer covers the nitride-based barrier layer with portions between the gate-source and gate-drain regions.

The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source / drain (S / D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.

To provide a protection circuit with a suitable structure in order to take advantage of characteristics of a display device including an oxide semiconductor that has excellent operation characteristics and can be manufactured at low temperature.SOLUTION: A nonlinear element 30a forming a protection circuit includes a gate insulating layer 37 that covers a gate electrode 15, a pair of a first wiring layer 38 and a second wiring layer 39 in which an end part overlaps with the gate electrode 15 on the gate insulating layer 37 and a second oxide semiconductor layer 40 and a conductive layer 41 are stacked, and a first oxide semiconductor layer 36 that overlaps with at least the gate electrode 15 and is in contact with a part of a side surface part and an upper surface part of the conductive layer 41 in the gate insulating layer 37, the first wiring layer 38, and the second wiring layer 39 and a side surface part of the second oxide semiconductor layer 40. By forming a junction between the oxide semiconductor layers with different physical properties on the gate insulating layer 37, a stable operation becomes possible as compared to Schottky junction, junction leakage is reduced, and characteristics of the nonlinear element 30a can be improved.SELECTED DRAWING: Figure 5

The invention relates to an SPICE model extraction method for improving reverse bias pn junction leakage current precision, and the method comprises the steps: adding a mathematical fitting formula related to the size to a key parameter jtssgd for adjusting the reverse bias pn junction leakage current in a BSIM4 model, introducing fitting parameters which are strongly related to the effective channel length, the effective channel width and the device area of a device, and carrying out the extraction of the reverse bias pn junction leakage current precision. The method can accurately capture and fit the complex behavior of the leakage current along with the size change of the device, achieves the accurate modeling of the cut-off leakage current caused by the reverse bias pn junction through the adjustment of the fitting parameters, and improves the simulation precision of the model for the cut-off leakage current of devices of different sizes.

The embodiment of the invention provides a semiconductor device and a forming method thereof. The semiconductor device comprises a substrate, a gate structure and a conductive plug. The gate structure is formed in the substrate and includes a conductive layer and an insulating cap layer. The conductive layer is provided with a first part and a second part extending from the upper surface of the first part along the vertical direction, so that a segment difference is formed between the upper surface of the first part and the upper surface of the second part. The insulating cover layer covers the upper surfaces of the first part and the second part. According to the semiconductor device and the forming method thereof provided by the embodiment of the invention, the occurrence opportunity of junction leakage current of the semiconductor device can be effectively reduced, and the efficiency and the reliability of the semiconductor device are further improved.

The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source / drain (S / D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.

Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source / drain depths, and / or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.

The invention provides a semiconductor structure and a preparation method thereof, the semiconductor structure comprises a plurality of semiconductor devices arranged in parallel, each semiconductor device comprises at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, and the metal interconnection structure is arranged in a dielectric layer; the second well region is arranged in the substrate between the first well regions of the adjacent semiconductor devices; the insulating layer is arranged on the dielectric layer between the adjacent semiconductor devices and extends to the two sides to a part of the metal interconnection structure; the passivation layer is arranged on the insulating layer; the first groove is formed in the surface of the metal interconnection structure and exposes part of the metal interconnection structure; and the second groove surrounds the first groove and is arranged on the metal interconnection structure, and a part of the insulating layer is exposed. According to the semiconductor structure and the preparation method thereof provided by the invention, the influence of environment humidity on junction leakage current measurement can be reduced.

The application discloses a gallium oxide field effect transistor based on a heterojunction hole super-injection and a preparation method thereof, and solves the problem of small current density of the gallium oxide field effect transistor. The P-type heterostructure region is additionally arranged, the Ga2O3 epitaxial layer channel is arranged on the Ga2O3 substrate, the source metal and the P-type heterostructure material region are arranged on two ends of the Ga2O3 epitaxial layer channel, and the P-type heterostructure material region and the Ga2O3 epitaxial layer channel form a hetero-PN junction. The method comprises the following steps: pretreatment, mesa etching, source metal growth, ohmic annealing, drain heterojunction and electrode material growth, preparation and opening of the gate dielectric, and growth of the gate metal. The P-type heterostructure material and the channel form a heterojunction, the drain metal and the P-type heterostructure material adopt a self-alignment process, the p-type NiO material is used as the p-type gallium oxide material instead, the p-NiO and n-Ga2O3 hole super-injection effect is utilized, the reverse breakdown voltage is improved, and the forward conduction resistance is reduced. The application can be applied to power electronic devices such as inverters with a working voltage greater than 5V.

Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source / drain depths, and / or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.

The invention provides an electrical test structure and a test method for monitoring the junction performance of an MOS (Metal Oxide Semiconductor) transistor, and the structure of the test unit is provided with a structure similar to that of the MOS transistor, namely, the test unit comprises a substrate layer, a well layer, a gate structure, a doped region and a test bonding pad, but the doped region is divided into two regions with opposite doping types, so that the junction performance of the MOS transistor is monitored. The junction capacitance, the junction breakdown voltage and the junction leakage current between the first conductive type doped region and the well layer, the junction breakdown voltage and the junction leakage current between the second conductive type doped region and the well layer can be monitored by connecting different types of required voltages into the first test bonding pad and the second test bonding pad, so that the junction structure characteristics of the MOS transistor can be comprehensively monitored, and the reliability of the MOS transistor can be improved through a process reliability test. The junction capacitance, the junction breakdown voltage and the junction leakage current of the MOS transistor junction are effectively monitored, and risk investigation can be carried out on related processes in the MOS transistor process.

The utility model discloses a GIP circuit and a touch display device. The GIP circuit comprises a forward scanning starting unit, a reverse scanning starting unit, a potential holding unit, a pull-down unit and a driving output unit, the forward-scanning starting unit and the reverse-scanning starting unit are connected together and then electrically connected with the potential maintaining unit. The potential holding unit, the pull-down unit and the driving output unit are electrically connected to form a first common contact; the potential maintaining unit is used for being started in the touch control time period so as to maintain the potential of the first common connection point to be high potential. By arranging the potential holding unit, the grid end of the driving output unit in the touch control time period is kept at a high potential, it is guaranteed that the output voltage of the driving output unit meets the requirement of the display time period after switching to the display time period, and therefore the problem of display cross grains caused by electric leakage of a common contact in the touch control time period is solved.

Utilizing the characteristics of display devices that use oxide semiconductors, which have excellent operating characteristics and can be manufactured at low temperatures A protection circuit with an appropriate configuration is required. A gate insulating layer 37 covering a gate electrode 15, and a gate insulating layer 37 on the gate insulating layer 37 The gate electrode 15 and the end of the gate electrode 15 are overlapped with each other, and the second oxide semiconductor layer 40 and the conductive layer 41 are stacked. The pair of first wiring layer 38 and second wiring layer 39 and the gate insulating layer 15 overlap each other. The side and upper portions of the conductive layer 41 in the edge layer 37, the first wiring layer 38, and the second wiring layer 39 The first oxide semiconductor layer 36 is in contact with a part of the surface portion and a side portion of the second oxide semiconductor layer 40. The protection circuit is configured using a nonlinear element 30a. By forming a junction between oxide semiconductor layers having different physical properties on the gate insulating layer 37, Compared to Schottky junctions, this allows for more stable operation, reduces junction leakage, and The characteristics of the linear element 30a can be improved.

The present invention discloses a manufacturing method and structure of a low dark current phototransistor, belonging to the semiconductor field. The present invention adopts a design of a high-concentration boron region and a manufacturing process of low-resistivity epitaxy. The process includes the following steps: preparation of a low-resistivity epitaxial wafer, wafer cleaning, field oxidation, high-concentration boron region implantation, high-concentration boron region diffusion, light-boron base region implantation, light-boron base region diffusion, emitter region implantation, emitter region diffusion, antireflection film layer deposition, photolithography and etching of the contact hole region, metal deposition, photolithography and etching of the metal pad region, and metallization alloying. The structure of the obtained chip is of the N+-N--P--N+ type. The present invention appropriately reduces the resistivity of the top-layer epitaxy, increases the doping concentration on the collector region side, effectively reduces the collector junction leakage current; at the same time, a high-concentration boron region structure is added in the chip design, which increases the doping concentration on the base region side of the collector junction, effectively reduces the collector junction leakage current, improves the dark current performance of the chip, and meets the application requirements in the high-temperature field.

Embodiments of the present disclosure provide a method, a testing device, and a storage medium for determining the thickness of a diffusion layer. The method includes: obtaining a first doping concentration of a first semiconductor in a PN junction and a second doping concentration of a second semiconductor in the PN junction; wherein the first doping concentration is less than the second doping concentration; determining an equivalent resistance of the depletion region and an equivalent resistance of the bulk phase of the PN junction; determining a first bulk phase length of the first semiconductor according to the first doping concentration, the equivalent resistance of the bulk phase, and the junction area of the PN junction; determining a depletion region length according to the first doping concentration, the second doping concentration, and the equivalent resistance of the depletion region; and determining the thickness of the diffusion layer of the first semiconductor according to the length of the first semiconductor, the first bulk phase length, and the depletion region length. Embodiments of the present disclosure can accurately measure the thickness of the diffusion layer of minority carriers in a PN junction, thereby improving junction leakage and accurately calculating the carrier diffusion coefficient.

A method includes forming a well region in a substrate; forming a first implant region in the substrate, the first implant region; forming a second implant region in the well region; forming a first shallow trench isolation (STI) region in the substrate; forming first deep trench isolation (DTI) regions extending downwards from the first STI region into the well region; forming a second STI region in the substrate; forming second DTI regions extending downwards from the second STI region; forming a third STI region in the substrate; forming third DTI regions extending downwards from the third STI region; forming a gate electrode; forming a first source / drain region in the first implant region and in contact with the third STI region; and forming second source / drain region in the second implant region and between the first STI region and the second STI region.

The invention relates to a gallium oxide field effect transistor with reverse resistance capability. The transistor comprises a gallium oxide substrate and a transistor unit body, and the transistor unit body comprises a drain end function unit and a gate end function unit. The drain end function unit comprises a drain end first function area adjacent to one side of the gate end function unit and drain electrode metal used for leading out a drain electrode, and the drain end first function area at least comprises a p-type oxide island and a Schottky island which are sequentially arranged in the first direction; the p-type oxide island is in contact with the gallium oxide substrate and forms a drain end heterojunction, the drain electrode metal is in adaptive connection with the p-type oxide island, and the Schottky island is formed at least based on Schottky contact of the drain electrode metal and a corresponding area of the gallium oxide substrate. According to the gallium oxide field effect transistor, the gallium oxide field effect transistor has reverse resistance capability and has the characteristics of high voltage resistance and low loss, and the application range of the gallium oxide field effect transistor is widened.

In order to take advantage of the characteristics of a display device including an oxide semiconductor, which has excellent operation characteristics and can be manufactured at low temperatures, a protection circuit or the like having an appropriate structure is needed.SOLUTION: A protective circuit is formed using a non-linear device 105a including a gate insulating layer 102 covering gate electrodes 101, first oxide-semiconductor layers 103 overlapping with the gate electrodes 101 over the gate insulating layer 102, and a pair of first and second wiring layers 38 and 39 whose end portions overlap with the gate electrodes over the first oxide-semiconductor layers 103 and in which a conductive layer 104a and a second oxide-semiconductor layer 170a are stacked. When a junction of oxide-semiconductor layers having different physical properties is formed over the gate insulating layer 102, stable operation can be performed as compared to a Schottky junction, junction leakage can be reduced, and characteristics of a non-linear device 170a can be improved.SELECTED DRAWING: Figure 5

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps of: after etching and opening a barrier dielectric layer of a silicide barrier layer and before pre-amorphization injection, removing a bottom oxide layer exposed out of the barrier dielectric layer by wet etching, and under the condition of ensuring that the influence on the process is small, improving the performance of the semiconductor device. The problem that the top height of the device isolation structure at the vertex angle of the source-drain region is reduced due to excessive loss of the device isolation structure at the vertex angle of the source-drain region in the process of removing the bottom oxide layer exposed by the barrier dielectric layer through wet etching can be avoided, the top surface height of the device isolation structure at the vertex angle of the source-drain region is ensured, and excessive top side walls of the source-drain region are prevented from being exposed; therefore, the problem that the formed metal silicide extends downwards from the top surface of the vertex angle of the source-drain region to the side wall of the vertex angle of the source-drain region can be avoided, the weakness of the vertex angle of the active region is improved, the junction leakage current of the device is reduced, and the performance of the device is improved.

This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes: a plurality of semiconductor devices arranged in parallel, each semiconductor device including at least one first well region disposed in a substrate and a metal interconnect structure disposed on the substrate, the metal interconnect structure being disposed within a dielectric layer; a second well region disposed in the substrate between the first well regions of adjacent semiconductor devices; an insulating layer disposed on the dielectric layer between adjacent semiconductor devices and extending laterally onto portions of the metal interconnect structure; a passivation layer disposed on the insulating layer; a first groove disposed on the surface of the metal interconnect structure, exposing a portion of the metal interconnect structure; and a second groove disposed around the first groove on the metal interconnect structure, exposing a portion of the insulating layer. The semiconductor structure and its fabrication method provided by this invention can reduce the influence of ambient humidity on junction leakage current measurement.