8 results about "Junction leakage" patented technology

The application relates to the field of semiconductors and discloses a semiconductor device and a forming method of the semiconductor device. The semiconductor device comprises a substrate, a source region and a drain region, and a halo injection region. The halo injection region comprises a first halo injection sub-region for preventing direct channel penetration and a second halo injection sub-region for adjusting junction leakage current. The first halo injection sub-region covers the bottom and / or side of a preset region, the preset region comprising the source region and / or the drain region, and a depletion layer ends in the first halo injection sub-region. The second halo injection sub-region covers the bottom and / or side of the first halo injection sub-region, and a minority carrier diffusion layer ends in the second halo injection sub-region. The doping concentration of the second halo injection sub-region is greater than that of the first halo injection sub-region. The semiconductor device provided by the application can adjust the interface performance between the substrate and the source region and / or the drain region by setting the halo injection region, and can solve the contradiction between direct channel penetration and pn junction leakage.

The invention discloses a chip aging test system and method, and the method comprises the steps: constructing a main buried layer and a reference buried layer in a silicon substrate in a chip manufacturing stage, enabling a sensing structure and a transistor to share a substrate and the same technology, and eliminating the parasitic effect introduced by a probe from a physical level; zero offset voltage and a temperature drift compensation value are obtained through initial offset calibration, and sensing signals are continuously corrected in the aging process; extracting the source electrode-substrate junction leakage current of the spatially coupled target transistor through differential processing, completing multi-dimensional normalization according to the cavity temperature and the grid bias voltage, and finally generating a normalized leakage current sequence capable of directly representing the intrinsic degradation trend of the device; the sequence supports continuous central difference operation, so that the inflection point moment of the leakage current is accurately identified, the residual service life is predicted according to the inflection point moment, and a degradation fingerprint spectrum is generated; therefore, the method realizes undisturbed, synchronous, in-situ and quantitative sensing of the leakage current of the key node under the real aging stress.

Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source / drain depths, and / or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.

The invention provides a semiconductor structure and a preparation method thereof, the semiconductor structure comprises a plurality of semiconductor devices arranged in parallel, each semiconductor device comprises at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, and the metal interconnection structure is arranged in a dielectric layer; the second well region is arranged in the substrate between the first well regions of the adjacent semiconductor devices; the insulating layer is arranged on the dielectric layer between the adjacent semiconductor devices and extends to the two sides to a part of the metal interconnection structure; the passivation layer is arranged on the insulating layer; the first groove is formed in the surface of the metal interconnection structure and exposes part of the metal interconnection structure; and the second groove surrounds the first groove and is arranged on the metal interconnection structure, and a part of the insulating layer is exposed. According to the semiconductor structure and the preparation method thereof provided by the invention, the influence of environment humidity on junction leakage current measurement can be reduced.

Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source / drain depths, and / or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.

The invention relates to a gallium oxide field effect transistor with reverse resistance capability. The transistor comprises a gallium oxide substrate and a transistor unit body, and the transistor unit body comprises a drain end function unit and a gate end function unit. The drain end function unit comprises a drain end first function area adjacent to one side of the gate end function unit and drain electrode metal used for leading out a drain electrode, and the drain end first function area at least comprises a p-type oxide island and a Schottky island which are sequentially arranged in the first direction; the p-type oxide island is in contact with the gallium oxide substrate and forms a drain end heterojunction, the drain electrode metal is in adaptive connection with the p-type oxide island, and the Schottky island is formed at least based on Schottky contact of the drain electrode metal and a corresponding area of the gallium oxide substrate. According to the gallium oxide field effect transistor, the gallium oxide field effect transistor has reverse resistance capability and has the characteristics of high voltage resistance and low loss, and the application range of the gallium oxide field effect transistor is widened.

In order to take advantage of the characteristics of a display device including an oxide semiconductor, which has excellent operation characteristics and can be manufactured at low temperatures, a protection circuit or the like having an appropriate structure is needed.SOLUTION: A protective circuit is formed using a non-linear device 105a including a gate insulating layer 102 covering gate electrodes 101, first oxide-semiconductor layers 103 overlapping with the gate electrodes 101 over the gate insulating layer 102, and a pair of first and second wiring layers 38 and 39 whose end portions overlap with the gate electrodes over the first oxide-semiconductor layers 103 and in which a conductive layer 104a and a second oxide-semiconductor layer 170a are stacked. When a junction of oxide-semiconductor layers having different physical properties is formed over the gate insulating layer 102, stable operation can be performed as compared to a Schottky junction, junction leakage can be reduced, and characteristics of a non-linear device 170a can be improved.SELECTED DRAWING: Figure 5

This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes: a plurality of semiconductor devices arranged in parallel, each semiconductor device including at least one first well region disposed in a substrate and a metal interconnect structure disposed on the substrate, the metal interconnect structure being disposed within a dielectric layer; a second well region disposed in the substrate between the first well regions of adjacent semiconductor devices; an insulating layer disposed on the dielectric layer between adjacent semiconductor devices and extending laterally onto portions of the metal interconnect structure; a passivation layer disposed on the insulating layer; a first groove disposed on the surface of the metal interconnect structure, exposing a portion of the metal interconnect structure; and a second groove disposed around the first groove on the metal interconnect structure, exposing a portion of the insulating layer. The semiconductor structure and its fabrication method provided by this invention can reduce the influence of ambient humidity on junction leakage current measurement.