489 results about "Floating diffusion" patented technology

A time-of-flight pixel circuit includes a photodiode configured to generate charge in response to modulated light reflected from an object. First and second transfer transistors are coupled to the photodiode. The first transfer transistor transfers a first portion of charge from the photodiode in response to a first modulation signal and the second transfer transistor transfers a second portion of charge from the photodiode in response to a second modulation signal. The second modulation signal is an inverted first modulation signal. A first floating diffusion is coupled to the first transfer transistor to receive the first portion of charge in response to a first modulation signal. Each one of a first plurality of sample and hold transistors is coupled between a respective one of a first plurality of memory nodes and the first transfer transistor.

An image sensor may include an array of imaging pixels arranged in rows and columns. Each imaging pixel may include a photodiode, an overflow capacitor, an overflow transistor that is interposed between the photodiode and the overflow capacitor, a floating diffusion region, a transfer transistor that is interposed between the photodiode and the floating diffusion region, a voltage supply, and a reset transistor that is interposed between the floating diffusion region and the voltage supply. The voltage supply may provide a voltage at a first magnitude that is less than the pinning voltage for a first portion of a reset period and may provide the voltage at a second magnitude that is greater than the pinning voltage for a second portion of the reset period.

A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.

A control circuitry region of a pixel sensor of a semiconductor device includes a plurality of conversion gain circuits that may be selectively activated and / or deactivated in various combinations to enable a plurality of sequential conversion gain operations to be performed across an exposure operation of the semiconductor device. The control circuitry region may include a first conversion gain circuit and a second conversion gain circuit that are connected to a floating diffusion node of the pixel sensor in parallel. The selectable parallel conversion gain circuits enable sequential conversion gain operations to be performed for the pixel sensor such that the capacitance in the pixel sensor may be gradually increased through the conversion gain operations. Gradually increasing the capacitance in the pixel sensor across the sequential conversion gain operations provides for smaller signal-to-noise ratio (SNR) drops, which enables a low SNR drop to be achieved for the pixel sensor.

An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

An image sensor structure including a substrate, a pixel structure, and a deep trench isolation (DTI) structure is provided. The substrate includes a first side and a second side opposite to each other. The pixel structure includes a transfer transistor, a light sensing device, and a floating diffusion region. The transfer transistor includes a first gate. The first gate is disposed on the first side of the substrate. The light sensing device is disposed in the substrate and is located on one side of the first gate. The floating diffusion region is disposed in the substrate and is located on another side of the first gate. The DTI structure extends into the substrate from the second side of the substrate. The top-view pattern of the floating diffusion region does not overlap the top-view pattern of the DTI structure.

An image sensor is provided. The image sensor includes: a photoelectric conversion region in a semiconductor substrate; a photocharge collection region provided in the photoelectric conversion region; a floating diffusion region in the semiconductor substrate that is spaced apart from the photocharge collection region along a vertical direction; a charge multiplication region between the photocharge collection region and the floating diffusion region; and a vertical gate electrode which extends into the semiconductor substrate and overlaps the photocharge collection region along the vertical direction. A side surface of the vertical gate electrode is adjacent to the floating diffusion region and the charge multiplication region.

The present technology relates to a solid-state image sensor, an imaging device, and an electronic device capable of switching FD conversion efficiency in all pixels of a solid-state image sensor. A photodiode performs photoelectric conversion on incident light. A floating diffusion (FD) stores charge obtained by the photodiode. FD2, which is a second FD to which the capacity of an additional capacitor MIM is added, adds the capacity to the FD. The additional capacitor MIM is constituted by a first electrode formed by a wiring and a second electrode formed by a metallic light blocking film provided on a surface of a substrate on which the photodiode is formed. Switching between the FD and FD+FD2 allows switching of the FD conversion efficiency. The present technology is applicable to a CMOS image sensor.

A solid-state imaging device includes: a pixel array in which a plurality of pixels are arranged in rows and columns; and a first power supply line. Each of the plurality of pixels includes a photoelectric converter, a floating diffusion, a capacitance accumulator, a first transfer transistor, an overflow transistor, a second transfer transistor, a first reset transistor, and an amplifier transistor. The solid-state imaging device further includes a resetter for resetting the floating diffusion and the capacitance accumulator at voltages different from each other.

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor comprises a substrate which is divided into a plurality of active regions by a shallow trench isolation structure; the photodiode, the charge storage region and the floating diffusion region are arranged in the substrate at intervals; the global transmission grid is arranged between the photodiode and the charge storage region and comprises a first branch arranged on the active region and a second branch arranged on the shallow trench isolation structure; the transfer gate is arranged between the charge storage region and the floating diffusion region and comprises a first gate arranged on the active region and a second gate arranged on the shallow trench isolation structure; the first mask layer is arranged on the global transmission gate and the transfer gate, and the second mask layer is arranged on the first mask layer on the first branch and the first gate; the shading structure covers the first subsection, the charge storage area and part of the transfer grid electrode. According to the image sensor and the manufacturing method thereof, the parasitic light response is improved, and the manufacturing yield is improved.

A pixel array includes: unit pixel groups; and two column lines provided for each column. Each of the unit pixel groups includes rows, a first pixel group comprising a plurality of pixels, a second pixel group comprising a plurality of pixels. The first pixel group and the second pixel group are arranged in a row direction. A pixel signal is output by simultaneously reading out: unit pixel groups that are connected to a first column line and that do not share a first floating diffusion region, and unit pixel groups that are connected to a second column line different from the first column line and that do not share a second floating diffusion region. At least one of the first floating diffusion region and the second floating diffusion region is between a dual conversion transistor and a reset transistor.

Various embodiments of the present disclosure are directed towards a semiconductor device including a plurality of photodetectors disposed within a substrate, where the substrate has a front-side opposite a back-side. The semiconductor device includes a floating diffusion node disposed in the substrate, where the photodetectors are disposed around the floating diffusion node. A trench isolation structure is disposed within the substrate and laterally surrounds the photodetectors. The trench isolation structure includes a first isolation structure disposed in the substrate and having a first depth, where the first isolation structure is disposed between adjacent photodetectors and is laterally offset from the floating diffusion node. The trench isolation structure includes a second isolation structure extending from the back-side of the substrate towards the floating diffusion node, where the second isolation structure directly overlies the floating diffusion node and has a second depth less than the first depth.

An image sensor includes a substrate, a first floating diffusion region and a second floating diffusion region in the substrate and spaced apart from each other, a ground region in the substrate and spaced apart from the first floating diffusion region and the second floating diffusion region, a first interconnection line on the substrate and connecting the first floating diffusion region and the second floating diffusion region, and a second interconnection line on the substrate and connected to the ground region, where the first interconnection line is at a first level and the second interconnection line is at a second level that is different from the first level.

First and second modulation gates disposed adjacent a silicon photoconversion structure generate, throughout the exposure interval, alternating first and second electrostatic fields that compel photocharge generated within the silicon photoconversion structure to the first and second storage diodes, respectively. Upon conclusion of the exposure interval, accumulated photocharge within the first and second storage diodes is transferred to first and second floating diffusion nodes, respectively, as part of a correlated-double-sampling readout with respect to each of the floating diffusion nodes.

An image sensor includes a pixel isolation structure in a semiconductor substrate. The pixel isolation structure defines a plurality of pixel regions, a photoelectric conversion region in the semiconductor substrate on each of the pixel regions, a floating diffusion region in the semiconductor substrate and spaced apart from the photoelectric conversion region. A transfer gate electrode is disposed between the photoelectric conversion region and the floating diffusion region on each of the pixel regions. A dielectric layer is disposed on the semiconductor substrate and covers the transfer gate electrode. A plurality of active patterns spaced apart from each other is disposed on a top surface of the dielectric layer. A plurality of pixel transistors is disposed on corresponding active patterns. In a plan view, at least one of the active patterns overlaps a portion of the pixel isolation structure.

Provided is a low-cost light detection device with large signal detection capacity. The light detection device includes a first semiconductor substrate including a first semiconductor layer and a second semiconductor layer stacked on top of each other. The first semiconductor layer includes a photoelectric conversion region and a floating diffusion region that accumulates charges resulting from photoelectric conversion in the photoelectric conversion region, and the second semiconductor layer includes a capacitor that accumulates the charges resulting from photoelectric conversion in the photoelectric conversion region.

The invention provides an image sensor. The image sensor comprises a substrate; the transmission gate is located on the substrate, and the floating diffusion region is located in the substrate on one side of the transmission gate; the source following grid electrode is located on the substrate, and the source following source region and the source following drain region are located in the substrate on the two sides of the source following grid electrode respectively; the MOM capacitor is located on the side, away from the substrate, of the transmission grid electrode and the source following grid electrode, and the floating diffusion region and the source following source region are electrically connected through the MOM capacitor. According to the invention, the MOM capacitor is connected between the floating diffusion region and the source following source region, so that the parasitic capacitance of the floating diffusion region can be reduced, the charge conversion gain of the floating diffusion region can be increased, and the signal-to-noise ratio of the device can be improved, thereby improving the reading noise reduction capability of the image sensor.

An image sensor includes a substrate, a pixel region defined by an isolation structure in the substrate, a first floating diffusion region on the pixel region, a source follower gate electrode on the substrate, and a first buried line on the isolation structure. The first buried line electrically connects the first floating diffusion region to the source follower gate electrode, and the first buried line is disposed in the substrate. The first buried line includes a first line portion extending from the first floating diffusion region in a first direction, and a second line portion extending from the source follower gate electrode in a second direction that intersects the first direction.

An image sensor comprising a first die, a second die, and a plurality of pixel cells arranged in rows and columns to form a pixel cell array is described. The first die and the second die are stacked to form a bonding interface disposed therebetween. A first pixel cell included in the plurality of pixel cells includes a photodiode, disposed within the first die, configured to photogenerate image charge in response to incident light, a flighting diffusion, disposed within the first die, coupled to receive the image charge, and a lateral overflow integration capacitor, disposed within the second die, selectively coupled to the floating diffusion through a first bonding connection formed at the bonding interface.

The invention provides a signal processing method of an image sensor, which comprises the following steps of: starting a transfer transistor by using a relatively low first starting voltage during LCG to read an image signal of the LCG, and starting the transfer transistor by using a relatively high second starting voltage during HCG to read an image signal of the HCG. Wherein the first turn-on voltage is smaller than the voltage for completely transferring the full well charge of the photodiode to the floating diffusion region under the LCG, so as to ensure that the charge in the photodiode is not completely emptied when the image signal of the LCG is read; the second turn-on voltage is greater than or equal to the voltage for completely transferring the residual charge of the photodiode to the floating diffusion region under the HCG, so that the charge in the photodiode can be completely transferred under low illumination. Compared with the prior art, the method can ensure that charges in the FD cannot exceed a readable range during LCG and HCG, read data distortion cannot be caused, the storage area does not need to be increased, the FD potential change amplitude is not too large during two times of charge transfer, noise can be reduced, the problem of transverse stripes of a lamp tube can be minimized, and the HDR image quality can be improved.

The embodiment of the invention provides a semiconductor structure, a manufacturing method of the semiconductor structure and an image sensor. The semiconductor structure comprises a substrate; a transmission gate formed on the surface of the substrate; the floating diffusion region and the transition doping region are formed in the substrate; wherein the transition doped region is located between the projection of the transmission gate on the substrate and the floating diffusion region; the doping concentration of the transition doping region is smaller than that of the floating diffusion region; the transition doped region comprises a first doped region and a second doped region which are formed based on an ion implantation process; the doping type of the first doping region is different from that of the floating diffusion region; the doping type of the second doped region is the same as that of the floating diffusion region; in the normal direction of the substrate, the ion implantation depth of the second doped region is larger than that of the first doped region. According to the embodiment of the invention, the occurrence of gate-induced drain leakage is reduced, and the imaging quality of the CMOS image sensor is improved.

An image sensor includes: a substrate having a first surface and a second surface; a deep element isolation pattern in the substrate to define a plurality of pixel regions; a shallow element isolation pattern adjacent to the first surface to define a first active region, a second active region, and a third active region separated between the plurality of pixel regions; a floating diffusion region in the first active region; a control source / drain region in the second active region; a source follower gate on the third active region; and a gate insulating film between the source follower gate and the third active region. The source follower gate and the gate insulating film extend to the control source / drain region. The source follower gate passes through the gate insulating film and is in direct contact with the control source / drain region.

An image sensor includes a pixel array in which a plurality of pixels are arranged, wherein each of the pixels includes a photodiode, a transfer transistor, first to third floating diffusion nodes, a first capacitor, a second capacitor, a third capacitor, a first switch transistor, a second switch transistor, and a reset transistor. The second switch transistor is configured to turn off in a first period and to turn on in a second period of an exposure period of the photodiode, and the reset transistor is configured to turn on in the first period and to turn off in the second period of the exposure period of the photodiode.

Image sensing devices are disclosed. In an embodiment, an image sensing device includes a substrate including a first surface and a second surface facing or opposite to the first surface; a plurality of photoelectric conversion regions arranged adjacent to each other within the substrate and configured to convert incident light received through the first surface into photocharges; a pixel isolation structure configured to isolate adjacent photoelectric conversion regions of the photoelectric conversion regions from each other within the substrate; a floating diffusion region disposed between the plurality of photoelectric conversion regions and in contact with the second surface of the substrate; and a plurality of transfer gates disposed on side surfaces of the plurality of photoelectric conversion regions so as not to vertically overlap the plurality of photoelectric conversion regions.

The invention provides an image sensor and a control method thereof, a pixel arrangement structure and electronic equipment, the image sensor comprises a photosensitive unit, a reset unit, a readout unit and a decoupling unit, the reset unit and the photosensitive unit are coupled to a floating diffusion node, the decoupling unit is arranged corresponding to a signal fluctuation node in a pixel block, and the readout unit is arranged corresponding to the signal fluctuation node in the pixel block. Adjusting the to-be-read signal transferred to the floating diffusion node and / or adjusting the output data signal of the pixel block based on the signal fluctuation node; the read-out unit reads out a signal corresponding to the floating diffusion node. According to the image sensor, through the design of the decoupling unit, the influence on a signal fluctuation node can be adjusted, the accuracy of image data is improved, especially in a pixel circuit with an overflow signal, based on the design of the decoupling unit, the accuracy of a finally output data signal can be effectively improved, and then the image quality is optimized; and device performance is improved.

Disclosed herein are fixed pattern noise (FPN) reduction techniques in image sensors operated with pulsed illumination. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to a first charge at a first floating diffusion, the first charge corresponding to a first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to a second charge at the second floating diffusion, the second charge corresponding to a second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.

The image sensor may include a plurality of pixels, each of which may include a photodiode having a charge storage region (“PD”), a floating diffusion region (“FD”), and a vertical charge transfer region between the PD and the FD. The vertical charge transfer region may include a first charge modulation region (“P1”), a second charge modulation region (“P2”), and a third charge modulation region (“P3”). The image sensor may operate in a global shutter mode, in which P2 may be used as an in-pixel charge memory region for temporarily storing charge during the transfer of charge from the PD to the FD via P1, P2, and P3.

An image sensor and a readout method for a pixel circuit thereof are provided. In the pixel circuit, a first transistor is coupled between a floating diffusion portion and a first capacitor, and a second transistor is coupled between the first transistor and a second capacitor. A readout cycle of the pixel circuit includes a high conversion gain (HCG) readout operation, an all-capacitor readout operation, a first readout stage, a second readout stage, and a third readout stage. The HCG readout operation is used to read out an HCG sensing result. The first readout stage and the second readout stage are used to read out a first medium illumination sensing result. The second readout stage and the third readout stage are used to read out a low conversion gain (LCG) sensing result. The all-capacitor readout operation is used to read out a high illumination sensing result.

An image sensor includes a substrate having a first surface and a second surface opposing the first surface, a first isolation pattern defining a plurality of shared pixel regions in the substrate, and a plurality of shared pixels respectively in the plurality of shared pixel regions. Each of the plurality of shared pixels includes a second isolation pattern defining a plurality of unit pixel regions in a corresponding shared pixel region, the second isolation pattern having an open region in a plan view, a plurality of photodiodes in the plurality of unit pixel regions, respectively, a plurality of floating diffusion regions in the plurality of unit pixel regions, and an inter-pixel overflow (IPO) gate overlapping the open region in the plan view. Each of the plurality of floating diffusion regions in each of the plurality of shared pixels is spaced apart from the IPO gate.

This disclosure provides a semiconductor structure, its fabrication method, and an image sensor, relating to the field of image sensor technology, and aims to improve the image quality of image sensors using this semiconductor structure. The semiconductor structure includes: a substrate and at least one semiconductor unit; the at least one semiconductor unit is disposed on the substrate; the semiconductor unit includes a first semiconductor layer, a gate layer, and a gate dielectric layer; the first semiconductor layer includes a photoelectric conversion portion, a channel portion, and a floating diffusion portion; the channel portion surrounds at least a portion of the photoelectric conversion portion; the floating diffusion portion is disposed on the side of the channel portion away from the substrate and is spaced apart from the photoelectric conversion portion; the gate layer at least penetrates a portion of the first semiconductor layer and is disposed on the side of the channel portion away from the photoelectric conversion portion; the gate dielectric layer is disposed between the gate layer and the channel portion. The aforementioned image sensor is used to capture and convert image information.