1510 results about "Control grid" patented technology

A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.

A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate having source and drain regions commonly connected to the floating diffusion region. The gate has an intrinsic capacitance which, when the gate is activated, is added to the capacitance of the floating diffusion region, providing a low conversion gain readout. When the gate is off, the floating diffusion region capacitance is minimized, providing a high conversion gain readout. The gate may also be selectively switched to mid-level. At mid-level, a mid-level conversion gain, which is between the high and low conversion gains, readout is provided, but the gate still provides some capacitance to prevent the floating diffusion region from saturating.

A grid-connected power storage system for coupling a power generation system to a grid, including: a main battery for discharging stored power to the load system; at least one additional battery coupled to the main battery for discharging stored power to the load system; a bidirectional converter coupled to the main and additional batteries, and including a plurality of switches for performing a conversion between a DC link voltage, between the power generation system and the grid, and a battery voltage, a first switch of the plurality of switches corresponding to the main battery and a second switch of the plurality of switches corresponding to the additional battery, wherein the first and second switches are connected to each other in parallel; and an integrated controller for selectively controlling operations of the first switch and the second switch based on an amount of power used by the load system.

Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

The invention discloses a composite dielectric grating MOSFET based dual-transistor light-sensitive detector. Each of the unit detectors comprises two transistors, wherein the two transistors comprise a photoreceptive transistor and a reading transistor which are used for implementing the photoreceptive function and the reading function respectively, both of the two transistors are formed above a composite dielectric grating MOSFET substrate P-type semiconductor material (1) and are separated through shallow trench isolation (STI), a bottom layer of an insulating dielectric material, a top layer of the insulating dielectric material and a control grid (2) are arranged above the substrate P-type semiconductor material respectively, a photoelectron storage layer (4) is arranged between the two layers of insulating dielectric materials, a source/drain electrode is arranged on the reading transistor to read signals, and the two transistors are connected through the photoelectron storage layer, so that the reading transistor can read photoelectrons which are stored by the photoreceptive transistor in the photoelectron storage layer through sensitization.

The invention discloses a semiconductor photosensitization device which comprises a source electrode, a drain electrode, a control grid, a floating grate region, a substrate, and a p-n node diode for connecting a floating gate region and a drain electrode. The floating grate region of the semiconductor photosensitization device is used for storing charges, and the floating grate potential of the semiconductor photosensitization device is related to light exposure intensity and time, thus, the invention can be used as a semiconductor photosensitization device. The invention also discloses production methods of the semiconductor photosensitization device and an image sensor, as well as an image sensor formed by arrays formed by the semiconductor photosensitization device. The semiconductor photosensitization device can simplify the design of a single pixel unit in a traditional image sensor and reduce the area occupied by the single pixel unit, thereby improving the pixel density of the image sensor, increasing the resolution of the image sensor and reducing the production cost of the image sensor.

The invention relates to an arrangement method of a photosensitive composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) detector. Each unit detector has a structure that N-shaped semiconductor regions are respectively arranged at both upper sides of a P-shaped semiconductor material of a substrate, two insulated dielectric material layers and a control grid electrode are respectively arranged over the substrate, a photoelectron storage layer is arranged between the two insulated dielectric material layers, the second insulated dielectric in contact with the control grid is made of a material preventing charges stored in the photoelectron storage layer from flowing into the grid electrode, a source electrode and a drain electrode are in suspended structures when photoelectrons are collected and stored to the photoelectron storage layer, the first insulated dielectric is a bottom dielectric and adopts silica, SiON or other dielectric materials with high dielectric constants, the second insulated dielectric layer is made from a top dielectric and adopts silica/silicon nitride/silica, silica, alumina or other dielectric materials with high dielectric constants, and the substrate layer or the grid electrode surface is provided with at least one transparent or semi-transparent window for detecting the wavelength of the detector.

The invention discloses a 3D (three-dimensional) NAND memory and a manufacturing method of the 3D NAND memory. The 3D NAND memory comprises multiple layers of storage arrays and multiple layers of control grid circuits, wherein each layer of the control grid circuit is electrically connected to the same layer of the storage array, so that selection of each layer of the storage array is realized; each layer of the control grid circuit is obtained by cascading a same number of transistors; grids of all the transistors of the control grid circuits are electrically connected to control wires; the number of the control wires is as the same as that of the transistors comprised in each layer of the control grid circuit; the grids of different transistors positioned on the same layer of the control grid circuit are electrically connected to different control wires. According to the 3D NAND memory, a small number of input control wires SSL select a large number of control grid layers through the control grid circuits, so that the area and the volume of the whole memory cannot be enlarged due to the increase of the number of the required layers of control grids when the storage capacity of the memory is improved due to the increase of the number of storage unit layers.

Vertical contraposed pair of floating grid and control grid is formed at side opposite to source diffusion zone in substrate. Erasing grid is formed between above source diffusion zone and contraposed grid. Selecting grid is formed is formed at side opposite to contraposed grid and erasing grid. Programming channel is extended from intermediate channel region on substrate to peripheral part of the selecting grid faced to the floating grid. Erasing channel is extended from peripheral part of the erasing grid faced to the floating grid to the source diffusion zone and the erasing grid. In some instances, the source diffusion zone is connected to the erasing grid electrically. In other instances, the floating grid stands out one or two sides of the control grid laterally. Comparing with prior art, the invention provides better programming and erasing performances with very small size of storage cell.

In accordance with one aspect of this invention, a multi charged particle beam writing apparatus includes an aperture member, in which a plurality of openings are formed, configured to form multi-beams by making portions of the charged particle beam pass through the plurality of openings; a plurality of blankers configured to perform blanking-deflect regarding beams corresponding to the multi-beams; a writing processing control unit configured to control writing processing with a plurality of beams having passed through different openings among the plurality of openings being irradiated on the target object at a predetermined control grid interval; and a dose controlling unit configured to variably control a dose of a beam associated with deviation according to a deviation amount when an interval between the plurality of beams irradiated is deviated from the control grid interval.

The invention provides a forest fire monitoring and preventing and controlling system and a control method thereof, the forest fire monitoring and preventing and controlling system divides a forest cover region into a plurality of independent preventing and controlling grids via a grid form distribution, once there is fire in the grids, the fire can be detected in time and controlled by spraying water, so that the fire is isolated within a grid range, fire spreading is effectively prevented, and the fire is completely monitored by a central supervisory control computer, so that workers can take corresponding fire protection measures according to fire situation, and early monitoring and preventing and controlling for the forest fire are implemented; simultaneously, the method of the invention is used for controlling fire, fire protection in each grid of the system is automatically detected and controlled by a monitoring terminal, even in bad communication environment or communication breakdown, fire spreading is preferably controlled, increase of fire damage caused by delayed fire protection measures in bad communication situation is avoided, and emergency handling capability of the system is enhanced.

The invention provides a field effect transistor that achieves the storage function and the preparation method, which belongs to the filed of semiconductor integrated circuit and manufacturing technology. The transistor comprises a source region, a drain region and a control grid, wherein the control grid utilizes a grid stepped construction which comprises a bottom layer of a tunneling oxidizing layer, an interface layer of a resistance-varying material layer and a top layer of a conductive electrode layer. The field effect transistor obtains an electrically programmable multi-threshold function, the source and drain currents of which are different when a same reading voltage is imposed on the grid, thereby achieving the information storage on two different states or other functions. Utilizing the invention, a plurality of devices and circuits with new functions, high performance and high reliability can be composed, thereby meeting the application of different circuit functions. Meanwhile the invention can adopt the compatibility with the CMOS technology of the conventional PN source or drain junction structure, and can also adopt the compatibility with the CMOS technology of the Schottky source or drain junction structure, with a greater flexibility in technology selection.

A household energy management system, which comprises a common controller connected with a controller for controlling grid power, a controller for controlling an in-house electric power generation device, a controller for controlling an electric storage device, a controller for controlling an electric storage device for traveling object, controllers for controlling household electric loads, and manage the energy consumption and supply by controlling the respective controllers, so that the overall energy consumption and supply in the house can be managed centrally, and the respective machines can be controlled with a single controller centrally.

An ion source for use in a mass spectrometer includes an electron emitter assembly configured to emit electron beams, wherein the electron emitter assembly comprises carbon nanotube bundles fixed to a substrate for emitting the electron beams, a first control grid configured to control emission of the electron beams, and a second control grid configured to control energies of the electron beams; an ionization chamber having an electron-beam inlet to allow the electron beams to enter the ionization chamber, a sample inlet for sample introduction, and an ion-beam outlet to provide an exit for ionized sample molecules; an electron lens disposed between the electron emitter assembly and the ionization chamber to focus the electron beams; and at least one electrode disposed proximate the ion-beam outlet to focus the ionized sample molecules exiting the ionization chamber.

The invention provides a shifting register unit, a driving method thereof, a grid drive circuit and a display device. The shifting register unit comprises a pull-up node control module, a pull-down node control module, a grid drive signal output end and a grid drive signal output module. The grid drive signal output module is connected with a pull-up node, a pull-down node, a normal phase clock signal input end and the grid drive signal output end. The pull-down node control module is connected with the pull-down node and an inverse phase clock signal input end. The shifting register unit further comprises a noise reduction module which is connected with a noise reduction control signal output end and the grid drive signal output end. The noise reduction module controlled by a noise reduction control signal is adopted with the existing grid drive signal output module to control grid drive signal denoising, and the noise reduction effect is improved.

The present invention relates to a method of forming a gate in a stack gate flash EEPROM cell. In order to preventing a lateral bird's beak from occurring in an ONO dielectric layer during a reoxidation process to be performed after a formation of a cell gate having a stack structure formed by stacking a floating gate, an ONO dielectric layer and a control gate, an oxide layer and a nitride layer are sequentially formed on an entire structure before the reoxidation and after a formation of the cell gate. The oxide layer serves to reduce a stress in depositing the nitride layer, and the nitride layer serves to prevent an occurrence of the lateral bird's beak of the ONO dielectric layer during the reoxidation process. Accordingly, the present invention prevents the lateral bird's beak of the ONO dielectric layer, thereby improving a speed of cell erase operation.

The invention relates to the technical field of semiconductor devices, and specifically relates to a VDMOS device with a relatively-low Miller capacitor and a manufacturing method of the VDMC device. According to the technical scheme of the invention, a groove filled with oxide is arranged in an epitaxial layer below grids, and the grids are controlled to be above a thick oxide layer medium, so that a semiconductor surface high electric field generated at the tail end of a control grid is reduced, and the reduction of a device voltage resistance level is prevented. The VDMOS device has the advantage that the power VDMOS new structure with the relatively-low Miller capacitor can adopt a higher JFET concentration, so that the conductive resistance of the device is effectively reduced.

The invention discloses a self-circulation aging test system and a test method for a frequency converter. The method comprises the following steps: constructing a test environment by an alternating-current power grid, a boosting transformer, a tested frequency converter, a grid-connected reactor and a grid-connected switch; controlling the alternating-current output end of the tested frequency converter to actively output a detection pulse train before grid-connected running through a grid-connected control module embedded into a tested frequency converter control circuit; identifying the phase sequence and phase of the current network voltage by detecting response current flowing through the grid-connected reactor; performing network voltage tracking and current vector control grid-connected output; feeding grid-connected output electric energy back to the rectification input end of the tested frequency converter through the boosting transformer; controlling the grid-connected output current amplitude to realize self-circulation full-power aging test of the frequency converter. By adopting the self-circulation aging test system and the test method, self-circulation full-power aging test of the frequency converter is realized under the hardware configuration condition of a general frequency converter product. The self-circulation aging test system and the test method have the advantages of easiness in configuration, convenience in operation, real simulation condition, energy saving and high aging efficiency.