282 results about "Control grid" patented technology

The invention discloses a forming method of a flash memory unit. The forming method comprises the following steps: providing a semiconductor substrate; forming a tunneling oxide layer on the semiconductor substrate; forming nanocrystalline silicon particles on the tunneling oxide layer; forming an isolation insulating layer on the tunneling oxide layer and the nanocrystalline silicon particles; and forming a control grid on the isolation insulating layer, wherein the step of forming the nanocrystalline silicon particles on the tunneling oxide layer comprises: forming an amorphous silicon layer on the tunneling oxide layer; and performing repeated seed crystal particle forming processes on the amorphous silicon layer, wherein surface annealing treatment is performed between two adjacent seed crystal particle forming processes, and an annealing process is performed after the last seed crystal particle forming process. The flash memory unit can be used for storing a large quantity of electrons, and has high performance.

The invention relates to the technical field of hygienic product production and manufacturing, and discloses an online high-speed sanitary towel spraying decoration system and method. The method includes acquiring a real-time surface image stream of the substrate by an upstream optical sensor array, including multispectral reflectance and microtopography data. And dynamically fitting a virtual reference plane based on the statistical median of the morphology data so as to adapt to material movement and surface fluctuation. And establishing a spraying control grid on the plane, and mapping reflection data to each grid point. Reversely solving a pigment theoretical saturation point according to the lattice point reflection characteristics, and calculating the initial spraying dosage of each point according to the pigment theoretical saturation point. And a multi-nozzle cooperative spraying instruction is generated in combination with the conveying speed. The method can adapt to the state change of the base material in real time, and accurate pattern positioning and dose on-demand supply on a high-speed production line are achieved, so that the uniformity and definition of a decorative layer are improved, and raw materials are saved.

The present disclosure relates to a display apparatus, and the display apparatus includes a display panel on which a plurality of sub-pixels are disposed, the plurality of sub-pixels each including an organic light-emitting diode, a base voltage node connected to a cathode electrode of the organic light-emitting diode, a plurality of driving voltage lines disposed on the display panel and configured to supply a driving voltage of the organic light-emitting diode to the plurality of sub-pixels, a controller configured to control a gate driving circuit and a data driving circuit, and a defect detection circuit configured to determine whether a defect occurs in the driving voltage line based on a voltage sensed at the base voltage node, wherein, based on a defect signal output from the defect detection circuit, an output of at least one of the controller, the gate driving circuit, and the data driving circuit is controlled.

The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.

The invention provides a cooperative low-voltage ride-through control method and related device based on a network construction type and network following type three-terminal interconnection system, and the method comprises the steps: triggering a cooperative low-voltage ride-through control mechanism in response to a voltage drop fault generated at an AC side connected with a network construction type converter; performing cooperative control on each converter based on the mechanism; wherein the control network construction type converter only undertakes AC side voltage establishment and current safety survival functions, realizes current limiting control through adaptive virtual impedance, and does not participate in DC side energy adjustment of a common DC bus; the DC voltage control type grid-following converter is controlled to suppress DC voltage double-frequency fluctuation of the common DC bus, and actively absorb and compensate double-frequency power disturbance introduced by the grid-forming converter; and controlling the active power control type grid-following converter to avoid active power adjustment during the voltage drop fault period. A collaborative low-voltage ride through control mechanism is provided, the direct-current voltage fluctuation is reduced, and the overall low-voltage ride through capacity of the system is improved.

The application provides a split-gate flash memory and a manufacturing method thereof. The memory comprises a semiconductor substrate, has an active region and an isolation structure, and part of the surface of the isolation structure is lower than the surface of the active region to form a groove; a coupling medium layer covers the top and sidewall of the active region; a floating gate is located on the surface of the coupling medium layer and surrounds the top and sidewall of the active region and does not completely fill the groove; an inter-electrode medium layer is located on the surface of the floating gate; a control gate is located on the surface of the inter-electrode medium layer and fills the remaining part of the groove; a word line is located on the sidewall of the floating gate and the control gate; and a tunneling medium layer is located between the word line and the floating gate, the control gate and the substrate. The application enhances the control force by three-dimensionally surrounding the channel with the floating gate, reduces the risk of punch-through, increases the coupling rate by filling the groove with the control gate, reduces the operating voltage, and improves the reliability of the device.

A kind of anti-radiation reinforced SiC super-junction JFET structure and preparation method, from bottom to top are in order: drain metallization layer, N+ substrate layer, N buffer layer, P column region, N column region, P-base region, current expansion region, N+ source region, P+ gate region, isolation dielectric layer, gate metallization layer, source metallization layer.P column region and N column region are arranged alternately on the upper surface of N buffer layer, P column region is symmetrically arranged, and N column region is arranged between two P column regions.P column region and P-base region form a P-type doped region as a whole, and are connected with source metallization layer.Electrically conductive channel structure is formed between P+ gate region and P-base region, and the opening and closing of channel are realized by controlling the voltage on P+ gate region.The application effectively solves the problem of electric field concentration caused by high-energy charged particle bombardment in the device, reduces local high temperature, and greatly improves the anti-single-particle radiation capability of SiC JFET.

A memory cell structure and a method for forming the same, the method comprising: using a first sidewall and a second sidewall as masks, etching a transition floating gate layer until the substrate surface is exposed to form two mutually independent memory gate structures on the substrate and an opening between the two memory structures, each memory gate structure including a floating gate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer, the floating gate including a first region and a second region located on the first region, the first region including opposing first and second sidewalls, the first sidewalls facing adjacent memory gate structures, the second sidewalls protruding a first dimension relative to the control gate sidewalls, the first sidewalls protruding a second dimension relative to the control gate sidewalls, the second dimension being larger than the first dimension; forming an erase gate within the opening to improve the erase efficiency of the formed memory cell structure.

A display device may comprise a display panel including a first subpixel group and a second subpixel group having different structures on a silicon substrate, a gate driving circuit supplying a gate signal to the display panel, a data driving circuit supplying a data voltage to the display panel, and a timing controller controlling the gate driving circuit and the data driving circuit and sensing a characteristic value of a driving transistor included in the first subpixel group through a reference voltage line. In the first subpixel group, a first driving transistor included in each subpixel may be electrically connected to the reference voltage line through a sensing transistor, and in the second subpixel group, a second driving transistor included in each subpixel may not be electrically connected to the reference voltage line.

The application provides a method for increasing the process window of an ILD filling of a flash memory device, which comprises the following steps: providing a semiconductor structure, which comprises a semiconductor substrate, a gate dielectric layer, a word line polysilicon, a floating gate and a control gate; forming an oxide layer on the surface of the semiconductor structure, and forming a nitride layer on the surface of the oxide layer; etching the nitride layer and the oxide layer by an etching process to form a first side wall on the outside of the floating gate, the control gate, the intermediate dielectric layer and the word line side wall; cleaning the semiconductor structure with the first side wall by a first wet cleaning process; ion implanting the semiconductor substrate to form a source region and a drain region on both sides of the first side wall; and cleaning the semiconductor structure with the source region and the drain region by a second wet cleaning process. The application solves the problem of the existing flash memory device in the ILD filling process.

The application relates to a threshold voltage correction circuit and a correction method, device and display equipment thereof. The threshold voltage correction circuit comprises a contrast unit, an analog unit and a control unit. The contrast unit comprises a first transistor. The analog unit comprises a second transistor, which is used for simulating the running state of a pull-down transistor in a gate driving circuit. The control unit is used for determining the threshold voltage difference of the first transistor and the second transistor according to the current change between the source and the drain of the first transistor and the second transistor. If the threshold voltage difference is greater than a preset voltage, the control gate driving unit signal is inserted into a black picture frame in the display process, and a target voltage is applied to the second transistor and the pull-down transistor in the gate driving circuit until the threshold voltage difference is less than or equal to the preset voltage. The problem that horizontal lines appear on the picture due to the right shift of the I-V curve of the TFT is solved.

A display device includes a display panel, a gate driver, a data driver and a driving controller which controls the gate driver and the data driver. The gate driver include a plurality of gate signal generators. A gate signal generator of the gate signal generators includes a first flip-flop which receives a clock signal and outputs a logic signal by sampling a previous carry signal at a rising edge of the clock signal, a first invertor which receives the clock signal and outputs an inverted clock signal having inverted waveform of the clock signal, a second flip-flop which output a carry signal by sampling the logic signal at a rising edge of the inverted clock signal. The gate driver outputs the gate signal based on the logic signal.

An electronic device including: a semiconductor nanowire; at least two separate first control gates, arranged next to each other on the side of a first lateral surface of the nanowire, and configured to each control the electrostatic potential of a quantum dot intended to be formed in the nanowire; at least one second control gate arranged on the side of a second lateral surface, opposite to the first lateral surface, of the nanowire, and configured to control the electrostatic potential of a coupling region intended to be formed between two quantum dots; wherein all the first control gates are arranged on the side of the first lateral surface only, and the or all the second control gates are arranged on the side of the second lateral surface only.

The invention discloses a doubly-fed asynchronous motor propulsion system grid-side converter control method and system, and the method comprises the steps: collecting a DC bus voltage actual value, comparing the DC bus voltage actual value with a reference value to obtain a voltage error, constructing a discrete sliding mode surface based on the error and a change rate thereof, and generating an active power reference value matched with a voltage stability demand; establishing a discrete prediction model of active power and reactive power based on a mathematical model of the grid-side converter, constructing a cost function which aims at tracking a power reference value and realizing a unit power factor, and determining an optimal switching state of the grid-side converter through rolling optimization in each control period; and converting the optimal switching state into a driving signal to directly act on a converter power switching device. According to the method, traditional PI control and SPWM modulation are replaced, the dynamic response speed, the anti-interference capability and the parameter adaptability of the system are remarkably improved, and stable and efficient operation of the electric propulsion system under complex working conditions is effectively guaranteed.

The application discloses a double-gate reconfigurable field effect transistor process design kit construction method, and belongs to the field of integrated circuit process design kit expansion, reconfigurable device modeling and physical verification. In view of the fact that existing open source PDK mainly faces traditional CMOS devices and is difficult to support circuit design, layout drawing and post-layout verification of double-gate RFET, the application provides a process design kit construction method for double-gate RFET. The method comprises the following steps: constructing a four-terminal RFET compact model and packaging the four-terminal RFET compact model into a SPICE subcircuit; establishing a schematic symbol, a layout unit and parameter configuration; extending LVS device identification rules to identify four-port RFET devices containing a source, a drain, a control gate and a polarity gate; constructing a parasitic parameter extraction file and integrating the parasitic parameter extraction file into a layout verification process; and finally, performing post-layout simulation verification on an RFET inverter and reconfigurable NAND and NOR logic. The application realizes a complete design closed loop of double-gate RFET from a model, a schematic, a layout, DRC / LVS, PEX and reverse label simulation.

The application discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor, comprising: source region, pocket area, channel region, drain region, polar grid, control grid, source, drain, first dielectric layer, second dielectric layer and third dielectric layer;Source region is connected with source and pocket area, and adopts Gauss light doping InAs material;Pocket area is connected with channel region, and is InAs / GaAsSb heterojunction structure;Channel region is connected with drain region;Drain region is connected with drain;First dielectric layer is located on the two sides of source region;Polar grid is located on the first dielectric layer;Second dielectric layer is located on the two sides of a part of channel region;Third dielectric layer is located on the two sides of another part of channel region;Control grid, including tunneling gate and auxiliary gate.The application further discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor's single particle irradiation effect simulation optimization method, can provide more comprehensive simulation data, and device optimization effect is better.

The application discloses a super flash including: a first gate trench formed at the top of a source region, wherein a floating gate and a control gate are formed in the first gate trench. A second nitrogen oxide layer and a first oxide layer are formed between a first side surface of the floating gate and side and bottom surfaces of the first gate trench. A third nitrogen oxide layer and a fourth oxide layer are formed between a second side surface of the floating gate and a side surface of the control gate. The floating gate is a TiN layer; and the top of the floating gate is higher than a top surface of the control gate. The second nitrogen oxide layer and the third nitrogen oxide layer prevent the diffusion of oxygen into the floating gate. The present application also discloses a method for manufacturing a super flash.

The invention relates to a transistor structure preparation method, apparatus and device, and a medium. The method comprises the steps of obtaining process node parameters of a transistor structure and a corresponding gate oxide layer thickness adjustment model; determining the target gate oxide layer thickness of the transistor structure according to the target beta value of the transistor structure and the incidence relation between the gate oxide layer thickness and the transistor current amplification factor beta value; according to the target gate oxide layer thickness and the incidence relation between the gate oxide layer thickness and the emitter width, determining a target emitter width value of the transistor structure; before a source region / drain region of the transistor structure is prepared, controlling a semiconductor machine to prepare a gate oxide layer of the transistor structure according to the thickness of a target gate oxide layer; and controlling the semiconductor machine to prepare an emitter region of the transistor structure according to the target emitter width value. The beta value of the prepared transistor can be precisely controlled by controlling the thickness of the gate oxide layer in a targeted manner at least according to process node parameters.

A circuit (400) includes a low voltage flash memory (200) integrated with a vertical field effect transistor and a non-volatile memory element (100). The low voltage flash memory is coupled with the non-volatile memory element through the vertical field effect transistor, one or more bit lines, and one or more word lines. The low voltage flash memory can provide a lower significant conductance and the non-volatile memory element can provide a higher significant conductance. The low voltage flash memory can include a source and a drain. The source can be separated from the drain by an epitaxial channel. The low voltage flash memory can include a floating gate. The floating gate can be separated from the epitaxial channel by a first dielectric layer. The low voltage flash memory can include a control gate. The control gate can be separated from the floating gate by a second dielectric layer.

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a substrate, forming a trench extending from a first surface of the substrate to an interior of the substrate, forming a shielding dielectric layer at a bottom and a part of a sidewall of the trench, and forming a shielding gate in the trench. The shielding gate fills a part of the trench, a top surface of the shielding gate is higher than a top surface of the shielding dielectric layer, and a distance from the top surface of the shielding dielectric layer to the first surface is a first depth. A part of the shielding gate is etched to make the top surface of the shielding gate flush with the top surface of the shielding dielectric layer, and a predetermined thickness of the substrate is etched from the first surface to make the distance from the top surface of the shielding dielectric layer to the first surface a second depth. The first depth is greater than the second depth. An inter-gate dielectric layer and a control gate structure are formed in the trench. The method of the application etches a predetermined thickness of the substrate while etching the shielding gate, thereby effectively reducing a high-density plasma filling aspect ratio, and further increasing a filling window and improving a filling effect.

The invention discloses a memory structure and a forming method thereof. The memory structure comprises a substrate; the channel structures are separately located on the substrate; the floating gate structure surrounds the channel structure; the control gate structure surrounds the floating gate structure; and the word line structure surrounds the channel structure, and the word line structure is positioned above the floating gate structure and the control gate structure. The word line structure, the floating gate structure and the control gate structure are arranged in the direction perpendicular to the surface of the substrate, the size of the memory structure in the direction parallel to the surface of the substrate is reduced, and the integration level of the device is improved; besides, the floating gate structure is surrounded by the control gate structure, so that the contact area between the control gate structure and the floating gate structure is increased, the coupling area between the control gate structure and the floating gate structure is further increased, the coupling rate of the device is improved, the power consumption of the memory structure is reduced, and the durability of the device is improved.

This invention discloses a method and system for controlling the voltage balance at the point of common coupling (PCC) of a grid-connected system, belonging to the field of electrical engineering. The grid-connected system includes one current-controlled grid-connected inverter and one voltage-controlled grid-connected inverter. The control method includes steps such as sampling, power calculation and PCC voltage estimation, power control, and negative-sequence adaptive voltage control. When a voltage imbalance occurs at the PCC of the grid-connected system, the voltage-controlled inverter is activated to output negative-sequence adaptive control. By adjusting the negative-sequence component of the output voltage, the voltage-controlled inverter compensates for the unbalanced voltage at the PCC. The final compensation effect is equivalent to a negative-sequence voltage source connected in series with the voltage-controlled inverter, which improves the voltage quality at the PCC and facilitates the stable grid connection of other inverters in the system.

The application discloses a high-reliability SONOS type pFLASH switch unit structure, and belongs to the microelectronic field. The structure comprises two 2T-FLASH tubes and one pMOS type signal transmission tube. The two 2T-FLASH tubes are in the same well. The two 2T-FLASH tubes are respectively 2T-FLASH tube T1 and 2T-FLASH tube T2, and the one pMOS type signal transmission tube is pMOS type signal transmission tube T3. T1 comprises pMOS type selection tube T12 and SONOS type pFLASH programming / erasing tube T11, the source end of T12 is connected with the drain end of T11, and a series connection relationship is formed. T2 comprises pMOS type selection tube T22 and SONOS type pFLASH programming / erasing tube T21, the source end of T22 is connected with the drain end of T21, and a series connection relationship is formed. T11 and T21 share a control gate.

A display device and an electronic device including the same are provided. The display device may include a display panel, a gate driving circuit, a data driving circuit, a driving voltage supply circuit, and a driving control circuit that controls the gate driving circuit, the data driving circuit, and the driving voltage supply circuit. The driving voltage supply circuit supplies a gate driving voltage, a data driving voltage, and a panel driving voltage including a first power supply voltage and a second power supply voltage lower than the first power supply voltage. The drive control circuit determines a scaling factor based on a load of input frame data, generates output frame data by applying the scaling factor to the input frame data, and determines a first power supply voltage and an input power supply voltage for generating the first power supply voltage based on a maximum gradation of the input frame data and a load of the output frame data.

This invention discloses a modulator and its manufacturing method, belonging to the field of silicon-based optoelectronics technology. The manufacturing method of the modulator includes the following steps: providing a substrate, forming an input waveguide, an output waveguide, a bulk, and a surrounding dielectric layer on the substrate; etching to thin the bulk and the surrounding dielectric layer in the area where the gate is located to form a groove; forming an insulating dielectric layer on top of the bulk; depositing a polysilicon layer, the thickness of which is not less than the depth of the groove; using a CMP process to thin the polysilicon layer at least to expose the top surface of the input waveguide, the output waveguide, and the surrounding dielectric layer, forming a polysilicon pattern in the groove; and continuing to etch to remove the polysilicon pattern outside the gate area to form the gate. By redesigning the interface structure of the input waveguide-SISCAP and SISCAP-output waveguide, the thickness of the gate is controlled by utilizing the thickness of the bulk and the thickness difference between the input and output waveguides, so that both the input and output waveguides are flush with the top of the gate, thereby making the device cross-section continuous and without abrupt changes in the vertical direction to limit interface reflection. Furthermore, the roughness of the gate top is reduced using the CMP process to reduce interface scattering.

The application discloses a kind of shielded gate trench MOSFET cell structure and its manufacturing method, shielded gate trench MOSFET cell structure includes substrate, drift region and interlayer dielectric layer, the drift region is provided with deep groove, the deep groove is provided with shielded gate, intermediate oxide layer and control gate;The upper portion of the drift region is formed with body region and source region by injection, the interlayer dielectric is provided with source contact hole that is through source region and extends into body region, the sidewall and bottom of the source contact hole are formed with high-doped contact region by injection;The lower of the source contact hole is formed with charge balance region by high-energy ion injection.In the application, by setting charge balance region, the lateral depletion of adjacent drift region by shielded gate can be enhanced when shielded gate trench MOSFET device is in reverse bias state, the specific on-resistance of the device is reduced, the epitaxial layer drift region is accelerated, and the reliability and radiation resistance of the device are improved.

This invention provides a method for obtaining breakdown voltage, a computer-readable storage medium, and a terminal. The method includes: providing a flash memory device, the flash memory device including word lines, control gates located on both sides of the word lines, and a dielectric layer between the two; applying a first voltage to the control gates, and applying a second voltage to the word lines within a preset voltage range with a preset step size; measuring and obtaining the word line current and control gate current under each of the second voltages, wherein the word line current is the current flowing into the word line, and the control gate current is the current flowing out of the control gate; and obtaining the breakdown voltage of the dielectric layer based on the word line current and the control gate current; wherein the first voltage is less than 0V, and the second voltage is greater than or equal to 0V. This invention solves the problem of inaccurate breakdown voltage of the dielectric layer between the word lines and the control gates obtained by existing methods.

The invention relates to a circuit arrangement (5) with a monitoring device (20) for monitoring a control device (1) for a half-bridge circuit (3), wherein the control device (1) is configured to generate control signals for high-side and low-side gate drivers (HSGD, LSGD) for controlling high-side and low-side FET switches (HST, LST) of the half-bridge circuit (3), and wherein the monitoring device (20) is configured to generate a turn-off / enable control signal (DISset) for controlling a turn-off / enable of the gate drivers (HSGD, LSGD). According to the invention, the integrated circuit (10) further comprises a signal processing device (30) configured to generate high-side and low-side turn-off / enable signals (HSdis) based on the turn-off / enable control signal (DISset).to generate LSdis) for the high-side and low-side gate drivers (HSGD, LSGD) such that when the turn-off / enable control signal (DISset) changes to turn off the gate drivers (HSGD, LSGD), the high-side turn-off / enable signal (HSdis) changes immediately and the low-side turn-off / enable signal (LSdis) changes after a delay (Δtdis), whereas when the turn-off / enable control signal (DISset) changes to enable the gate drivers (HSGD, LSGD), the low-side turn-off / enable signal (LSdis) changes immediately and the high-side turn-off / enable signal (HSdis) changes after a time delay (Δten).

The invention discloses an EEPROM (Electrically Erasable Programmable Read-Only Memory) unit and a using method thereof The unit comprises a first subunit and a second subunit which are complementary, each of the first subunit and the second subunit comprises a substrate, and a first drain electrode, a source electrode and a second drain electrode are spaced from each other and formed on the substrate; a first channel is arranged between the first drain electrode and the source electrode, a first floating gate and a first selection gate are arranged above the first channel, a first control gate is arranged above the first floating gate, a first matching part is arranged in the first floating gate, and the first selection gate is provided with a second matching part matched with the first matching part; an electron migration path is formed between the first floating gate and the first selection gate; when the erasing operation is carried out, the first subunit and the second subunit are set to be in a first state; and when the programming operation is carried out, the first subunit or the second subunit is set to be in the second state, so that the states of the first subunit and the second subunit are different. The EEPROM unit provided by the invention has relatively high reliability.

This invention belongs to the field of power semiconductor technology and relates to a parallel current sharing circuit for a variable conduction region MCT. This invention employs a gate layout partitioning and threshold hierarchical control method, dividing the MCT gate layout into multiple conduction regions. By combining a gate drive circuit, a pulse discharge circuit, a feedback circuit, and a gate control circuit, the MCT gate conduction regions are controlled in real time, achieving precise control of the current peak during pulse discharge. The gate drive circuit is powered by an external low-voltage power supply and provides the gate drive signal to the gate control circuit through a driver chip. The pulse discharge circuit is powered by an external high-voltage source, discharging a resistor to generate a high-frequency pulse current signal. The feedback circuit samples the current peak of the high-frequency pulse current signal and provides a feedback signal to the gate control circuit. The feedback signal from the feedback circuit is used to precisely control the MCT conduction regions. The parallel current sharing structure of the variable conduction region MCT has the advantages of high integration, small size, and high stability.