905 results about "Control grid" patented technology

The invention discloses a fault ride-through hierarchical control method for a network-constructed converter, and the method comprises the steps: introducing a virtual resistor formed by fault current negative feedback into the voltage and current inner loop control of the network-constructed converter based on VSG control through a current inner loop dynamic amplitude limiting control layer after the converter enters a fault ride-through state, the size of the virtual resistor is adjusted in real time along with the amplitude of the fault current so as to carry out dynamic current limiting control on the virtual resistor; and the power outer loop dynamic compensation control layer dynamically adjusts an active power instruction value and a reactive power instruction value of the network construction type converter based on VSG control during the fault ride-through period according to the voltage drop degree of the power grid after the converter enters the fault ride-through state. And respectively performing active-frequency control and reactive-voltage control based on the active power instruction value and the reactive power instruction value. In addition, the method also comprises a state coupling and parameter self-adaption module. According to the method, the GFM converter can have better dynamic performance in the fault recovery stage.

The invention relates to the technical field of hybrid inverters, and discloses a hybrid inverter supporting reactive compensation and a control method thereof, and the hybrid inverter comprises a DC input unit, a three-phase full-bridge inversion unit, a grid-connected switching unit, a signal acquisition unit and a digital control unit. The direct current input unit comprises a photovoltaic interface, a battery interface and a direct current bus and is used for converging photovoltaic and energy storage electric energy; the three-phase full-bridge inversion unit is composed of a power device and an LCL filter and converts direct current into alternating current. The grid-connected switching unit comprises a static switch and an isolation transformer and is used for controlling power grid connection; the signal acquisition unit detects voltage and current signals; and the digital control unit judges a grid-connected mode or an off-grid mode according to the signal, calculates a reactive current reference value and generates a PWM (Pulse Width Modulation) control signal so as to realize reactive compensation control in the grid-connected mode and the off-grid mode. According to the invention, reactive power compensation capability is provided in both grid-connected and off-grid operation modes, and stable operation of the inverter in various working conditions is ensured.

The invention relates to an impedance measurement method and system. The method comprises the following steps: acquiring grid-connected point voltage, measurement frequency, disturbance amplitude and nth inverter grid-connected current of the multi-inverter grid-connected system; inputting the grid-connected point voltage into an improved phase-locked loop in a fundamental wave and disturbance control unit to generate a power grid frequency and a power grid phase; inputting the power grid phase and the nth inverter grid-connected current into the current control loop to generate a fundamental current control instruction; inputting the measurement frequency, the disturbance amplitude and the power grid frequency into the disturbance control ring to generate a disturbance instruction; inputting the disturbance instruction and the fundamental current control instruction into the modulation ring, generating a control driving signal according to a modulation strategy of an inverter, and controlling each inverter switch; and obtaining the controlled grid-connected point voltage through an impedance calculation unit, and generating the impedance of the inverter to be tested and the impedance of the power grid. By adopting the method, disturbance can be injected efficiently at low cost so as to measure impedance.

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a substrate which comprises a base layer and a spacer layer located on the base layer, and is divided into a first region for forming a BCD device and a second region for forming an SGT device, a BCD structure is arranged in the substrate layer of the first area, and a first SGT structure and a second SGT structure which are spaced from each other are arranged in the substrate layer of the second area; forming a patterned photoresist layer on the first SGT structure in the second region and the spacer layer above the BCD structure in the first region, and etching the spacer layer to expose a part of the substrate layer and the second SGT structure; and forming a control gate on the spacer layer above a part of the BCD structure and extending to a part of the exposed substrate layer, wherein the control gate is also formed on the exposed second SGT structure. On the basis of not increasing a photomask and a process, the breakdown voltage can be increased, and the electrical performance of the device is improved.

A programmable driver circuit (54) and related method (600) for simultaneously controlling multiple tunable probabilistic bit generators are disclosed. The driver circuit comprises a plurality of programmable voltage generators (52; 30), a programming unit (35) and a non-volatile memory unit (34a-b). Input terminals of the plurality of programmable voltage generators are jointly connectible to a single voltage supply source. The programming unit is configured to generate a sequence of programming pulses for the different voltage generators. Each voltage generator comprises a single-stage or multi-stage voltage divider circuit (31) formed by a series of resistive elements (32-1; 32-2; 33). The non-volatile memory unit (34a-b) comprises at least the resistive element positioned first in the series of resistive elements as a programmable resistance and a program control transistor (34-1) connected in series between the programmable resistance and a fixed reference voltage. A control gate of the program control transistor is operatively coupled to the programming unit to receive the sequence of programming pulses for the programmable voltage generator when operated in a programming mode.

The invention relates to the technical field of MOS semiconductors, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method, the vertical D-MOSFET comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, the profile of the cross section of the grid electrode is triangular, and a polycrystalline silicon covering layer is deposited at the junction of the grid electrode and the gate oxide layer; the profile of the cross section of the gate oxide layer is in a semi-elliptical shape, and the profile of the cross section of the polycrystalline silicon covering layer is in a triangular shape. The section profile of the grid electrode is designed to be triangular, the grid oxide layer is controlled to be in a semi-oval shape, electric field distribution and a carrier migration path are optimized, the triangular grid electrode can reduce electric field concentration at the edge of the grid electrode, and the breakdown risk is reduced.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

The invention discloses a ferroelectric semiconductor junction field effect transistor, a preparation method and application. The transistor can simultaneously realize optical sensor, storage, synapse and logic in a single device by utilizing the physical characteristics of the transistor. The structure comprises a source electrode, a drain electrode, a control grid electrode, a channel layer, a ferroelectric grid layer, an oxide layer and a substrate from top to bottom. The channel layer is made of a two-dimensional transition metal sulfide semiconductor material, the ferroelectric gate layer is made of a two-dimensional ferroelectric semiconductor material, the source electrode and the drain electrode are located on two layers of the two-dimensional semiconductor channel respectively, and the control gate is located over the ferroelectric gate layer. According to the preparation method and application of the ferroelectric semiconductor junction field effect transistor, the logic functions of optical signal sensing, data storage, synaptic calculation and self-switching can be integrated in a single transistor, the function discrete limitation of a traditional device is broken through, a new path is provided for a high-density integrated reconfigurable electronic device, and the field effect transistor is suitable for large-scale popularization and application. And the structure complexity and the function density are effectively balanced.

The invention relates to the technical field of arc-shaped screens, and discloses a 3D game scene adaptation method and device based on an arc-shaped screen, and the method comprises the steps: carrying out the three-dimensional coordinate sampling of the surface of the arc-shaped screen, constructing an arc-shaped screen space model, and carrying out the dynamic tracking in a 3D game scene according to the arc-shaped screen space model, and obtaining scene mapping data; performing spatial distortion vector construction and compensation transformation analysis based on the scene mapping data to obtain target scene data; constructing a control grid node by using the curved surface feature tensor, applying a deformation constraint condition to the control grid node, and solving a deformation energy equation to obtain scene deformation control data; the rendering control instruction is created based on the scene deformation control data, and scene state acquisition and space adaptation calculation are executed according to the rendering control instruction to obtain the scene display data, so that accurate correction of scene display is realized, the image quality is remarkably improved, and the stability and continuity of scene display are ensured.

The present application discloses a cell structure of a super flash comprising: a word line gate, a floating gate, a control gate, and an erase gate. The floating gate comprises a first TiN layer located on a side face of the control gate and a second polysilicon layer formed at the top of the first TiN layer. The second polysilicon layer is in electric contact with the first TiN layer. The erase gate is located at the top of the second polysilicon layer, and the erase gate and the floating gate are spaced from each other by a second inter-gate dielectric layer therebetween. During erasing, the top angle of the second polysilicon layer generates point discharge, thereby reducing an erasing voltage. The present application also discloses a method for manufacturing a super flash.

The invention provides a manufacturing method of a semiconductor structure, which is applied to the technical field of semiconductors. According to the invention, before the second conductive layer is formed, the ion implantation process is carried out on the substrate, so that the first ion implantation region is formed in the substrate below the deep trench, and the second ion implantation region is synchronously formed in the substrate at two sides of the deep trench, thereby saving an ion implantation process. The conduction type of the first ion implantation region (located between the control gate and the drain electrode) is opposite to that of the substrate, so that carriers can be mutually depleted, and the purpose of increasing a depletion region and the breakdown voltage is achieved; and then a second conductive layer is formed and deposited in the deep trench, and a control gate in a special shape is formed by combining a first conductive layer on the side wall of the deep trench, so that the purposes of reducing the overlapping area between the control gate and a drain electrode, reducing the gate-drain capacitance of the power semiconductor device, reducing the switching loss and finally improving the switching speed are achieved.

The invention provides a memory structure and a preparation method thereof. The method comprises the following steps: providing a substrate; depositing a floating gate layer on one side of the substrate; etching the floating gate layer to form a plurality of floating gate structures; a plurality of separated floating gates are formed through photoetching, a gap is formed between every two adjacent floating gates, the section of each floating gate is of a trapezoidal structure, the upper bottom of each trapezoidal structure faces the corresponding gap, and the lower bottom of each trapezoidal structure faces the corresponding selection gate; performing ion implantation on the substrate in alignment with a gap position between the floating gates to form a source end; a control gate is formed on one side of the source end, the control gate is located between every two adjacent floating gates, and the two floating gates located on the two sides of the control gate are symmetrically arranged relative to the control gate. The data retention capability of the memory is improved by changing the shape of the floating gate, damage to the tunneling oxide layer during source end ion implantation is avoided, part of existing process steps are reduced, the quality of the memory is improved, and the preparation efficiency is improved.

The invention discloses a device for simulating influence of ditch cleaning ice cover evolution on hydrodynamic parameters and an application method thereof, and relates to the technical field of ice water dynamics and hydraulic engineering experiments. The device comprises a low-level water tank, a high-level water tank, a centrifugal pump, a flow valve, a water tank, a steady-flow perforated plate, a ditch cleaning ice cover simulation device, a first water level control grid plate, a second water level control grid plate and a flow field measurement system. According to the invention, three key parameters of ditch cleaning length, ice cover submerging water depth and roughness of the bottom of the ice cover are independently regulated and controlled, and non-contact high-precision measurement is carried out by means of a PIV technology, so that systematic and refined research on hydrodynamic parameters of an ice cover ditch cleaning area is realized. According to the method, researchers can safely and systematically research the influence of a single variable on the ice cover ditch cleaning water power at low cost, and the fundamental bottleneck of traditional field measurement in the research is solved.

The invention discloses a manufacturing method of a memory device and the memory device, and the manufacturing method comprises the steps: providing a semiconductor substrate which comprises a substrate and a hard mask layer on the substrate; a plurality of first grooves are formed in the active area of the substrate from the hard mask layer, one part of the first grooves are located in the storage area, the other part of the first grooves are located in the leading-out area, and the parts, in the substrate, of the first grooves are defined as base body grooves; forming a gate insulating layer and a semi-floating gate at the bottom of the groove of the substrate; one part of the semi-floating gate is in contact with the substrate, and the other part of the semi-floating gate is isolated from the substrate through a gate insulating layer; and forming an inter-gate dielectric layer and a first gate layer in the first groove, forming a control gate of the memory unit in the first groove of the memory region, and forming a lead-out wire of the memory unit in the first groove of the lead-out region, namely, enabling the lead-out region to be in contact with the outside, and solving the problem of voltage drop caused by large buried gate resistance.

The invention provides a numerical control delayer, a four-digit numerical control delayer and a manufacturing method of a chip of the four-digit numerical control delayer. The delayer comprises a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit, the first single-pole double-throw switch comprises two stages of triodes S1 and S2 which are connected in parallel; the second single-pole double-throw switch comprises a triode S3 and a triode S4 which are connected in parallel; one end of the delay unit is connected with the drain electrode of S1, and the other end is connected with the drain electrode of S3; one end of the reference unit is connected with the drain of S2, and the other end is connected with the drain of S4; drain electrodes of the S1 and the S2 are connected with a radio frequency signal input port; drain electrodes of the S3 and the S4 are connected with a radio frequency signal output port; source electrodes of the S1, the S2, the S3 and the S4 are all in direct current grounding, grid electrodes of the S1, the S2, the S3 and the S4 are all connected with a voltage control unit, and on and off of each triode are controlled by controlling grid electrode voltage, so that the delayer is switched between a reference state and a delay state. According to the invention, the insertion loss of the delayer in the millimeter wave frequency band can be reduced.

The invention provides a nonvolatile memory structure, a preparation method and a programming, erasing and reading method, and the nonvolatile memory structure comprises a substrate which is internally provided with a source region and a drain region; the floating gate structure comprises a first dielectric layer arranged between the source region and the drain region; the charge storage layer is arranged on the first dielectric layer, and the charge storage layer comprises a plurality of nano storage points which are electrically isolated from one another; the second dielectric layer is arranged on the charge storage layer; and the control grid electrode is arranged on the second dielectric layer. The charge storage layer comprises a plurality of nanometer storage points which are electrically isolated from one another, charges can be stored in the nanometer storage points which are electrically isolated from one another during programming, when any nanometer storage point is broken down, due to the fact that the nanometer storage points are electrically isolated from one another, the rest of undamaged nanometer storage points can still normally store the charges, and therefore the reliability of programming is improved. The charge storage layer can maintain a normal storage function, so that the overall stability of the memory is improved, and the service life of the memory is prolonged.

The invention discloses a split gate field effect transistor with an ESD discharge path and a low-cost preparation method thereof. The split gate field effect transistor comprises a low-resistance N + substrate, two ends of the low-resistance N + substrate are respectively provided with a drain metal and an epitaxial layer, the top of the epitaxial layer is provided with a plurality of grooves, the side walls of the grooves are covered with first dielectric layers, and split gates and control gates are arranged in the grooves; the control gate and the split gate are isolated through a second dielectric layer in the range of the active region, the control gate and the split gate are short-circuited in the range of the transition region, the short-circuited part of the control gate is provided with a plurality of P-type regions, and the plurality of P-type regions are connected through N-type regions. According to the split gate field effect transistor, a plurality of PN junctions are introduced between the control gate and the split gate of the transition region of the traditional split gate field effect transistor to form a back-to-back Zener diode, and when an ESD event occurs, electrostatic charges are discharged through the Zener diode, so that the voltage between the gate and the source is not higher than the rated gate-source voltage, and the gate and the source are prevented from breaking down and damaging the device.

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

The invention discloses a forming method of a flash memory unit. The forming method comprises the following steps: providing a semiconductor substrate; forming a tunneling oxide layer on the semiconductor substrate; forming nanocrystalline silicon particles on the tunneling oxide layer; forming an isolation insulating layer on the tunneling oxide layer and the nanocrystalline silicon particles; and forming a control grid on the isolation insulating layer, wherein the step of forming the nanocrystalline silicon particles on the tunneling oxide layer comprises: forming an amorphous silicon layer on the tunneling oxide layer; and performing repeated seed crystal particle forming processes on the amorphous silicon layer, wherein surface annealing treatment is performed between two adjacent seed crystal particle forming processes, and an annealing process is performed after the last seed crystal particle forming process. The flash memory unit can be used for storing a large quantity of electrons, and has high performance.

The present invention is entitled "Method for Fabricating Memory Cells, High Voltage Devices and Logic Devices on a Substrate by Silicide on a Conductive Block". The present invention discloses a method for forming a semiconductor device, the method comprising: recessing the upper surface of a first region and a second region of a semiconductor substrate relative to a third region of the substrate; forming a pair of stacked structures in the first region, each stacked structure having a control gate above a floating gate; forming a first source region in the substrate between the pair of stacked structures; forming an erase gate above the first source region; forming a dummy material block in the third region; forming a select gate adjacent to the stacked structure; forming a high voltage gate in the second region; forming a first barrier layer above at least a portion of one of the high voltage gates; forming a silicide on the top surface of the high voltage gate that is not below the first barrier layer; and replacing the dummy material block with a metal material block.

The invention relates to the technical field of inverters, in particular to an interface circuit of an inverter and the inverter. The interface circuit comprises a main control chip, a broken line detection unit, a voltage division unit and a signal amplification unit, the broken line detection unit is connected with the other end of a broken line switch unit, and the broken line detection unit is used for detecting the broken line state of the power grid dispatching equipment and pulling down the voltage of the input end of the signal amplification unit when the line is broken; the voltage division unit comprises a first voltage division module and a plurality of second voltage division modules with different resistance values, the plurality of second voltage division modules and the plurality of power regulation switch units are connected in series in a one-to-one correspondence manner and then are connected in parallel, a first parallel node is grounded, and a second parallel node is connected with one end of the first voltage division module and the input end of the signal amplification unit; the other end of the first voltage-dividing module is connected with an external power supply; and the main control chip is used for judging the voltage output by the signal amplification unit and controlling grid-connected power generation according to a judgment result. The system has the functions of power dispatching and disconnection detection of the power grid dispatching equipment at the same time.

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first region and a second region which are adjacent to each other; the floating gate structure is positioned on the substrate in the first region; the control gate structure is located on the floating gate structure, and the control gate structure and the floating gate structure are insulated from each other; the first dielectric layer is located on the surface of one side, facing the second region, of the floating gate structure and the control gate structure, and the width of the first dielectric layer located at the top of the floating gate structure is smaller than that of the first dielectric layer located at the bottom of the floating gate structure in the direction perpendicular to the side wall of the floating gate structure; and the erasing gate structure is positioned on the substrate in the second region. According to the embodiment of the invention, when voltage is applied to the erasure gate structure, leakage current is not easy to generate, and electrons in the floating gate structure can enter the erasure gate structure through the first dielectric layer close to the top position of the floating gate structure, so that the erasure efficiency of the semiconductor structure is improved.

The invention provides a preparation method of a shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and the shield gate MOSFET, and belongs to the technical field of semiconductor power devices. The method comprises the following steps: forming a groove in a substrate on which a mask grows; forming an ONO lamination layer on the substrate with the groove; wherein the ONO lamination layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer which are laminated in sequence; shield gate polycrystalline silicon is formed in the groove provided with the ONO lamination layer; forming an isolation layer on the shield gate polycrystalline silicon; wherein the isolation layer is coated above the silicon nitride layer; and forming control gate polycrystalline silicon on the isolation layer. According to the method, the control gate polycrystalline silicon and the silicon nitride are isolated through the isolation layer, so that the forward high-temperature gate bias reliability is improved under the condition that the threshold voltage and the on resistance of the shield gate MOSFET are not influenced, and the product performance is improved.

The invention discloses a shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof. The device comprises a substrate; a semiconductor body; the semiconductor body comprises a drift region, a body region and a first active region; first grooves are formed in the two sides of the semiconductor body in the thickness direction perpendicular to the substrate; a source structure; the source structure is in contact with the first active region; a barrier dielectric layer, a shield gate dielectric layer and a shield gate; the upper surface of the barrier dielectric layer is flush with the upper surface of the isolation dielectric layer in the thickness direction of the substrate; and a control gate structure and a drain. The shield gate MOSFET device can effectively prevent hot carriers from being injected into the shield gate dielectric layer under the action of an electric field between the shield gate and the drift region when the shield gate MOSFET device is reversely broken down.

The present application discloses a shift register, a display panel and a display device, where the shift register includes N cascaded shift register units, each of which includes an input module, a noise reduction module, a pull-down control module, a pull-down module and an output module; where in the same shift register unit, the input module is configured to receive an input signal and control a signal of a first node; the noise reduction module is configured to receive the input signal and a first level signal, and control a transmission path of the first level signal to a second node; the pull-down control module is configured to receive a first clock signal and control a signal of the second node; the output module is configured to receive a second clock signal and a signal of the first node and control a gate drive signal.

A memory device includes an array comprising a plurality of one-time-programmable (OTP) memory cells; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.

Systems, devices, and methods for controlling grid-tied inverters with instantaneous synchronization and low-voltage-ride-through (LVRT) capabilities under a wide range of grid cable impedance without using a phase-locked loop.

The invention relates to an inertia synchronization PMSG self-adaptive control method based on online impedance estimation, and belongs to the field of new energy grid connection. The method comprises the following steps: S1, constructing an RLS-GA hybrid strategy algorithm to quickly and accurately identify power grid impedance, and determining the strength type of a power grid; s2, establishing a direct-drive fan grid-connected system control strategy, and adopting a power control ring, a current control ring and an inertia transmission control ring at a machine side; the grid side adopts a direct-current voltage synchronous loop, a reactive voltage control loop and a stabilization control loop; s3, linearizing the control equation, and based on a linearized small signal equation, obtaining a state variable of the direct-current voltage synchronous control grid-connected system of the grid-forming type direct-driven wind turbine generator; s4, calculating control parameters of a reactive voltage control loop and a direct-current voltage synchronous loop; and S5, carrying out adaptive parameter setting on an existing permanent magnet fan inertia synchronization strategy so as to adapt to the change of strong and weak power grids and improve the stability performance of the PMSG under different power grid short circuit ratios.

The invention provides a wide SOA shield gate MOSFET device and a manufacturing method thereof. The wide SOA shield gate MOSFET device comprises a substrate, an epitaxial layer, a groove, a shield gate, a control gate, a first isolation dielectric layer, a P well region, an N + injection region, a contact hole and a hole bottom contact region, the P well region comprises a first P well region which is formed only in a general injection mode after the control gate is formed, the MOSFET device is characterized in that the P well region further comprises a second P well region which is formed by band plate injection after the general injection mode, and / or the distances between at least one contact hole and the boundary of the adjacent groove are different. And cellular-level uniform heat dissipation is provided, the thermal stability of a power device in thermal design is improved, and an MOSFET device with a wide SOA is provided.