539 results about "Control grid" patented technology

The invention discloses a fault ride-through hierarchical control method for a network-constructed converter, and the method comprises the steps: introducing a virtual resistor formed by fault current negative feedback into the voltage and current inner loop control of the network-constructed converter based on VSG control through a current inner loop dynamic amplitude limiting control layer after the converter enters a fault ride-through state, the size of the virtual resistor is adjusted in real time along with the amplitude of the fault current so as to carry out dynamic current limiting control on the virtual resistor; and the power outer loop dynamic compensation control layer dynamically adjusts an active power instruction value and a reactive power instruction value of the network construction type converter based on VSG control during the fault ride-through period according to the voltage drop degree of the power grid after the converter enters the fault ride-through state. And respectively performing active-frequency control and reactive-voltage control based on the active power instruction value and the reactive power instruction value. In addition, the method also comprises a state coupling and parameter self-adaption module. According to the method, the GFM converter can have better dynamic performance in the fault recovery stage.

The invention relates to the technical field of hybrid inverters, and discloses a hybrid inverter supporting reactive compensation and a control method thereof, and the hybrid inverter comprises a DC input unit, a three-phase full-bridge inversion unit, a grid-connected switching unit, a signal acquisition unit and a digital control unit. The direct current input unit comprises a photovoltaic interface, a battery interface and a direct current bus and is used for converging photovoltaic and energy storage electric energy; the three-phase full-bridge inversion unit is composed of a power device and an LCL filter and converts direct current into alternating current. The grid-connected switching unit comprises a static switch and an isolation transformer and is used for controlling power grid connection; the signal acquisition unit detects voltage and current signals; and the digital control unit judges a grid-connected mode or an off-grid mode according to the signal, calculates a reactive current reference value and generates a PWM (Pulse Width Modulation) control signal so as to realize reactive compensation control in the grid-connected mode and the off-grid mode. According to the invention, reactive power compensation capability is provided in both grid-connected and off-grid operation modes, and stable operation of the inverter in various working conditions is ensured.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

The invention discloses a ferroelectric semiconductor junction field effect transistor, a preparation method and application. The transistor can simultaneously realize optical sensor, storage, synapse and logic in a single device by utilizing the physical characteristics of the transistor. The structure comprises a source electrode, a drain electrode, a control grid electrode, a channel layer, a ferroelectric grid layer, an oxide layer and a substrate from top to bottom. The channel layer is made of a two-dimensional transition metal sulfide semiconductor material, the ferroelectric gate layer is made of a two-dimensional ferroelectric semiconductor material, the source electrode and the drain electrode are located on two layers of the two-dimensional semiconductor channel respectively, and the control gate is located over the ferroelectric gate layer. According to the preparation method and application of the ferroelectric semiconductor junction field effect transistor, the logic functions of optical signal sensing, data storage, synaptic calculation and self-switching can be integrated in a single transistor, the function discrete limitation of a traditional device is broken through, a new path is provided for a high-density integrated reconfigurable electronic device, and the field effect transistor is suitable for large-scale popularization and application. And the structure complexity and the function density are effectively balanced.

The invention discloses a device for simulating influence of ditch cleaning ice cover evolution on hydrodynamic parameters and an application method thereof, and relates to the technical field of ice water dynamics and hydraulic engineering experiments. The device comprises a low-level water tank, a high-level water tank, a centrifugal pump, a flow valve, a water tank, a steady-flow perforated plate, a ditch cleaning ice cover simulation device, a first water level control grid plate, a second water level control grid plate and a flow field measurement system. According to the invention, three key parameters of ditch cleaning length, ice cover submerging water depth and roughness of the bottom of the ice cover are independently regulated and controlled, and non-contact high-precision measurement is carried out by means of a PIV technology, so that systematic and refined research on hydrodynamic parameters of an ice cover ditch cleaning area is realized. According to the method, researchers can safely and systematically research the influence of a single variable on the ice cover ditch cleaning water power at low cost, and the fundamental bottleneck of traditional field measurement in the research is solved.

The invention discloses a split gate field effect transistor with an ESD discharge path and a low-cost preparation method thereof. The split gate field effect transistor comprises a low-resistance N + substrate, two ends of the low-resistance N + substrate are respectively provided with a drain metal and an epitaxial layer, the top of the epitaxial layer is provided with a plurality of grooves, the side walls of the grooves are covered with first dielectric layers, and split gates and control gates are arranged in the grooves; the control gate and the split gate are isolated through a second dielectric layer in the range of the active region, the control gate and the split gate are short-circuited in the range of the transition region, the short-circuited part of the control gate is provided with a plurality of P-type regions, and the plurality of P-type regions are connected through N-type regions. According to the split gate field effect transistor, a plurality of PN junctions are introduced between the control gate and the split gate of the transition region of the traditional split gate field effect transistor to form a back-to-back Zener diode, and when an ESD event occurs, electrostatic charges are discharged through the Zener diode, so that the voltage between the gate and the source is not higher than the rated gate-source voltage, and the gate and the source are prevented from breaking down and damaging the device.

The invention discloses a forming method of a flash memory unit. The forming method comprises the following steps: providing a semiconductor substrate; forming a tunneling oxide layer on the semiconductor substrate; forming nanocrystalline silicon particles on the tunneling oxide layer; forming an isolation insulating layer on the tunneling oxide layer and the nanocrystalline silicon particles; and forming a control grid on the isolation insulating layer, wherein the step of forming the nanocrystalline silicon particles on the tunneling oxide layer comprises: forming an amorphous silicon layer on the tunneling oxide layer; and performing repeated seed crystal particle forming processes on the amorphous silicon layer, wherein surface annealing treatment is performed between two adjacent seed crystal particle forming processes, and an annealing process is performed after the last seed crystal particle forming process. The flash memory unit can be used for storing a large quantity of electrons, and has high performance.

A memory device includes an array comprising a plurality of one-time-programmable (OTP) memory cells; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.

The invention relates to an inertia synchronization PMSG self-adaptive control method based on online impedance estimation, and belongs to the field of new energy grid connection. The method comprises the following steps: S1, constructing an RLS-GA hybrid strategy algorithm to quickly and accurately identify power grid impedance, and determining the strength type of a power grid; s2, establishing a direct-drive fan grid-connected system control strategy, and adopting a power control ring, a current control ring and an inertia transmission control ring at a machine side; the grid side adopts a direct-current voltage synchronous loop, a reactive voltage control loop and a stabilization control loop; s3, linearizing the control equation, and based on a linearized small signal equation, obtaining a state variable of the direct-current voltage synchronous control grid-connected system of the grid-forming type direct-driven wind turbine generator; s4, calculating control parameters of a reactive voltage control loop and a direct-current voltage synchronous loop; and S5, carrying out adaptive parameter setting on an existing permanent magnet fan inertia synchronization strategy so as to adapt to the change of strong and weak power grids and improve the stability performance of the PMSG under different power grid short circuit ratios.

The invention relates to the technical field of hygienic product production and manufacturing, and discloses an online high-speed sanitary towel spraying decoration system and method. The method includes acquiring a real-time surface image stream of the substrate by an upstream optical sensor array, including multispectral reflectance and microtopography data. And dynamically fitting a virtual reference plane based on the statistical median of the morphology data so as to adapt to material movement and surface fluctuation. And establishing a spraying control grid on the plane, and mapping reflection data to each grid point. Reversely solving a pigment theoretical saturation point according to the lattice point reflection characteristics, and calculating the initial spraying dosage of each point according to the pigment theoretical saturation point. And a multi-nozzle cooperative spraying instruction is generated in combination with the conveying speed. The method can adapt to the state change of the base material in real time, and accurate pattern positioning and dose on-demand supply on a high-speed production line are achieved, so that the uniformity and definition of a decorative layer are improved, and raw materials are saved.

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

The present disclosure relates to a display apparatus, and the display apparatus includes a display panel on which a plurality of sub-pixels are disposed, the plurality of sub-pixels each including an organic light-emitting diode, a base voltage node connected to a cathode electrode of the organic light-emitting diode, a plurality of driving voltage lines disposed on the display panel and configured to supply a driving voltage of the organic light-emitting diode to the plurality of sub-pixels, a controller configured to control a gate driving circuit and a data driving circuit, and a defect detection circuit configured to determine whether a defect occurs in the driving voltage line based on a voltage sensed at the base voltage node, wherein, based on a defect signal output from the defect detection circuit, an output of at least one of the controller, the gate driving circuit, and the data driving circuit is controlled.

The invention provides a NORD flash memory structure and a manufacturing method and a testing method thereof. The NORD flash memory structure comprises a memory cell array and a floating gate lead-out region. In the floating gate lead-out region, a floating gate contact plug is directly and electrically connected to a floating gate polycrystalline silicon layer, and no control gate polycrystalline silicon layer is arranged above the floating gate polycrystalline silicon layer. Through the structure, the floating gate which is electrically suspended previously can be led out. On one hand, a fixed potential can be directly applied to the floating gate, so that the influence of a'read 'process and a'write / erase' process is separated in a test, and the process improvement direction is defined; and on the other hand, electrical parameters between the floating gate and all parts around the floating gate can be directly measured, so that the quality of the key dielectric layer can be accurately monitored. The technical problem that electric monitoring and problem analysis are difficult to directly carry out due to electric suspension of the floating gate is solved.

The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.

The invention provides a cooperative low-voltage ride-through control method and related device based on a network construction type and network following type three-terminal interconnection system, and the method comprises the steps: triggering a cooperative low-voltage ride-through control mechanism in response to a voltage drop fault generated at an AC side connected with a network construction type converter; performing cooperative control on each converter based on the mechanism; wherein the control network construction type converter only undertakes AC side voltage establishment and current safety survival functions, realizes current limiting control through adaptive virtual impedance, and does not participate in DC side energy adjustment of a common DC bus; the DC voltage control type grid-following converter is controlled to suppress DC voltage double-frequency fluctuation of the common DC bus, and actively absorb and compensate double-frequency power disturbance introduced by the grid-forming converter; and controlling the active power control type grid-following converter to avoid active power adjustment during the voltage drop fault period. A collaborative low-voltage ride through control mechanism is provided, the direct-current voltage fluctuation is reduced, and the overall low-voltage ride through capacity of the system is improved.

The application provides a split-gate flash memory and a manufacturing method thereof. The memory comprises a semiconductor substrate, has an active region and an isolation structure, and part of the surface of the isolation structure is lower than the surface of the active region to form a groove; a coupling medium layer covers the top and sidewall of the active region; a floating gate is located on the surface of the coupling medium layer and surrounds the top and sidewall of the active region and does not completely fill the groove; an inter-electrode medium layer is located on the surface of the floating gate; a control gate is located on the surface of the inter-electrode medium layer and fills the remaining part of the groove; a word line is located on the sidewall of the floating gate and the control gate; and a tunneling medium layer is located between the word line and the floating gate, the control gate and the substrate. The application enhances the control force by three-dimensionally surrounding the channel with the floating gate, reduces the risk of punch-through, increases the coupling rate by filling the groove with the control gate, reduces the operating voltage, and improves the reliability of the device.

A fin-based tunneling filed field effect transistor (TFET) includes a control gate structure and an assisting gate structure adjacent to the control gate structure. The assisting gate structure is disposed between the control gate structure and a source / drain region of the fin-based TFET. When a voltage is applied to the assisting gate structure, the assisting gate structure causes the valence band of the fin-based TFET to be raised near the junction between the source / drain region and a channel region in a semiconductor layer under the assisting gate structure. This reduces the tunneling distance between the source / drain region and the channel region, which allows for a lesser threshold voltage to be used for the control gate structure than without the assisting gate structure.

A kind of anti-radiation reinforced SiC super-junction JFET structure and preparation method, from bottom to top are in order: drain metallization layer, N+ substrate layer, N buffer layer, P column region, N column region, P-base region, current expansion region, N+ source region, P+ gate region, isolation dielectric layer, gate metallization layer, source metallization layer.P column region and N column region are arranged alternately on the upper surface of N buffer layer, P column region is symmetrically arranged, and N column region is arranged between two P column regions.P column region and P-base region form a P-type doped region as a whole, and are connected with source metallization layer.Electrically conductive channel structure is formed between P+ gate region and P-base region, and the opening and closing of channel are realized by controlling the voltage on P+ gate region.The application effectively solves the problem of electric field concentration caused by high-energy charged particle bombardment in the device, reduces local high temperature, and greatly improves the anti-single-particle radiation capability of SiC JFET.

A memory cell structure and a method for forming the same, the method comprising: using a first sidewall and a second sidewall as masks, etching a transition floating gate layer until the substrate surface is exposed to form two mutually independent memory gate structures on the substrate and an opening between the two memory structures, each memory gate structure including a floating gate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer, the floating gate including a first region and a second region located on the first region, the first region including opposing first and second sidewalls, the first sidewalls facing adjacent memory gate structures, the second sidewalls protruding a first dimension relative to the control gate sidewalls, the first sidewalls protruding a second dimension relative to the control gate sidewalls, the second dimension being larger than the first dimension; forming an erase gate within the opening to improve the erase efficiency of the formed memory cell structure.

A display device may comprise a display panel including a first subpixel group and a second subpixel group having different structures on a silicon substrate, a gate driving circuit supplying a gate signal to the display panel, a data driving circuit supplying a data voltage to the display panel, and a timing controller controlling the gate driving circuit and the data driving circuit and sensing a characteristic value of a driving transistor included in the first subpixel group through a reference voltage line. In the first subpixel group, a first driving transistor included in each subpixel may be electrically connected to the reference voltage line through a sensing transistor, and in the second subpixel group, a second driving transistor included in each subpixel may not be electrically connected to the reference voltage line.

A method can include receiving a first power supply voltage at a first terminal substantially at a first side of an IC device; providing first and second rows of insulated gate field effect transistors (IGFETs) substantially at a second side of the IC device, each IGFET including first and second source / drains (S / Ds), channels, and a control gate that substantially surrounds the channels. A first power supply voltage can be coupled from the first terminal to an S / D of an IGFET in the first row via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side. IGFETs of the first row can have a first conductivity type. IGFETs of the second row can have a second conductivity type. Corresponding devices and systems are also disclosed.

The present invention provides a semiconductor device that can be driven at high speed. A memory string extends in a direction perpendicular to a substrate plane, and has a semiconductor layer containing indium oxide. The memory string includes MONOS memory cells, with a tunnel layer provided on the control-gate side and a block layer on the semiconductor-layer side. Holes are injected into a charge storage layer from the control-gate side during erase operations. The semiconductor layer has a region in contact with an oxide layer. The semiconductor layer and the oxide layer both contain crystal grains. A semiconductor layer with high crystallinity can be formed using the oxide layer as a crystal nucleus. Also, memory cells can be provided on the memory string. A transistor included in a memory cell can be a vertical transistor in which each of the semiconductor layer, a gate insulating layer, and a gate electrode are at least partially provided in a trench portion.

The invention provides a shield gate field effect transistor and a manufacturing method thereof, and relates to the technical field of semiconductors. The shield gate field effect transistor comprises a control gate and a shield gate, the control gate comprises a plurality of main gate electrodes and a plurality of interconnected gate electrodes, two adjacent main gate electrodes are arranged in a staggered manner, and the end parts of the two adjacent main gate electrodes are connected through the interconnected gate electrodes to form a square structure; the shield gate comprises a field plate structure and a contact structure, the contact structure is connected with the field plate structure, the field plate structure is located below the control gate, and the contact structure is located in the square structure; the projection of the shielding grid in the vertical direction is overlapped with the projection of the interconnection grid in the vertical direction, and the projection of the shielding grid and the projection of the main body grid in the vertical direction are spaced. The shield gate field effect transistor and the manufacturing method thereof have the advantage that the dynamic latch-up effect can be effectively inhibited.

The application provides a method for increasing the process window of an ILD filling of a flash memory device, which comprises the following steps: providing a semiconductor structure, which comprises a semiconductor substrate, a gate dielectric layer, a word line polysilicon, a floating gate and a control gate; forming an oxide layer on the surface of the semiconductor structure, and forming a nitride layer on the surface of the oxide layer; etching the nitride layer and the oxide layer by an etching process to form a first side wall on the outside of the floating gate, the control gate, the intermediate dielectric layer and the word line side wall; cleaning the semiconductor structure with the first side wall by a first wet cleaning process; ion implanting the semiconductor substrate to form a source region and a drain region on both sides of the first side wall; and cleaning the semiconductor structure with the source region and the drain region by a second wet cleaning process. The application solves the problem of the existing flash memory device in the ILD filling process.

The application relates to a threshold voltage correction circuit and a correction method, device and display equipment thereof. The threshold voltage correction circuit comprises a contrast unit, an analog unit and a control unit. The contrast unit comprises a first transistor. The analog unit comprises a second transistor, which is used for simulating the running state of a pull-down transistor in a gate driving circuit. The control unit is used for determining the threshold voltage difference of the first transistor and the second transistor according to the current change between the source and the drain of the first transistor and the second transistor. If the threshold voltage difference is greater than a preset voltage, the control gate driving unit signal is inserted into a black picture frame in the display process, and a target voltage is applied to the second transistor and the pull-down transistor in the gate driving circuit until the threshold voltage difference is less than or equal to the preset voltage. The problem that horizontal lines appear on the picture due to the right shift of the I-V curve of the TFT is solved.

The embodiment of the invention discloses a semiconductor device. Comprising a semiconductor body, and the semiconductor body comprises a first surface, a second surface, a well region, a first region and a first groove; the first groove comprises a first sub-groove and a second sub-groove which are communicated with each other; in the direction perpendicular to the first surface and pointing to the second surface, the size of the second sub-groove is larger than that of the first sub-groove; in the direction from the first surface to the second surface, the vertical distance between the first sub-groove and the second surface is smaller than the vertical distance between the well region and the second surface; a first insulating layer; a shield gate; a first strain insulating layer; a second insulating layer; a control gate; the first area is provided with a second groove, and the depth of the second groove is smaller than the thickness of the first area. A second strain insulating layer; the first strain insulating layer and the second strain insulating layer are used for applying stress to the two ends of the channel region; a source electrode; and a drain electrode. According to the technical scheme of the embodiment of the invention, the channel carrier mobility can be improved, and the channel resistance can be reduced.

A semiconductor device is provided. The semiconductor device includes a memory structure including a first transistor channel, a gate structure overlying the first transistor channel, and a second transistor channel overlying the gate structure. The gate structure includes a control gate.

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor body, wherein the semiconductor body comprises a first surface, a second surface, a well region, a first region, a first groove and a second groove; the first groove comprises a first sub-groove and a second sub-groove which are communicated with each other; the second groove is at least located between the well region and the first groove; a first insulating layer; a shield gate; the first isolation layer is located in the second sub-groove, and the vertical projection of the first isolation layer on the second surface covers the vertical projection of the shielding grid electrode on the second surface and the vertical projection of the first insulation layer on the second surface; the stress providing layer is located on the side wall of the second groove; the strain layer is positioned on one side, away from the well region, of the stress providing layer; the stress providing layer is used for providing stress for the strain layer and improving the carrier mobility in the strain layer; a second insulating layer; a control gate; a source electrode; and a drain electrode. According to the technical scheme of the embodiment of the invention, the channel carrier mobility can be improved, and the channel resistance can be reduced.

A display device includes a display panel, a gate driver, a data driver and a driving controller which controls the gate driver and the data driver. The gate driver include a plurality of gate signal generators. A gate signal generator of the gate signal generators includes a first flip-flop which receives a clock signal and outputs a logic signal by sampling a previous carry signal at a rising edge of the clock signal, a first invertor which receives the clock signal and outputs an inverted clock signal having inverted waveform of the clock signal, a second flip-flop which output a carry signal by sampling the logic signal at a rising edge of the inverted clock signal. The gate driver outputs the gate signal based on the logic signal.

A display device is provided, the display device including: a display panel including one or more sub-pixels; and a gate drive circuit to provide gate signals to the sub-pixels through gate lines, the gate drive circuit including: a gate output buffer circuit including a pull-up transistor to control a connection between a control clock input node and a gate output node and a pull-down transistor to control a connection between a low level voltage node and the gate output node; a control circuit able to control the gate output buffer circuit; and a dummy pull-down transistor, a gate node of the dummy pull-down transistor being shared with a gate node of the pull-down transistor.