75 results about "Control grid" patented technology

The invention discloses a forming method of a flash memory unit. The forming method comprises the following steps: providing a semiconductor substrate; forming a tunneling oxide layer on the semiconductor substrate; forming nanocrystalline silicon particles on the tunneling oxide layer; forming an isolation insulating layer on the tunneling oxide layer and the nanocrystalline silicon particles; and forming a control grid on the isolation insulating layer, wherein the step of forming the nanocrystalline silicon particles on the tunneling oxide layer comprises: forming an amorphous silicon layer on the tunneling oxide layer; and performing repeated seed crystal particle forming processes on the amorphous silicon layer, wherein surface annealing treatment is performed between two adjacent seed crystal particle forming processes, and an annealing process is performed after the last seed crystal particle forming process. The flash memory unit can be used for storing a large quantity of electrons, and has high performance.

The application provides a split-gate flash memory and a manufacturing method thereof. The memory comprises a semiconductor substrate, has an active region and an isolation structure, and part of the surface of the isolation structure is lower than the surface of the active region to form a groove; a coupling medium layer covers the top and sidewall of the active region; a floating gate is located on the surface of the coupling medium layer and surrounds the top and sidewall of the active region and does not completely fill the groove; an inter-electrode medium layer is located on the surface of the floating gate; a control gate is located on the surface of the inter-electrode medium layer and fills the remaining part of the groove; a word line is located on the sidewall of the floating gate and the control gate; and a tunneling medium layer is located between the word line and the floating gate, the control gate and the substrate. The application enhances the control force by three-dimensionally surrounding the channel with the floating gate, reduces the risk of punch-through, increases the coupling rate by filling the groove with the control gate, reduces the operating voltage, and improves the reliability of the device.

A kind of anti-radiation reinforced SiC super-junction JFET structure and preparation method, from bottom to top are in order: drain metallization layer, N+ substrate layer, N buffer layer, P column region, N column region, P-base region, current expansion region, N+ source region, P+ gate region, isolation dielectric layer, gate metallization layer, source metallization layer.P column region and N column region are arranged alternately on the upper surface of N buffer layer, P column region is symmetrically arranged, and N column region is arranged between two P column regions.P column region and P-base region form a P-type doped region as a whole, and are connected with source metallization layer.Electrically conductive channel structure is formed between P+ gate region and P-base region, and the opening and closing of channel are realized by controlling the voltage on P+ gate region.The application effectively solves the problem of electric field concentration caused by high-energy charged particle bombardment in the device, reduces local high temperature, and greatly improves the anti-single-particle radiation capability of SiC JFET.

A display device may comprise a display panel including a first subpixel group and a second subpixel group having different structures on a silicon substrate, a gate driving circuit supplying a gate signal to the display panel, a data driving circuit supplying a data voltage to the display panel, and a timing controller controlling the gate driving circuit and the data driving circuit and sensing a characteristic value of a driving transistor included in the first subpixel group through a reference voltage line. In the first subpixel group, a first driving transistor included in each subpixel may be electrically connected to the reference voltage line through a sensing transistor, and in the second subpixel group, a second driving transistor included in each subpixel may not be electrically connected to the reference voltage line.

The application provides a method for increasing the process window of an ILD filling of a flash memory device, which comprises the following steps: providing a semiconductor structure, which comprises a semiconductor substrate, a gate dielectric layer, a word line polysilicon, a floating gate and a control gate; forming an oxide layer on the surface of the semiconductor structure, and forming a nitride layer on the surface of the oxide layer; etching the nitride layer and the oxide layer by an etching process to form a first side wall on the outside of the floating gate, the control gate, the intermediate dielectric layer and the word line side wall; cleaning the semiconductor structure with the first side wall by a first wet cleaning process; ion implanting the semiconductor substrate to form a source region and a drain region on both sides of the first side wall; and cleaning the semiconductor structure with the source region and the drain region by a second wet cleaning process. The application solves the problem of the existing flash memory device in the ILD filling process.

A display device includes a display panel, a gate driver, a data driver and a driving controller which controls the gate driver and the data driver. The gate driver include a plurality of gate signal generators. A gate signal generator of the gate signal generators includes a first flip-flop which receives a clock signal and outputs a logic signal by sampling a previous carry signal at a rising edge of the clock signal, a first invertor which receives the clock signal and outputs an inverted clock signal having inverted waveform of the clock signal, a second flip-flop which output a carry signal by sampling the logic signal at a rising edge of the inverted clock signal. The gate driver outputs the gate signal based on the logic signal.

The application discloses a double-gate reconfigurable field effect transistor process design kit construction method, and belongs to the field of integrated circuit process design kit expansion, reconfigurable device modeling and physical verification. In view of the fact that existing open source PDK mainly faces traditional CMOS devices and is difficult to support circuit design, layout drawing and post-layout verification of double-gate RFET, the application provides a process design kit construction method for double-gate RFET. The method comprises the following steps: constructing a four-terminal RFET compact model and packaging the four-terminal RFET compact model into a SPICE subcircuit; establishing a schematic symbol, a layout unit and parameter configuration; extending LVS device identification rules to identify four-port RFET devices containing a source, a drain, a control gate and a polarity gate; constructing a parasitic parameter extraction file and integrating the parasitic parameter extraction file into a layout verification process; and finally, performing post-layout simulation verification on an RFET inverter and reconfigurable NAND and NOR logic. The application realizes a complete design closed loop of double-gate RFET from a model, a schematic, a layout, DRC / LVS, PEX and reverse label simulation.

The application discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor, comprising: source region, pocket area, channel region, drain region, polar grid, control grid, source, drain, first dielectric layer, second dielectric layer and third dielectric layer;Source region is connected with source and pocket area, and adopts Gauss light doping InAs material;Pocket area is connected with channel region, and is InAs / GaAsSb heterojunction structure;Channel region is connected with drain region;Drain region is connected with drain;First dielectric layer is located on the two sides of source region;Polar grid is located on the first dielectric layer;Second dielectric layer is located on the two sides of a part of channel region;Third dielectric layer is located on the two sides of another part of channel region;Control grid, including tunneling gate and auxiliary gate.The application further discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor's single particle irradiation effect simulation optimization method, can provide more comprehensive simulation data, and device optimization effect is better.

The application discloses a super flash including: a first gate trench formed at the top of a source region, wherein a floating gate and a control gate are formed in the first gate trench. A second nitrogen oxide layer and a first oxide layer are formed between a first side surface of the floating gate and side and bottom surfaces of the first gate trench. A third nitrogen oxide layer and a fourth oxide layer are formed between a second side surface of the floating gate and a side surface of the control gate. The floating gate is a TiN layer; and the top of the floating gate is higher than a top surface of the control gate. The second nitrogen oxide layer and the third nitrogen oxide layer prevent the diffusion of oxygen into the floating gate. The present application also discloses a method for manufacturing a super flash.

This invention discloses a method and system for controlling the voltage balance at the point of common coupling (PCC) of a grid-connected system, belonging to the field of electrical engineering. The grid-connected system includes one current-controlled grid-connected inverter and one voltage-controlled grid-connected inverter. The control method includes steps such as sampling, power calculation and PCC voltage estimation, power control, and negative-sequence adaptive voltage control. When a voltage imbalance occurs at the PCC of the grid-connected system, the voltage-controlled inverter is activated to output negative-sequence adaptive control. By adjusting the negative-sequence component of the output voltage, the voltage-controlled inverter compensates for the unbalanced voltage at the PCC. The final compensation effect is equivalent to a negative-sequence voltage source connected in series with the voltage-controlled inverter, which improves the voltage quality at the PCC and facilitates the stable grid connection of other inverters in the system.

The application discloses a high-reliability SONOS type pFLASH switch unit structure, and belongs to the microelectronic field. The structure comprises two 2T-FLASH tubes and one pMOS type signal transmission tube. The two 2T-FLASH tubes are in the same well. The two 2T-FLASH tubes are respectively 2T-FLASH tube T1 and 2T-FLASH tube T2, and the one pMOS type signal transmission tube is pMOS type signal transmission tube T3. T1 comprises pMOS type selection tube T12 and SONOS type pFLASH programming / erasing tube T11, the source end of T12 is connected with the drain end of T11, and a series connection relationship is formed. T2 comprises pMOS type selection tube T22 and SONOS type pFLASH programming / erasing tube T21, the source end of T22 is connected with the drain end of T21, and a series connection relationship is formed. T11 and T21 share a control gate.

This invention discloses a modulator and its manufacturing method, belonging to the field of silicon-based optoelectronics technology. The manufacturing method of the modulator includes the following steps: providing a substrate, forming an input waveguide, an output waveguide, a bulk, and a surrounding dielectric layer on the substrate; etching to thin the bulk and the surrounding dielectric layer in the area where the gate is located to form a groove; forming an insulating dielectric layer on top of the bulk; depositing a polysilicon layer, the thickness of which is not less than the depth of the groove; using a CMP process to thin the polysilicon layer at least to expose the top surface of the input waveguide, the output waveguide, and the surrounding dielectric layer, forming a polysilicon pattern in the groove; and continuing to etch to remove the polysilicon pattern outside the gate area to form the gate. By redesigning the interface structure of the input waveguide-SISCAP and SISCAP-output waveguide, the thickness of the gate is controlled by utilizing the thickness of the bulk and the thickness difference between the input and output waveguides, so that both the input and output waveguides are flush with the top of the gate, thereby making the device cross-section continuous and without abrupt changes in the vertical direction to limit interface reflection. Furthermore, the roughness of the gate top is reduced using the CMP process to reduce interface scattering.

This invention belongs to the field of power semiconductor technology and relates to a parallel current sharing circuit for a variable conduction region MCT. This invention employs a gate layout partitioning and threshold hierarchical control method, dividing the MCT gate layout into multiple conduction regions. By combining a gate drive circuit, a pulse discharge circuit, a feedback circuit, and a gate control circuit, the MCT gate conduction regions are controlled in real time, achieving precise control of the current peak during pulse discharge. The gate drive circuit is powered by an external low-voltage power supply and provides the gate drive signal to the gate control circuit through a driver chip. The pulse discharge circuit is powered by an external high-voltage source, discharging a resistor to generate a high-frequency pulse current signal. The feedback circuit samples the current peak of the high-frequency pulse current signal and provides a feedback signal to the gate control circuit. The feedback signal from the feedback circuit is used to precisely control the MCT conduction regions. The parallel current sharing structure of the variable conduction region MCT has the advantages of high integration, small size, and high stability.

This invention discloses a manufacturing process for a floating-gate flash memory with a P-type doped control gate. The process steps are as follows: S1: Define the active regions of the floating-gate flash memory and the peripheral logic region; S2: Implant a P-type implantation layer to form a punch-through barrier and threshold voltage for the floating-gate storage transistor; S3: Perform the first etching of CG-Poly and implant ions to form an implantation layer for adjusting the threshold voltage of the selector device; S4: Form a self-aligned selector gate using CMP; S5: Perform low-energy, high-dose, and large-tilt-angle P-type impurity implantation to dope CG-Poly; S6: Perform LDD implantation, third sidewall deposition and etching, and source / drain implantation sequentially. This invention employs low-energy, high-dose, and large-tilt-angle P-type impurity implantation to dope CG-Poly before or after the second CG-Poly etching. By placing the doping implantation of CG-Poly after the second CG-Poly etching, the implanted P-type impurity ions undergo less thermal propagation, reducing the diffusion of P-type impurity ions from CG-Poly to other materials and improving process compatibility.

The present disclosure discloses a method for manufacturing a semi-floating gate transistor. Self-aligned etching is performed by using an SIN protection layer of a control gate structure to form a vertical contact window, instead of the photolithography and etching of conventional lateral contact window, thus omitting one contact window photolithography process, avoiding the formation of an asymmetric semi-floating gate device due to the deterioration of the photolithography pattern overlay of the lateral contact window, and greatly improving the uniformity and the process window of the semi-floating gate transistor. In addition, since the physical distance between the vertical contact window and the gate of the tunnel field-effect transistor of the semi-floating gate transistor is significantly shortened, the tunneling efficiency is high, thus improving the charging speed of the semi-floating gate polysilicon.

The application provides a one-time programmable device forming method, which comprises the following steps: providing a semiconductor device, which comprises a floating gate and a control gate located on an epitaxial layer and arranged at intervals, and a source end and a drain end located in the epitaxial layer and on both sides of the floating gate and the control gate, and an interlayer dielectric layer is further formed on the floating gate and the control gate; forming a via in the interlayer dielectric layer, and filling the via with tungsten by introducing WF6 gas and hydrogen, so as to form a via structure connected with the source end and / or the drain end, wherein, during the tungsten filling process, when the filling operation is interrupted and / or the hydrogen flow is insufficient, the following operations are performed: the temperature of the via filling process condition is set to 300-500 DEG C, the hydrogen flow is set to 500-700 sccm, and the hydrogen introduction time is set to 30-50 s; and the one-time programmable device is filled with tungsten by using the via filling process condition. The application reduces the occurrence of test failure of data retention.

The application discloses a test structure for drain end interference reliability of a storage unit and a test method thereof. The test structure is arranged in a cutting path of a wafer on which a storage chip is arranged. The test structure comprises at least two back-to-back storage units, i.e., a cycle storage unit and an interference storage unit. The cycle storage unit and the interference storage unit are each provided with a control gate, a floating gate, a tunneling dielectric layer and a blocking dielectric layer. The blocking dielectric layer is arranged between the control gate and the floating gate, the floating gate is arranged between the tunneling dielectric layer and the blocking dielectric layer, and the tunneling dielectric layer is arranged on the surface of a wafer substrate. The two drain ends of the cycle storage unit and the interference storage unit share one drain lead-out end. The source end / gate of the cycle storage unit and the source end / gate of the interference storage unit are respectively led out. During the test, the source end of the cycle storage unit is grounded, and the source end of the interference storage unit is applied with a test voltage. The application realizes efficient and accurate evaluation of the drain end interference problem of the NorFlash.

A semiconductor device includes a first source region and a drain region disposed on a substrate; a first gate stack comprising a first floating gate and a first control gate, and disposed between the first source region and the drain region; a first select gate disposed on one sidewall of the first gate stack; a first spacer disposed on a lower sidewall of the first select gate, and disposed adjacent to the first source region; a second spacer disposed on an upper sidewall of the first select gate; a first control gate silicide layer disposed on the first control gate; and a first select gate silicide layer disposed on the first select gate, and disposed between the first spacer and the second spacer.

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes: a substrate; a semiconductor body located on one side of the substrate; the semiconductor body including a drift region, a body region, and a first region; the drift region located on the side of the semiconductor body closer to the substrate; the body region located on the side of the drift region away from the substrate; the first region located on the side of the body region away from the substrate; first trenches formed on both sides of the semiconductor body; a shielding gate structure located at the bottom of the first trenches; a control gate structure located on the side of the shielding gate structure away from the substrate and within the first trenches; a source interconnect layer located on the side of the control gate structure away from the substrate and within the first trenches; the source interconnect layer contacting the first region; a source located on the side of the semiconductor body and the source interconnect layer away from the substrate; the source contacting the source interconnect layer; and a drain located on the side of the substrate away from the semiconductor body. The cell size of the semiconductor device provided by this invention can be reduced to an extremely small size.

The application provides a voltage type global shutter photosensitive detector based on a composite dielectric gate capacitor and a method. In a unit of the detector, a global shutter structure is arranged between a composite dielectric gate MOS capacitor and a reading transistor, and specifically includes a switch transistor and a switch capacitor. The structure of the switch transistor includes a bottom insulating dielectric layer, a control gate and a source-drain electrode. The source of the switch transistor is connected with the composite dielectric gate MOS capacitor. The drain of the switch transistor is connected with the switch capacitor in series. Charge signals are coupled from the composite dielectric gate MOS capacitor to the switch capacitor, so that the charge signals are converted into voltage signals. The control gate of the reading transistor is connected with the source of the switch transistor. Voltage signals are input from the control gate end of the reading transistor, and are read out by the drain of the reading transistor. The application can realize a global exposure function on the basis of a traditional photosensitive detector, and can effectively solve the analog domain noise caused by dark current at a photosensitive interface.

A circuit includes a digital circuit, a pullup circuit, a first / second pulldown circuits, and a ground loss detection unit (GLDA). The digital circuit generates a control signal for enabling / disabling an output channel based on an input signal. The pullup circuit enables the output channel if the control signal has a first value, by controlling a gate of a switch that couples a power source to the load. The first pulldown circuit disables the output channel if the control signal has a second value, by controlling the gate. The GLDA generates a ground loss triggering signal by comparing a voltage associated with the ground to an auxiliary voltage. A first value indicates loss of ground connection. The second pulldown circuit pulls a gate of the switch to the source of the switch when the ground loss triggering signal has the first value.

A method for manufacturing a semiconductor device, a semiconductor device, and a memory device are provided. The method includes forming shallow trench isolation structures in a substrate, where each shallow trench isolation structure has a protruding portion protruding from the surface of the substrate and first trenches are defined between the adjacent protruding portions of the shallow trench isolation structures; forming floating gates in first trenches and performing a first etching on a part of the protruding portions of the shallow trench isolation structures, where second trenches are formed between adjacent floating gates; performing a narrowing process on the floating gates; performing a second etching on a remaining part of the protruding portions of the shallow trench isolation structures to widen the second trenches; and forming a control gate, where the control gate is partially filled in the second trenches.

A light-emitting display device according to one or more embodiments of the present disclosure can comprise a display panel with multiple subpixels connected by data lines, gate lines, and gate drive voltage lines, a data drive circuit designed to supply data signals to the data lines, and a gate drive circuit designed to supply sampling signals to the gate lines, wherein each of the multiple subpixels comprises a light-emitting device, a drive transistor designed to connect between the gate drive voltage line and the light-emitting device and to control a current flowing through the light-emitting device, a first switching transistor designed to connect between a first node of the drive transistor and the data line, and a second switching transistor designed tobetween a second node of the drive transistor, which is connected to the light-emitting device, and the data line, may include a first capacitor connected between the first node and the second node, and a second capacitor connected between a third node of the drive transistor, which is connected to the drive voltage line, and the second node.

This invention relates to an enhanced denitrification device, specifically an enhanced denitrification device using a combined electrolysis-microelectrolysis-anaerobic process, comprising a denitrification container and an external power supply. The inner cavity of the denitrification container is divided into a wastewater treatment zone and an anaerobic water collection zone by a water collection control grid. The wastewater treatment zone has an inlet at the top, and the water collection control grid has a water collection outlet connecting the wastewater treatment zone and the anaerobic water collection zone. The anaerobic water collection zone has a sludge discharge outlet and a water outlet on its side. The wastewater treatment zone is filled with iron-carbon microelectrolysis packing material. Several electrode plates are also spaced apart within the wastewater treatment zone, with anode and cathode plates alternating. The anode plates are connected to the positive terminal of the external power supply, and the cathode plates are connected to the negative terminal of the external power supply. Compared with existing technologies, this invention solves the problems of high energy consumption in external power supply-driven electrolysis and limitations of iron-carbon microelectrolysis in existing technologies, achieving a combined use of external power supply electrolysis and iron-carbon microelectrolysis, providing enhanced denitrification capability for wastewater with a low carbon-to-nitrogen ratio and lower energy consumption.

A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

A method includes forming a structure in which a first conductive film, a dielectric film, a second conductive film, and a capping layer are sequentially stacked on a substrate; forming a mask pattern on the capping layer; etching the capping layer by using the mask pattern; forming a control gate line by etching the second conductive film by using the mask pattern as an etch mask, the control gate line comprising an inclined surface; etching a portion of the dielectric film and the first conductive film using the mask pattern as an etch mask to form a floating gate line from the first conductive film, and a remaining dielectric film from the dielectric film; forming an insulating spacer covering a sidewall of the floating gate line and the inclined surface of the control gate line; and forming a selection gate structure covering the insulating spacer and the capping layer.

本申请提供了一种闪存器件及其制备方法，所述闪存器件包括：半导体衬底，堆叠形成于半导体衬底上的浮栅层、栅介质层和控制栅层，其中，浮栅层与栅介质层的接触面以及控制栅层与栅介质层的接触面均为倾斜面。可以在保证闪存器件存储单元器件性能的同时，利用增大控制栅层和浮栅层的耦合面积，提高控制栅对浮栅的耦合比（coupling ratio），从而提升控制栅层与浮栅层的耦合效率，提升器件性能。

The application provides a trench gate MOSFET and a forming method, which comprises the following steps: forming a first trench in an epitaxial layer of a cell region and forming a second trench in an epitaxial layer of a gate lead-out region; forming a first gate dielectric layer and a first control gate in the first trench and the second trench; forming a third trench on both sides of the first control gate in the cell region and forming a fourth trench on both sides of the first control gate in the gate lead-out region; forming a second gate dielectric layer and a second control gate in the third trench and the fourth trench, the second control gate is separated from the first control gate by the second gate dielectric layer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer; forming a well region in the epitaxial layer close to the surface of the epitaxial layer; forming a source-drain terminal in the well region close to the surface of the epitaxial layer in the cell region; forming an interlayer dielectric layer on the surface of the epitaxial layer; forming a first contact hole in the cell region and forming a second contact hole in the gate lead-out region, and the first control gate and the second control gate are communicated.

In one embodiment, a charged particle beam writing method calculates an irradiation amount of a charged particle beam for writing a pattern on a substrate with a target mesh size based on design data. The writing region is virtually divided into first mesh regions using a mesh size larger than the target size, and an area density of the pattern in each first mesh region is calculated. A first irradiation amount of individual beams, defined at grid intersections of a control grid in the writing region, is then calculated using the area density. A second irradiation amount for the individual beams, when the writing region is divided with the target mesh size, is obtained from the first irradiation amount using a conversion formula including a reduction ratio of the target mesh size with respect to the predetermined mesh size.