759 results about "Control grid" patented technology

The invention discloses a fault ride-through hierarchical control method for a network-constructed converter, and the method comprises the steps: introducing a virtual resistor formed by fault current negative feedback into the voltage and current inner loop control of the network-constructed converter based on VSG control through a current inner loop dynamic amplitude limiting control layer after the converter enters a fault ride-through state, the size of the virtual resistor is adjusted in real time along with the amplitude of the fault current so as to carry out dynamic current limiting control on the virtual resistor; and the power outer loop dynamic compensation control layer dynamically adjusts an active power instruction value and a reactive power instruction value of the network construction type converter based on VSG control during the fault ride-through period according to the voltage drop degree of the power grid after the converter enters the fault ride-through state. And respectively performing active-frequency control and reactive-voltage control based on the active power instruction value and the reactive power instruction value. In addition, the method also comprises a state coupling and parameter self-adaption module. According to the method, the GFM converter can have better dynamic performance in the fault recovery stage.

The invention relates to the technical field of hybrid inverters, and discloses a hybrid inverter supporting reactive compensation and a control method thereof, and the hybrid inverter comprises a DC input unit, a three-phase full-bridge inversion unit, a grid-connected switching unit, a signal acquisition unit and a digital control unit. The direct current input unit comprises a photovoltaic interface, a battery interface and a direct current bus and is used for converging photovoltaic and energy storage electric energy; the three-phase full-bridge inversion unit is composed of a power device and an LCL filter and converts direct current into alternating current. The grid-connected switching unit comprises a static switch and an isolation transformer and is used for controlling power grid connection; the signal acquisition unit detects voltage and current signals; and the digital control unit judges a grid-connected mode or an off-grid mode according to the signal, calculates a reactive current reference value and generates a PWM (Pulse Width Modulation) control signal so as to realize reactive compensation control in the grid-connected mode and the off-grid mode. According to the invention, reactive power compensation capability is provided in both grid-connected and off-grid operation modes, and stable operation of the inverter in various working conditions is ensured.

A programmable driver circuit (54) and related method (600) for simultaneously controlling multiple tunable probabilistic bit generators are disclosed. The driver circuit comprises a plurality of programmable voltage generators (52; 30), a programming unit (35) and a non-volatile memory unit (34a-b). Input terminals of the plurality of programmable voltage generators are jointly connectible to a single voltage supply source. The programming unit is configured to generate a sequence of programming pulses for the different voltage generators. Each voltage generator comprises a single-stage or multi-stage voltage divider circuit (31) formed by a series of resistive elements (32-1; 32-2; 33). The non-volatile memory unit (34a-b) comprises at least the resistive element positioned first in the series of resistive elements as a programmable resistance and a program control transistor (34-1) connected in series between the programmable resistance and a fixed reference voltage. A control gate of the program control transistor is operatively coupled to the programming unit to receive the sequence of programming pulses for the programmable voltage generator when operated in a programming mode.

The invention relates to the technical field of MOS semiconductors, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method, the vertical D-MOSFET comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, the profile of the cross section of the grid electrode is triangular, and a polycrystalline silicon covering layer is deposited at the junction of the grid electrode and the gate oxide layer; the profile of the cross section of the gate oxide layer is in a semi-elliptical shape, and the profile of the cross section of the polycrystalline silicon covering layer is in a triangular shape. The section profile of the grid electrode is designed to be triangular, the grid oxide layer is controlled to be in a semi-oval shape, electric field distribution and a carrier migration path are optimized, the triangular grid electrode can reduce electric field concentration at the edge of the grid electrode, and the breakdown risk is reduced.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

The invention discloses a ferroelectric semiconductor junction field effect transistor, a preparation method and application. The transistor can simultaneously realize optical sensor, storage, synapse and logic in a single device by utilizing the physical characteristics of the transistor. The structure comprises a source electrode, a drain electrode, a control grid electrode, a channel layer, a ferroelectric grid layer, an oxide layer and a substrate from top to bottom. The channel layer is made of a two-dimensional transition metal sulfide semiconductor material, the ferroelectric gate layer is made of a two-dimensional ferroelectric semiconductor material, the source electrode and the drain electrode are located on two layers of the two-dimensional semiconductor channel respectively, and the control gate is located over the ferroelectric gate layer. According to the preparation method and application of the ferroelectric semiconductor junction field effect transistor, the logic functions of optical signal sensing, data storage, synaptic calculation and self-switching can be integrated in a single transistor, the function discrete limitation of a traditional device is broken through, a new path is provided for a high-density integrated reconfigurable electronic device, and the field effect transistor is suitable for large-scale popularization and application. And the structure complexity and the function density are effectively balanced.

The present application discloses a cell structure of a super flash comprising: a word line gate, a floating gate, a control gate, and an erase gate. The floating gate comprises a first TiN layer located on a side face of the control gate and a second polysilicon layer formed at the top of the first TiN layer. The second polysilicon layer is in electric contact with the first TiN layer. The erase gate is located at the top of the second polysilicon layer, and the erase gate and the floating gate are spaced from each other by a second inter-gate dielectric layer therebetween. During erasing, the top angle of the second polysilicon layer generates point discharge, thereby reducing an erasing voltage. The present application also discloses a method for manufacturing a super flash.

The invention discloses a device for simulating influence of ditch cleaning ice cover evolution on hydrodynamic parameters and an application method thereof, and relates to the technical field of ice water dynamics and hydraulic engineering experiments. The device comprises a low-level water tank, a high-level water tank, a centrifugal pump, a flow valve, a water tank, a steady-flow perforated plate, a ditch cleaning ice cover simulation device, a first water level control grid plate, a second water level control grid plate and a flow field measurement system. According to the invention, three key parameters of ditch cleaning length, ice cover submerging water depth and roughness of the bottom of the ice cover are independently regulated and controlled, and non-contact high-precision measurement is carried out by means of a PIV technology, so that systematic and refined research on hydrodynamic parameters of an ice cover ditch cleaning area is realized. According to the method, researchers can safely and systematically research the influence of a single variable on the ice cover ditch cleaning water power at low cost, and the fundamental bottleneck of traditional field measurement in the research is solved.

The invention provides a numerical control delayer, a four-digit numerical control delayer and a manufacturing method of a chip of the four-digit numerical control delayer. The delayer comprises a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit, the first single-pole double-throw switch comprises two stages of triodes S1 and S2 which are connected in parallel; the second single-pole double-throw switch comprises a triode S3 and a triode S4 which are connected in parallel; one end of the delay unit is connected with the drain electrode of S1, and the other end is connected with the drain electrode of S3; one end of the reference unit is connected with the drain of S2, and the other end is connected with the drain of S4; drain electrodes of the S1 and the S2 are connected with a radio frequency signal input port; drain electrodes of the S3 and the S4 are connected with a radio frequency signal output port; source electrodes of the S1, the S2, the S3 and the S4 are all in direct current grounding, grid electrodes of the S1, the S2, the S3 and the S4 are all connected with a voltage control unit, and on and off of each triode are controlled by controlling grid electrode voltage, so that the delayer is switched between a reference state and a delay state. According to the invention, the insertion loss of the delayer in the millimeter wave frequency band can be reduced.

The invention provides a nonvolatile memory structure, a preparation method and a programming, erasing and reading method, and the nonvolatile memory structure comprises a substrate which is internally provided with a source region and a drain region; the floating gate structure comprises a first dielectric layer arranged between the source region and the drain region; the charge storage layer is arranged on the first dielectric layer, and the charge storage layer comprises a plurality of nano storage points which are electrically isolated from one another; the second dielectric layer is arranged on the charge storage layer; and the control grid electrode is arranged on the second dielectric layer. The charge storage layer comprises a plurality of nanometer storage points which are electrically isolated from one another, charges can be stored in the nanometer storage points which are electrically isolated from one another during programming, when any nanometer storage point is broken down, due to the fact that the nanometer storage points are electrically isolated from one another, the rest of undamaged nanometer storage points can still normally store the charges, and therefore the reliability of programming is improved. The charge storage layer can maintain a normal storage function, so that the overall stability of the memory is improved, and the service life of the memory is prolonged.

The invention discloses a split gate field effect transistor with an ESD discharge path and a low-cost preparation method thereof. The split gate field effect transistor comprises a low-resistance N + substrate, two ends of the low-resistance N + substrate are respectively provided with a drain metal and an epitaxial layer, the top of the epitaxial layer is provided with a plurality of grooves, the side walls of the grooves are covered with first dielectric layers, and split gates and control gates are arranged in the grooves; the control gate and the split gate are isolated through a second dielectric layer in the range of the active region, the control gate and the split gate are short-circuited in the range of the transition region, the short-circuited part of the control gate is provided with a plurality of P-type regions, and the plurality of P-type regions are connected through N-type regions. According to the split gate field effect transistor, a plurality of PN junctions are introduced between the control gate and the split gate of the transition region of the traditional split gate field effect transistor to form a back-to-back Zener diode, and when an ESD event occurs, electrostatic charges are discharged through the Zener diode, so that the voltage between the gate and the source is not higher than the rated gate-source voltage, and the gate and the source are prevented from breaking down and damaging the device.

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

The invention discloses a forming method of a flash memory unit. The forming method comprises the following steps: providing a semiconductor substrate; forming a tunneling oxide layer on the semiconductor substrate; forming nanocrystalline silicon particles on the tunneling oxide layer; forming an isolation insulating layer on the tunneling oxide layer and the nanocrystalline silicon particles; and forming a control grid on the isolation insulating layer, wherein the step of forming the nanocrystalline silicon particles on the tunneling oxide layer comprises: forming an amorphous silicon layer on the tunneling oxide layer; and performing repeated seed crystal particle forming processes on the amorphous silicon layer, wherein surface annealing treatment is performed between two adjacent seed crystal particle forming processes, and an annealing process is performed after the last seed crystal particle forming process. The flash memory unit can be used for storing a large quantity of electrons, and has high performance.

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first region and a second region which are adjacent to each other; the floating gate structure is positioned on the substrate in the first region; the control gate structure is located on the floating gate structure, and the control gate structure and the floating gate structure are insulated from each other; the first dielectric layer is located on the surface of one side, facing the second region, of the floating gate structure and the control gate structure, and the width of the first dielectric layer located at the top of the floating gate structure is smaller than that of the first dielectric layer located at the bottom of the floating gate structure in the direction perpendicular to the side wall of the floating gate structure; and the erasing gate structure is positioned on the substrate in the second region. According to the embodiment of the invention, when voltage is applied to the erasure gate structure, leakage current is not easy to generate, and electrons in the floating gate structure can enter the erasure gate structure through the first dielectric layer close to the top position of the floating gate structure, so that the erasure efficiency of the semiconductor structure is improved.

The present application discloses a shift register, a display panel and a display device, where the shift register includes N cascaded shift register units, each of which includes an input module, a noise reduction module, a pull-down control module, a pull-down module and an output module; where in the same shift register unit, the input module is configured to receive an input signal and control a signal of a first node; the noise reduction module is configured to receive the input signal and a first level signal, and control a transmission path of the first level signal to a second node; the pull-down control module is configured to receive a first clock signal and control a signal of the second node; the output module is configured to receive a second clock signal and a signal of the first node and control a gate drive signal.

A memory device includes an array comprising a plurality of one-time-programmable (OTP) memory cells; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.

Systems, devices, and methods for controlling grid-tied inverters with instantaneous synchronization and low-voltage-ride-through (LVRT) capabilities under a wide range of grid cable impedance without using a phase-locked loop.

The invention relates to an inertia synchronization PMSG self-adaptive control method based on online impedance estimation, and belongs to the field of new energy grid connection. The method comprises the following steps: S1, constructing an RLS-GA hybrid strategy algorithm to quickly and accurately identify power grid impedance, and determining the strength type of a power grid; s2, establishing a direct-drive fan grid-connected system control strategy, and adopting a power control ring, a current control ring and an inertia transmission control ring at a machine side; the grid side adopts a direct-current voltage synchronous loop, a reactive voltage control loop and a stabilization control loop; s3, linearizing the control equation, and based on a linearized small signal equation, obtaining a state variable of the direct-current voltage synchronous control grid-connected system of the grid-forming type direct-driven wind turbine generator; s4, calculating control parameters of a reactive voltage control loop and a direct-current voltage synchronous loop; and S5, carrying out adaptive parameter setting on an existing permanent magnet fan inertia synchronization strategy so as to adapt to the change of strong and weak power grids and improve the stability performance of the PMSG under different power grid short circuit ratios.

The invention relates to the technical field of hygienic product production and manufacturing, and discloses an online high-speed sanitary towel spraying decoration system and method. The method includes acquiring a real-time surface image stream of the substrate by an upstream optical sensor array, including multispectral reflectance and microtopography data. And dynamically fitting a virtual reference plane based on the statistical median of the morphology data so as to adapt to material movement and surface fluctuation. And establishing a spraying control grid on the plane, and mapping reflection data to each grid point. Reversely solving a pigment theoretical saturation point according to the lattice point reflection characteristics, and calculating the initial spraying dosage of each point according to the pigment theoretical saturation point. And a multi-nozzle cooperative spraying instruction is generated in combination with the conveying speed. The method can adapt to the state change of the base material in real time, and accurate pattern positioning and dose on-demand supply on a high-speed production line are achieved, so that the uniformity and definition of a decorative layer are improved, and raw materials are saved.

The invention relates to a threshold voltage correcting circuit, a threshold voltage correcting method, a threshold voltage correcting device and display equipment. The threshold voltage correcting circuit comprises a comparison unit, a simulation unit and a control unit. The contrast unit comprises a first transistor; the simulation unit comprises a second transistor, and the second transistor is used for simulating the running state of a pull-down transistor in the gate drive circuit; the control unit is used for determining the threshold voltage difference between the first transistor and the second transistor according to the current change between the source and drain electrodes of the first transistor and the second transistor; and if the threshold voltage difference is greater than the preset voltage, controlling a gate driving unit signal to insert a black picture frame in a display process, and applying a target voltage to a second transistor and a pull-down transistor in the gate driving circuit until the threshold voltage difference is detected to be less than or equal to the preset voltage. The problem that the I-V curve of the TFT moves rightwards to cause cross grains in a picture is solved.

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

This document describes systems and techniques for a current-limiting control strategy for single-loop droop-controlled grid-forming inverters. In aspects, a hysteresis module is configured to compare an output current detected across one or more transistors in an inverter controlled by the single-loop droop converter with a specified maximum current and to generate an overcurrent signal. The overcurrent signal presents a fault signal responsive to the output current exceeding the specified maximum current. A logic array is configured to logically combine gate control signals generated by the single-loop droop controller to selectively direct the one or more transistors to allow the output current to flow therethrough with the overcurrent signal to present modified gate control signals to the one or more transistors. The logic array is configured to replace one or more of the gate control signals in the modified gate control signals with a gate disable signal responsive to the overcurrent signal presenting the fault signal.

The present disclosure relates to a display apparatus, and the display apparatus includes a display panel on which a plurality of sub-pixels are disposed, the plurality of sub-pixels each including an organic light-emitting diode, a base voltage node connected to a cathode electrode of the organic light-emitting diode, a plurality of driving voltage lines disposed on the display panel and configured to supply a driving voltage of the organic light-emitting diode to the plurality of sub-pixels, a controller configured to control a gate driving circuit and a data driving circuit, and a defect detection circuit configured to determine whether a defect occurs in the driving voltage line based on a voltage sensed at the base voltage node, wherein, based on a defect signal output from the defect detection circuit, an output of at least one of the controller, the gate driving circuit, and the data driving circuit is controlled.

The invention provides a NORD flash memory structure and a manufacturing method and a testing method thereof. The NORD flash memory structure comprises a memory cell array and a floating gate lead-out region. In the floating gate lead-out region, a floating gate contact plug is directly and electrically connected to a floating gate polycrystalline silicon layer, and no control gate polycrystalline silicon layer is arranged above the floating gate polycrystalline silicon layer. Through the structure, the floating gate which is electrically suspended previously can be led out. On one hand, a fixed potential can be directly applied to the floating gate, so that the influence of a'read 'process and a'write / erase' process is separated in a test, and the process improvement direction is defined; and on the other hand, electrical parameters between the floating gate and all parts around the floating gate can be directly measured, so that the quality of the key dielectric layer can be accurately monitored. The technical problem that electric monitoring and problem analysis are difficult to directly carry out due to electric suspension of the floating gate is solved.

The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.

The invention provides a cooperative low-voltage ride-through control method and related device based on a network construction type and network following type three-terminal interconnection system, and the method comprises the steps: triggering a cooperative low-voltage ride-through control mechanism in response to a voltage drop fault generated at an AC side connected with a network construction type converter; performing cooperative control on each converter based on the mechanism; wherein the control network construction type converter only undertakes AC side voltage establishment and current safety survival functions, realizes current limiting control through adaptive virtual impedance, and does not participate in DC side energy adjustment of a common DC bus; the DC voltage control type grid-following converter is controlled to suppress DC voltage double-frequency fluctuation of the common DC bus, and actively absorb and compensate double-frequency power disturbance introduced by the grid-forming converter; and controlling the active power control type grid-following converter to avoid active power adjustment during the voltage drop fault period. A collaborative low-voltage ride through control mechanism is provided, the direct-current voltage fluctuation is reduced, and the overall low-voltage ride through capacity of the system is improved.

The invention provides a forming method of a Nord flash memory, which comprises the following steps: forming a second active region, a plurality of columns of first active regions extending along a first direction and a shallow trench isolation structure in a substrate, and enabling the second active region to pass through the shallow trench isolation structure to connect the two columns of first active regions; a plurality of gate structures are formed on the surface of each column of first active regions, each gate structure comprises a word line gate, a floating gate and a control gate, the floating gate and the control gate are stacked and located on the two sides of a word line, and each gate structure is provided with a second active region on each of the two sides in the second direction; the two second active regions are also located on the two sides of the gate structure in the first direction; respectively forming ion implantation regions in the second active regions on two sides of each gate structure; word line connecting holes are formed in the surfaces of the ion implantation regions; and respectively connecting the word line connecting holes on the two sides of each column of gate structures along the first direction, so as to form two bit lines on the two sides of each column of gate structures along the first direction.

The application provides a split-gate flash memory and a manufacturing method thereof. The memory comprises a semiconductor substrate, has an active region and an isolation structure, and part of the surface of the isolation structure is lower than the surface of the active region to form a groove; a coupling medium layer covers the top and sidewall of the active region; a floating gate is located on the surface of the coupling medium layer and surrounds the top and sidewall of the active region and does not completely fill the groove; an inter-electrode medium layer is located on the surface of the floating gate; a control gate is located on the surface of the inter-electrode medium layer and fills the remaining part of the groove; a word line is located on the sidewall of the floating gate and the control gate; and a tunneling medium layer is located between the word line and the floating gate, the control gate and the substrate. The application enhances the control force by three-dimensionally surrounding the channel with the floating gate, reduces the risk of punch-through, increases the coupling rate by filling the groove with the control gate, reduces the operating voltage, and improves the reliability of the device.

A fin-based tunneling filed field effect transistor (TFET) includes a control gate structure and an assisting gate structure adjacent to the control gate structure. The assisting gate structure is disposed between the control gate structure and a source / drain region of the fin-based TFET. When a voltage is applied to the assisting gate structure, the assisting gate structure causes the valence band of the fin-based TFET to be raised near the junction between the source / drain region and a channel region in a semiconductor layer under the assisting gate structure. This reduces the tunneling distance between the source / drain region and the channel region, which allows for a lesser threshold voltage to be used for the control gate structure than without the assisting gate structure.

A kind of anti-radiation reinforced SiC super-junction JFET structure and preparation method, from bottom to top are in order: drain metallization layer, N+ substrate layer, N buffer layer, P column region, N column region, P-base region, current expansion region, N+ source region, P+ gate region, isolation dielectric layer, gate metallization layer, source metallization layer.P column region and N column region are arranged alternately on the upper surface of N buffer layer, P column region is symmetrically arranged, and N column region is arranged between two P column regions.P column region and P-base region form a P-type doped region as a whole, and are connected with source metallization layer.Electrically conductive channel structure is formed between P+ gate region and P-base region, and the opening and closing of channel are realized by controlling the voltage on P+ gate region.The application effectively solves the problem of electric field concentration caused by high-energy charged particle bombardment in the device, reduces local high temperature, and greatly improves the anti-single-particle radiation capability of SiC JFET.