717 results about "Shallow trench isolation" patented technology

The invention discloses a self-isolation type image sensing structure, a sensor and a preparation method, and belongs to the field of semiconductors, the self-isolation type image sensing structure is characterized in that a shallow trench isolation structure is exposed after the back surface of a substrate is thinned, then a first semiconductor layer is extended on the back surface of the substrate, and a first isolation structure is prepared in the first semiconductor layer; sequentially depositing a second semiconductor material layer and a metal grating material layer on the first semiconductor layer; sequentially etching the metal grating material layer and the second semiconductor material layer to form a plurality of metal grating structures distributed at intervals and corresponding self-isolation structures; extending a plurality of photosensitive layers in the photosensitive region groove between the adjacent self-isolation structures to form a photosensitive region; and then activating, preparing a filter layer and the like are carried out to obtain a complete back-illuminated image sensor. The self-isolation photodiode is obtained by changing the structural distribution of the photodiode, unexpectedly, the problem that the substrate is damaged by doping is solved, meanwhile, the crosstalk effect is greatly reduced, and the performance of the image sensor is improved.

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps that a substrate is provided, the substrate comprises an SGT device region and a BCD device region which are transversely arranged, and the conduction types of the SGT device region and the BCD device region are different; forming a plurality of deep grooves in the SGT device region and the BCD device region; gate material filling is carried out on the multiple deep grooves, a first voltage-withstanding gate structure and at least one gate filling structure of the SGT device area and a second voltage-withstanding gate structure of the BCD device area are formed, and the first voltage-withstanding gate structure is close to the BCD device area; forming a shield gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, wherein the shallow trench isolation structures are located between the first voltage-withstanding gate structure and the second voltage-withstanding gate structure. According to the invention, the process cost of SGT and BCD device integration can be reduced, and the device connection is simplified.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

The invention discloses an image sensor and a manufacturing method thereof, the image sensor comprises a substrate, a photodiode, a storage node and a floating diffusion region which are arranged in the substrate at intervals, the storage node is arranged between the photodiode and the floating diffusion region, and one side, close to the storage node, of the photodiode is in a step shape; the first transmission grid electrode comprises a vertical grid electrode and a plane grid electrode, the vertical grid electrode is arranged in the substrate between the photodiode and the storage node, and the plane grid electrode is arranged on the vertical grid electrode and part of the substrate; a second transfer gate disposed on the substrate between the storage node and the floating diffusion region; the shallow trench isolation structure is arranged around the first transmission grid electrode, the storage node, the second transmission grid electrode and the floating diffusion region in a surrounding manner; and the shading structure is arranged on the first transmission grid electrode, the storage node and part of the second transmission grid electrode. According to the invention, the pixel transmission sensitivity can be improved, the parasitic light response of the storage node is reduced, and the imaging quality of the image sensor is improved.

The invention relates to the technical field of semiconductors, in particular to a shallow trench isolation structure and a process method thereof. The shallow trench isolation structure comprises a trench and a filling structure; the bottom of the groove is provided with a vertical side wall, the top of the groove is a trapezoidal opening, the trapezoidal opening is gradually enlarged from outside to inside, and the inclined side wall of the trapezoidal opening is intersected with the vertical side wall; the filling structure is filled in the groove. The process method of the shallow trench isolation structure comprises the following steps: introducing process gas into a process chamber to excite and generate plasma, and carrying out vertical bombardment on a substrate; gradually adjusting the bombardment angle of the plasma, and carrying out inclined bombardment on the bottom of the side wall of the groove; reducing the radio frequency power, gradually adjusting the bombardment angle of the plasma, and carrying out inclined bombardment on the top of the side wall of the groove; and a filling step: filling an insulating material into the groove. According to the shallow trench isolation structure and the process method thereof provided by the invention, the filling defect rate is low, and the reliability and the yield of shallow trench isolation are remarkably improved.

The present disclosure relates to semiconductor structures and, more particularly, to devices with a three dimensional channel and methods of manufacture. The structure includes: a drift region within a semiconductor substrate; a shallow trench isolation structure within the drift region; and a gate structure within the shallow trench isolation structure and extending to an upper surface of the semiconductor substrate adjacent to the drift region.

The invention discloses a method for forming a shallow trench isolation structure, and belongs to the technical field of semiconductors, the method for forming the shallow trench isolation structure comprises the steps of forming a first stop layer on a substrate, etching the first stop layer and a part of the substrate, and forming a trench; an insulating material is deposited in the groove and on the first stop layer, a second stop layer and a sacrificial layer are sequentially deposited on the insulating material, and the insulating material, the second stop layer and the sacrificial layer are provided with recesses in the groove; the sacrificial layer is ground and thinned until the second stop layer is exposed, and part of the sacrificial layer is reserved at the concave position of the second stop layer; and synchronously etching the second stop layer and the sacrificial layer until the second stop layer is completely removed. A stop layer and a sacrificial layer are deposited on an unground insulating material, the height difference of a wafer surface film layer is preliminarily compensated by using a grinding process, and then the residual film layer is synchronously consumed by using an etching process, so that the height difference of the insulating material is reduced, and the difficulty of a CMP (Chemical Mechanical Polishing) process is reduced.

The invention provides a manufacturing method of a shallow trench isolation structure. The manufacturing method comprises the following steps: patterning a pad oxide layer-silicon nitride layer laminated structure based on a photomask to obtain a first mask opening; etching the substrate to obtain an isolation groove; carrying out a pull-back process; depositing a sacrificial layer material in the isolation trench and the first mask opening; forming a shielding layer; patterning the shielding layer based on the photomask to obtain a second mask opening; removing the sacrificial layer material in the isolation groove and obtaining a sacrificial side wall located on the side wall of the opening of the silicon nitride layer; removing the shielding layer and depositing a silicon oxide layer in the isolation groove and the first mask opening; and removing the silicon nitride layer, the liner oxide layer and the sacrificial side wall. According to the method, the first mask opening and the second mask opening are formed in different steps based on the same photomask by adopting the pull-back process, the sacrificial side wall on the side wall of the opening of the silicon nitride layer is used for protecting the trench oxide layer from being lost in the subsequent removal process of the liner oxide layer, and the problem of a sunken region at the top edge of the shallow trench isolation region can be avoided or improved.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

The invention discloses a semiconductor structure forming method and a semiconductor structure. The method comprises the steps of providing a substrate; forming a shallow trench isolation structure connected with the buried oxide layer in the top layer silicon, wherein the shallow trench isolation structure is provided with a capacitor region; forming a first interlayer dielectric layer on the substrate; at least two adjacent and mutually independent capacitor openings and a plurality of first conductive openings are formed, the projection of each capacitor opening on the surface of the shallow trench isolation structure is located in the capacitor area, and the projection of each first conductive opening on the surface of the shallow trench isolation structure is located outside the capacitor area; the capacitor opening and the first conductive opening penetrate through the first interlayer dielectric layer, the shallow trench isolation structure and the buried oxide layer; a capacitor conductive structure is formed in each capacitor opening, a first conductive structure is formed in the first conductive opening, and the capacitor conductive structures form MOM capacitors with adjacent positive and negative plates. According to the invention, high integration level is considered while large capacitance is provided.

The present application discloses an HV device, comprising: a gate dielectric layer formed in a first trench, a gate conductive material layer formed on the surface of the gate dielectric layer, and a second dielectric layer filling a second trench formed between a second side face of a drain shallow trench isolation and a first side face of the first trench. The depths of the first trench and the second trench are equal. The first trench and the second trench connect with each other to form an overall trench. Bottom surfaces of the second dielectric layer and the gate dielectric layer are flush with each other. A first side face of the gate conductive material layer extends to the surface of the second dielectric layer. The present application also discloses a method for manufacturing the HV device.

The invention belongs to the technical field of visible light detection, and aims to realize accurate detection of multicolor visible light and monolithic integration of a multi-wavelength receiver. The invention provides a fully-integrated multicolor visible light detector based on a sub-wavelength polycrystalline silicon grating, which comprises three detectors capable of selectively detecting blue, green and red signals respectively. The principle is as follows: a one-dimensional sub-wavelength polycrystalline silicon grating in the multicolor detector is embedded in an upper SiO2 layer and a lower shallow trench isolation region to form a dielectric waveguide structure of which the middle is a high-refractive-index medium and the periphery is a low-refractive-index oxide layer. The period and the grating width of the sub-wavelength grating are changed, so that the incident polarized light and the sub-wavelength periodic structure are strongly coupled to cause a guided-mode resonance effect, and the sub-wavelength grating can be applied to a transmission optical filter. The size and the cost of the multicolor visible light communication system can be effectively reduced, and the data transmission rate of the system is greatly improved.

A method for forming a semiconductor structure and a semiconductor structure, the method comprising: providing a substrate including a high-voltage gate oxide region and high-voltage source and drain regions, the high-voltage source and drain regions being located at two sides of the high-voltage gate oxide region, and a shallow trench isolation structure between the high-voltage gate oxide region and the high-voltage source and drain regions; forming an isolating membrane on the surface of the preset region of the substrate, wherein the isolating membrane exposes the high-voltage gate oxide region; forming a first photoresist layer on the surface of the high-voltage gate oxide region, wherein the first photoresist layer exposes an edge region adjacent to the shallow trench isolation structure in the high-voltage gate oxide region; etching the exposed edge region in the high-voltage gate oxide region by taking the isolating film and the first photoresist layer as masks so as to reduce the height of the surface of the edge region of the high-voltage gate oxide region; and removing the first photoresist layer to expose the high-voltage gate oxide region, and forming a high-voltage device gate oxide layer on the high-voltage gate oxide region. The performance of the high-voltage device can be optimized, and the reliability of the high-voltage device is improved.

The invention discloses a shallow trench isolation structure and a preparation method thereof, and belongs to the technical field of semiconductors, and the preparation method comprises the steps: providing a semiconductor substrate, and sequentially forming a liner oxide layer and a nitride layer on the semiconductor substrate; forming grooves in the liner oxide layer, the nitride layer and the semiconductor substrate; the grooves extend into the semiconductor substrate from the nitride layer and divide the semiconductor substrate into a plurality of active regions; performing back etching on the pad oxide layer and the nitride layer on the two sides of the groove so as to expose the top surface of the active region of the semiconductor substrate close to the top of the side wall of the groove; forming an epitaxial layer on the inner wall of the groove and the exposed top surface of the active region of the semiconductor substrate; smoothing the top corner of the exposed active region of the semiconductor substrate to form a line oxide layer; and forming an isolation region in the groove, performing planarization processing on the isolation region to expose the nitride layer, and removing the nitride layer.

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor comprises a substrate which is divided into a plurality of active regions by a shallow trench isolation structure; the photodiode, the charge storage region and the floating diffusion region are arranged in the substrate at intervals; the global transmission grid is arranged between the photodiode and the charge storage region and comprises a first branch arranged on the active region and a second branch arranged on the shallow trench isolation structure; the transfer gate is arranged between the charge storage region and the floating diffusion region and comprises a first gate arranged on the active region and a second gate arranged on the shallow trench isolation structure; the first mask layer is arranged on the global transmission gate and the transfer gate, and the second mask layer is arranged on the first mask layer on the first branch and the first gate; the shading structure covers the first subsection, the charge storage area and part of the transfer grid electrode. According to the image sensor and the manufacturing method thereof, the parasitic light response is improved, and the manufacturing yield is improved.

Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.

The invention provides a radio frequency switch and a forming method, and the method comprises the steps: providing an SOI which comprises a switch region and a control region which are adjacent to each other; forming a plurality of first shallow trench isolation structures which are arranged at intervals in the top layer silicon of the switch region and the control region; the first shallow trench isolation structure, the buried oxide layer and partial thickness of the bottom layer silicon of the switch region are etched to form second shallow trenches which are arranged at intervals, and the width, located on the bottom layer silicon, of each second shallow trench is larger than the width, located on the buried oxide layer, of each second shallow trench; the second shallow trench is filled with oxide to form a second shallow trench isolation structure, and the thickness of the second shallow trench isolation structure is larger than that of the first shallow trench isolation structure; gate structures of the MOS transistor are formed on the surface of the top layer silicon of the switch region and the control region, a source end and a drain end of the MOS transistor are formed in the top layer silicon on the two sides of each gate structure respectively, and the second shallow trench isolation structure is partially located below the source end and the drain end of the switch region.

A semiconductor structure is provided that includes a resistive random access memory on a surface of a bit line (28) embedded in a shallow trench isolation structure (12). The structure may also include a source line (SL) over the bit line (28) or embedded in the shallow trench isolation structure (12).

In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.

A semiconductor device includes a backside contact, a shallow trench isolation (STI), and a backside dielectric trench isolation (BDTI) below the STI. A top surface of the BDTI is connected to the STI on a backside of a high voltage region of the semiconductor device, a bottom surface of the BDTI is connected to a backside power interconnect, and the BDTI isolates a backside contact from a substrate.

Embodiments of the invention include a semiconductor structure having first stacked transistors including a first upper transistor over a first lower transistor. Second stacked transistors are adjacent to the first stacked transistors. A gate structure includes a gate extension into a shallow trench isolation region, where a non-conductive frontside gate cut through the gate structure isolates the first stacked transistors and the second stacked transistors, where a contact through the non-conductive frontside gate cut contacts the gate extension and is coupled to the first lower transistor.

The invention discloses a manufacturing method of a shallow trench isolation structure and the shallow trench isolation structure. The manufacturing method of the shallow trench isolation structure comprises the following steps: forming a hard mask layer with a protection structure on a semiconductor layer; forming a groove which penetrates through the hard mask layer and extends into the semiconductor layer; forming an isolation medium in the groove, wherein the protection structure is adjacent to the isolation medium in the groove; and removing the hard mask layer to form a shallow trench isolation structure, wherein in the process of removing the hard mask layer, the side wall of the isolation medium in the groove is protected by the protection structure, so that a gap is prevented from being formed between the semiconductor layer and the side wall of the isolation medium.

According to the preparation method of the semiconductor structure and the semiconductor structure provided by the invention, the longitudinal space of a chip is fully utilized, and a gate dielectric layer, an active layer and a first source-drain layer are sequentially formed on a shallow trench isolation structure in a substrate, so that a longitudinally arranged high-voltage gate oxide layer MOS (Metal Oxide Semiconductor) tube is formed; therefore, the transverse area of the high-voltage gate oxide layer MOS tube is reduced, and the integration level of a chip where the high-voltage gate oxide layer MOS tube is located is improved. As the high-voltage gate oxide MOS tube is positioned above the shallow trench isolation structure in the substrate and is positioned on a different horizontal plane from the first MOS tube positioned in the substrate in the chip, the interference of the high-voltage gate oxide MOS tube on the adjacent first MOS tube is reduced. Therefore, an isolation structure does not need to be arranged between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube, the horizontal distance between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube is reduced, the overall area of a chip is reduced, the integration degree of the chip is further improved, and the preparation cost of the chip is reduced.

A semiconductor device includes a logic device including a first portion of a first substrate extending vertically below a first source / drain region, a second portion of the first substrate extending vertically below a second source / drain region, a first shallow trench isolation (STI) extending vertically and isolating the first portion of the first substrate and the second portion of the first substrate, a backside power delivery network (BSPDN) below the logic device, a first dielectric layer extending vertically through sidewalls of a backside contact. The first dielectric layer isolates the backside contact from the first portion of the first substrate and the second portion of the first substrate.

A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.

The present invention discloses a method and structure for integrating CMOS and self-aligned silicon-germanium (SGe) HBTs. The method comprises: forming multiple shallow trench isolation regions on a silicon substrate; forming polysilicon gates, gate silicon oxide, and lightly doped regions in the CMOS active region; opening a base window in the HBT region and forming a selective ion implantation region; forming a SiGe base region; forming a sacrificial emitter region; etching to expose the surface of the outer region of the SiGe base region and forming an extrinsic base region; forming an emitter window and exposing the SiGe surface of the underlying SiGe base region; forming a silicon emitter region in the emitter window, and photolithographically patterning the emitter region and the extrinsic base region. The present invention utilizes a novel sacrificial emitter process, combined with a method for self-aligning the raised extrinsic base region and the emitter region, effectively reducing process complexity and making the device process compatible with standard CMOS and other passive device processes.

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

A method of forming a semiconductor device includes forming a fin structure protruding over a substrate, the fin structure including a fin and alternating layers of a first semiconductor material and a second semiconductor material over the fin; forming shallow trench isolation (STI) regions on opposite sides of the fin structure; forming an STI protection structure on the upper surface of the STI region; forming a dummy gate structure over the fin structure; forming a source / drain opening in the fin structure to expose the first semiconductor material and the second semiconductor material; replacing the first semiconductor material disposed under the dummy gate structure with a sacrificial material; after replacement, forming a source / drain region in the source / drain opening; after forming the source / drain region, the sacrificial material is removed and the dummy gate structure is replaced with a replacement gate structure. The embodiment of the invention also relates to a semiconductor device.

The present application provides a power device and a method for preparing the same. The preparation method comprises the following steps: providing a silicon substrate, forming a well region, a drift region located in the well region, and a shallow trench isolation structure located in the drift region in the silicon substrate, forming a liner isolation layer between the shallow trench isolation structure and the silicon substrate, defining an injection window on the drift region, the injection window being adjacent to the shallow trench isolation structure, and the injection window exposing the silicon substrate; performing ion implantation on the injection window in the drift region to form a destructive layer mainly composed of amorphous silicon on the surface of the silicon substrate corresponding to the injection window; performing thermal oxidation treatment on the region corresponding to the destructive layer to form a high-voltage gate oxide layer in the injection window, the high-voltage gate oxide layer being adjacent to the shallow trench isolation structure. The present application helps to avoid local breakdown of the device and can improve the electrical performance of the device.