1202 results about "Shallow trench isolation" patented technology

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

The invention discloses a self-isolation type image sensing structure, a sensor and a preparation method, and belongs to the field of semiconductors, the self-isolation type image sensing structure is characterized in that a shallow trench isolation structure is exposed after the back surface of a substrate is thinned, then a first semiconductor layer is extended on the back surface of the substrate, and a first isolation structure is prepared in the first semiconductor layer; sequentially depositing a second semiconductor material layer and a metal grating material layer on the first semiconductor layer; sequentially etching the metal grating material layer and the second semiconductor material layer to form a plurality of metal grating structures distributed at intervals and corresponding self-isolation structures; extending a plurality of photosensitive layers in the photosensitive region groove between the adjacent self-isolation structures to form a photosensitive region; and then activating, preparing a filter layer and the like are carried out to obtain a complete back-illuminated image sensor. The self-isolation photodiode is obtained by changing the structural distribution of the photodiode, unexpectedly, the problem that the substrate is damaged by doping is solved, meanwhile, the crosstalk effect is greatly reduced, and the performance of the image sensor is improved.

The invention provides a forming method of a double-shallow-trench isolation structure with different depths and a semiconductor device, and the method comprises the steps: S1, providing a substrate which comprises a first region and a second region; s2, sequentially forming a first dielectric layer, a first hard mask layer and a second hard mask layer on the substrate, wherein the first hard mask layer and the second hard mask layer are made of different materials; s3, forming a first initial opening in the second hard mask layer of the first region, performing etching by taking the second hard mask layer as a mask, and stopping forming a first opening on the surface of the first dielectric layer; s4, forming a second initial opening in the second hard mask layer of the second region, etching by taking the second hard mask layer as a mask, and stopping on the surface of the substrate to form a second opening; s5, removing the second hard mask layer; and S6, etching the first opening and the second opening at the same time by taking the first hard mask layer as a mask, forming a first shallow trench below the first opening, and forming a second shallow trench below the second opening. The depth difference between the first shallow trench and the second shallow trench is determined by the thickness of the first dielectric layer.

A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors. Each field effect transistor includes source / drain regions located on opposite sides of the field effect transistors. A shallow trench isolation region located between adjacent field effect transistors electrically separates the plurality of field effect transistors from one another. The shallow trench isolation region has a tapered profile. A backside isolation region is embedded within the shallow trench isolation region and cuts through the source / drain regions. The backside isolation region has a reverse tapered profile.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps that a substrate is provided, the substrate comprises an SGT device region and a BCD device region which are transversely arranged, and the conduction types of the SGT device region and the BCD device region are different; forming a plurality of deep grooves in the SGT device region and the BCD device region; gate material filling is carried out on the multiple deep grooves, a first voltage-withstanding gate structure and at least one gate filling structure of the SGT device area and a second voltage-withstanding gate structure of the BCD device area are formed, and the first voltage-withstanding gate structure is close to the BCD device area; forming a shield gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, wherein the shallow trench isolation structures are located between the first voltage-withstanding gate structure and the second voltage-withstanding gate structure. According to the invention, the process cost of SGT and BCD device integration can be reduced, and the device connection is simplified.

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

A semiconductor device includes a semiconductor substrate including shallow trench isolation (STI) regions, a semiconductor fin between the STI regions, and a STI liner on an upper surface of the STI regions. A STI layer is in each of the STI regions, and includes a liner opening exposing a portion of the STI layer. A source / drain is on a sidewall of the semiconductor fin. A multi-stage backside contact is on the source / drain and contacting the portion of the STI layer via the liner opening.

Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates; low oxide trench dishing, and high oxide: SiN selectivity. Dual chemical additives comprise at least one silicone-containing compound comprising at least one of (1) ethylene oxide and propylene oxide (EO-PO) group, and at least one of substituted ethylene diamine group on the same molecule; and (2) at least one non-ionic organic molecule having at least two, preferably at least four hydroxyl functional groups.

The invention provides a preparation method of a shallow trench isolation structure and a semiconductor structure, and particularly relates to the technical field of semiconductors. The preparation method of the shallow trench isolation structure comprises the steps that a substrate is provided, the substrate comprises a substrate body and trench oxide formed in the substrate body, and the portion, protruding out of the substrate body, of the trench oxide is provided with a recess; forming a patterned hard mask layer on the substrate, wherein the patterned hard mask layer is provided with an opening in a region corresponding to the trench oxide; forming an oxide layer on the patterned hard mask layer, wherein the oxide layer covers the trench oxide and fills the recess; planarizing the oxide layer by taking the patterned hard mask layer as a stop layer; and removing the patterned hard mask layer. The method can effectively improve the sinking problem in the shallow trench isolation structure and improve the reliability of the device.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

The invention discloses a manufacturing method of a semiconductor structure, which belongs to the technical field of semiconductors, and comprises the following steps: providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate; etching a part of the pad oxide layer, the pad nitride layer and the substrate to form a shallow trench; an insulating medium is deposited in the shallow trench, the insulating medium is planarized for the first time, and the insulating medium is flush with the pad nitride layers on the two sides; performing micro-etching treatment on the pad nitriding layer to form a micro-structure layer, and performing micro-etching by adopting a weak physical sputtering mode; oxidizing the pad nitride layer to form an intermediate oxide layer; equivalently removing the intermediate oxide layer and part of the insulating medium; repeating the micro-etching treatment, the oxidation treatment and the equivalent removal step until the pad nitride layer is removed; and removing the pad oxide layer and a part of the insulating medium. According to the manufacturing method of the semiconductor structure provided by the invention, the phenomenon that the corner edge of the shallow trench isolation structure is sunken can be avoided, and the performance of the semiconductor structure is improved.

The invention discloses a preparation method of a semiconductor structure, and belongs to the technical field of semiconductors. The preparation method at least comprises the following steps: providing a substrate; sequentially forming a pad oxide layer, an intermediate material layer and a pad nitride layer on the substrate; etching the pad nitride layer, the intermediate material layer, the pad oxide layer and the substrate to form a shallow trench, and forming an insulating medium layer in the shallow trench until the insulating medium layer in the shallow trench protrudes out of the pad nitride layer; planarizing the insulating dielectric layer until the pad nitride layer is exposed; performing oxidation treatment on the intermediate material layer to obtain an oxidized material layer; etching to remove the pad nitride layer; and planarizing the oxide material layer and the insulating medium layer. Through the preparation method of the semiconductor structure provided by the invention, dish-shaped recesses can be prevented from appearing on the surface of the shallow trench isolation structure, and the flatness of the surface of the shallow trench isolation structure is improved.

Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and / or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and / or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.

The invention discloses an image sensor and a manufacturing method thereof, the image sensor comprises a substrate, a photodiode, a storage node and a floating diffusion region which are arranged in the substrate at intervals, the storage node is arranged between the photodiode and the floating diffusion region, and one side, close to the storage node, of the photodiode is in a step shape; the first transmission grid electrode comprises a vertical grid electrode and a plane grid electrode, the vertical grid electrode is arranged in the substrate between the photodiode and the storage node, and the plane grid electrode is arranged on the vertical grid electrode and part of the substrate; a second transfer gate disposed on the substrate between the storage node and the floating diffusion region; the shallow trench isolation structure is arranged around the first transmission grid electrode, the storage node, the second transmission grid electrode and the floating diffusion region in a surrounding manner; and the shading structure is arranged on the first transmission grid electrode, the storage node and part of the second transmission grid electrode. According to the invention, the pixel transmission sensitivity can be improved, the parasitic light response of the storage node is reduced, and the imaging quality of the image sensor is improved.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

The invention relates to the technical field of semiconductors, in particular to a shallow trench isolation structure and a process method thereof. The shallow trench isolation structure comprises a trench and a filling structure; the bottom of the groove is provided with a vertical side wall, the top of the groove is a trapezoidal opening, the trapezoidal opening is gradually enlarged from outside to inside, and the inclined side wall of the trapezoidal opening is intersected with the vertical side wall; the filling structure is filled in the groove. The process method of the shallow trench isolation structure comprises the following steps: introducing process gas into a process chamber to excite and generate plasma, and carrying out vertical bombardment on a substrate; gradually adjusting the bombardment angle of the plasma, and carrying out inclined bombardment on the bottom of the side wall of the groove; reducing the radio frequency power, gradually adjusting the bombardment angle of the plasma, and carrying out inclined bombardment on the top of the side wall of the groove; and a filling step: filling an insulating material into the groove. According to the shallow trench isolation structure and the process method thereof provided by the invention, the filling defect rate is low, and the reliability and the yield of shallow trench isolation are remarkably improved.

The present disclosure relates to semiconductor structures and, more particularly, to devices with a three dimensional channel and methods of manufacture. The structure includes: a drift region within a semiconductor substrate; a shallow trench isolation structure within the drift region; and a gate structure within the shallow trench isolation structure and extending to an upper surface of the semiconductor substrate adjacent to the drift region.

The invention discloses a method for forming a shallow trench isolation structure, and belongs to the technical field of semiconductors, the method for forming the shallow trench isolation structure comprises the steps of forming a first stop layer on a substrate, etching the first stop layer and a part of the substrate, and forming a trench; an insulating material is deposited in the groove and on the first stop layer, a second stop layer and a sacrificial layer are sequentially deposited on the insulating material, and the insulating material, the second stop layer and the sacrificial layer are provided with recesses in the groove; the sacrificial layer is ground and thinned until the second stop layer is exposed, and part of the sacrificial layer is reserved at the concave position of the second stop layer; and synchronously etching the second stop layer and the sacrificial layer until the second stop layer is completely removed. A stop layer and a sacrificial layer are deposited on an unground insulating material, the height difference of a wafer surface film layer is preliminarily compensated by using a grinding process, and then the residual film layer is synchronously consumed by using an etching process, so that the height difference of the insulating material is reduced, and the difficulty of a CMP (Chemical Mechanical Polishing) process is reduced.

The invention relates to a deep and shallow trench isolation structure and process, and the process comprises the steps: providing a substrate, and depositing a multifunctional layer on the surface of the substrate; forming a first pattern on a partial region of the multifunctional layer through a photoetching technology; etching for the first time by using the first pattern, removing a part of material of the multifunctional layer and etching the substrate to form a shallow trench structure, and removing the first pattern mask; forming a second pattern on the non-etched region through the photoetching technology again; performing second etching by using the second pattern, removing the multifunctional layer in an unetched region to the surface of the substrate, and removing the second pattern mask; and under the protection effect of the multifunctional layer, carrying out third etching on the exposed region, and processing the exposed region to a designed depth to form a shallow trench structure and a deep trench structure with different depths. According to the invention, the height difference of the etching stop layer after STI etching in different areas is eliminated, so that the subsequent oxide filling and chemical mechanical polishing processes are easy to control, and the quality of the device is improved.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

A semiconductor structure including first shallow trench isolation regions and second shallow trench isolation regions, where the second shallow trench isolation regions are deeper than the first shallow trench isolation regions, and backside contact structures in direct contact with and physically separated by at least one of the second shallow trench isolation regions.

The invention discloses a deep trench isolation structure and a manufacturing process method thereof, an injection layer of a second conduction type is arranged on a substrate of a first conduction type, and a deep trap of the second conduction type is arranged on the injection layer; the surface layer of the deep well is provided with a shallow trench isolation structure, and the outer side of the shallow trench isolation structure is provided with a well region of a second conductive type; a deep trench is formed in the shallow trench isolation structure through etching; filling materials which are filled in sections are arranged in the deep grooves; wherein the lower part in the deep trench is filled with a silicon oxide material, and the upper part in the deep trench is filled with a polycrystalline silicon material; filling in the deep trench is divided into two sections of composite filling made of different materials, the portion located on the lower portion of the deep trench is made of silicon oxide, the portion located on the upper middle portion of the deep trench is made of polycrystalline silicon, the structure is further optimized, the bottom of DTI polycrystalline silicon is shortened to the position below an injection layer, the bottom of the DTI polycrystalline silicon can pull up a high peak electric field in a depletion region, and therefore the reliability of the deep trench is improved. And the breakdown voltage of the device is improved.

The invention provides a manufacturing method of a shallow trench isolation structure. The manufacturing method comprises the following steps: patterning a pad oxide layer-silicon nitride layer laminated structure based on a photomask to obtain a first mask opening; etching the substrate to obtain an isolation groove; carrying out a pull-back process; depositing a sacrificial layer material in the isolation trench and the first mask opening; forming a shielding layer; patterning the shielding layer based on the photomask to obtain a second mask opening; removing the sacrificial layer material in the isolation groove and obtaining a sacrificial side wall located on the side wall of the opening of the silicon nitride layer; removing the shielding layer and depositing a silicon oxide layer in the isolation groove and the first mask opening; and removing the silicon nitride layer, the liner oxide layer and the sacrificial side wall. According to the method, the first mask opening and the second mask opening are formed in different steps based on the same photomask by adopting the pull-back process, the sacrificial side wall on the side wall of the opening of the silicon nitride layer is used for protecting the trench oxide layer from being lost in the subsequent removal process of the liner oxide layer, and the problem of a sunken region at the top edge of the shallow trench isolation region can be avoided or improved.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

A semiconductor device includes a substrate, a shallow trench isolation, and a plurality of bit line structures. The substrate includes a plurality of active regions. The shallow trench isolation is arranged in the substrate and comprises a first insulating layer higher than the surface of the substrate and a second insulating layer lower than the surface of the substrate. The bit line structure is arranged on the substrate and at least comprises a conductive layer. At least one bit line structure crosses the active region and the first insulating layer and the second insulating layer of the shallow trench isolation, and is respectively provided with a first insulating stack structure, a second insulating stack structure and a third insulating stack structure. The first insulating stack structure, the second insulating stack structure, and the third insulating stack structure include top surfaces coplanar with each other and different stack materials. Therefore, the assembly efficiency of the bit line structure is improved, and the operation performance of the semiconductor device is optimized.

A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.