920 results about "Shallow trench isolation" patented technology

The invention discloses a self-isolation type image sensing structure, a sensor and a preparation method, and belongs to the field of semiconductors, the self-isolation type image sensing structure is characterized in that a shallow trench isolation structure is exposed after the back surface of a substrate is thinned, then a first semiconductor layer is extended on the back surface of the substrate, and a first isolation structure is prepared in the first semiconductor layer; sequentially depositing a second semiconductor material layer and a metal grating material layer on the first semiconductor layer; sequentially etching the metal grating material layer and the second semiconductor material layer to form a plurality of metal grating structures distributed at intervals and corresponding self-isolation structures; extending a plurality of photosensitive layers in the photosensitive region groove between the adjacent self-isolation structures to form a photosensitive region; and then activating, preparing a filter layer and the like are carried out to obtain a complete back-illuminated image sensor. The self-isolation photodiode is obtained by changing the structural distribution of the photodiode, unexpectedly, the problem that the substrate is damaged by doping is solved, meanwhile, the crosstalk effect is greatly reduced, and the performance of the image sensor is improved.

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps that a substrate is provided, the substrate comprises an SGT device region and a BCD device region which are transversely arranged, and the conduction types of the SGT device region and the BCD device region are different; forming a plurality of deep grooves in the SGT device region and the BCD device region; gate material filling is carried out on the multiple deep grooves, a first voltage-withstanding gate structure and at least one gate filling structure of the SGT device area and a second voltage-withstanding gate structure of the BCD device area are formed, and the first voltage-withstanding gate structure is close to the BCD device area; forming a shield gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, wherein the shallow trench isolation structures are located between the first voltage-withstanding gate structure and the second voltage-withstanding gate structure. According to the invention, the process cost of SGT and BCD device integration can be reduced, and the device connection is simplified.

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

The invention discloses a manufacturing method of a semiconductor structure, which belongs to the technical field of semiconductors, and comprises the following steps: providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate; etching a part of the pad oxide layer, the pad nitride layer and the substrate to form a shallow trench; an insulating medium is deposited in the shallow trench, the insulating medium is planarized for the first time, and the insulating medium is flush with the pad nitride layers on the two sides; performing micro-etching treatment on the pad nitriding layer to form a micro-structure layer, and performing micro-etching by adopting a weak physical sputtering mode; oxidizing the pad nitride layer to form an intermediate oxide layer; equivalently removing the intermediate oxide layer and part of the insulating medium; repeating the micro-etching treatment, the oxidation treatment and the equivalent removal step until the pad nitride layer is removed; and removing the pad oxide layer and a part of the insulating medium. According to the manufacturing method of the semiconductor structure provided by the invention, the phenomenon that the corner edge of the shallow trench isolation structure is sunken can be avoided, and the performance of the semiconductor structure is improved.

Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

The invention discloses an image sensor and a manufacturing method thereof, the image sensor comprises a substrate, a photodiode, a storage node and a floating diffusion region which are arranged in the substrate at intervals, the storage node is arranged between the photodiode and the floating diffusion region, and one side, close to the storage node, of the photodiode is in a step shape; the first transmission grid electrode comprises a vertical grid electrode and a plane grid electrode, the vertical grid electrode is arranged in the substrate between the photodiode and the storage node, and the plane grid electrode is arranged on the vertical grid electrode and part of the substrate; a second transfer gate disposed on the substrate between the storage node and the floating diffusion region; the shallow trench isolation structure is arranged around the first transmission grid electrode, the storage node, the second transmission grid electrode and the floating diffusion region in a surrounding manner; and the shading structure is arranged on the first transmission grid electrode, the storage node and part of the second transmission grid electrode. According to the invention, the pixel transmission sensitivity can be improved, the parasitic light response of the storage node is reduced, and the imaging quality of the image sensor is improved.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

The invention relates to the technical field of semiconductors, in particular to a shallow trench isolation structure and a process method thereof. The shallow trench isolation structure comprises a trench and a filling structure; the bottom of the groove is provided with a vertical side wall, the top of the groove is a trapezoidal opening, the trapezoidal opening is gradually enlarged from outside to inside, and the inclined side wall of the trapezoidal opening is intersected with the vertical side wall; the filling structure is filled in the groove. The process method of the shallow trench isolation structure comprises the following steps: introducing process gas into a process chamber to excite and generate plasma, and carrying out vertical bombardment on a substrate; gradually adjusting the bombardment angle of the plasma, and carrying out inclined bombardment on the bottom of the side wall of the groove; reducing the radio frequency power, gradually adjusting the bombardment angle of the plasma, and carrying out inclined bombardment on the top of the side wall of the groove; and a filling step: filling an insulating material into the groove. According to the shallow trench isolation structure and the process method thereof provided by the invention, the filling defect rate is low, and the reliability and the yield of shallow trench isolation are remarkably improved.

The present disclosure relates to semiconductor structures and, more particularly, to devices with a three dimensional channel and methods of manufacture. The structure includes: a drift region within a semiconductor substrate; a shallow trench isolation structure within the drift region; and a gate structure within the shallow trench isolation structure and extending to an upper surface of the semiconductor substrate adjacent to the drift region.

The invention discloses a method for forming a shallow trench isolation structure, and belongs to the technical field of semiconductors, the method for forming the shallow trench isolation structure comprises the steps of forming a first stop layer on a substrate, etching the first stop layer and a part of the substrate, and forming a trench; an insulating material is deposited in the groove and on the first stop layer, a second stop layer and a sacrificial layer are sequentially deposited on the insulating material, and the insulating material, the second stop layer and the sacrificial layer are provided with recesses in the groove; the sacrificial layer is ground and thinned until the second stop layer is exposed, and part of the sacrificial layer is reserved at the concave position of the second stop layer; and synchronously etching the second stop layer and the sacrificial layer until the second stop layer is completely removed. A stop layer and a sacrificial layer are deposited on an unground insulating material, the height difference of a wafer surface film layer is preliminarily compensated by using a grinding process, and then the residual film layer is synchronously consumed by using an etching process, so that the height difference of the insulating material is reduced, and the difficulty of a CMP (Chemical Mechanical Polishing) process is reduced.

The invention relates to a deep and shallow trench isolation structure and process, and the process comprises the steps: providing a substrate, and depositing a multifunctional layer on the surface of the substrate; forming a first pattern on a partial region of the multifunctional layer through a photoetching technology; etching for the first time by using the first pattern, removing a part of material of the multifunctional layer and etching the substrate to form a shallow trench structure, and removing the first pattern mask; forming a second pattern on the non-etched region through the photoetching technology again; performing second etching by using the second pattern, removing the multifunctional layer in an unetched region to the surface of the substrate, and removing the second pattern mask; and under the protection effect of the multifunctional layer, carrying out third etching on the exposed region, and processing the exposed region to a designed depth to form a shallow trench structure and a deep trench structure with different depths. According to the invention, the height difference of the etching stop layer after STI etching in different areas is eliminated, so that the subsequent oxide filling and chemical mechanical polishing processes are easy to control, and the quality of the device is improved.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

A semiconductor structure including first shallow trench isolation regions and second shallow trench isolation regions, where the second shallow trench isolation regions are deeper than the first shallow trench isolation regions, and backside contact structures in direct contact with and physically separated by at least one of the second shallow trench isolation regions.

The invention provides a manufacturing method of a shallow trench isolation structure. The manufacturing method comprises the following steps: patterning a pad oxide layer-silicon nitride layer laminated structure based on a photomask to obtain a first mask opening; etching the substrate to obtain an isolation groove; carrying out a pull-back process; depositing a sacrificial layer material in the isolation trench and the first mask opening; forming a shielding layer; patterning the shielding layer based on the photomask to obtain a second mask opening; removing the sacrificial layer material in the isolation groove and obtaining a sacrificial side wall located on the side wall of the opening of the silicon nitride layer; removing the shielding layer and depositing a silicon oxide layer in the isolation groove and the first mask opening; and removing the silicon nitride layer, the liner oxide layer and the sacrificial side wall. According to the method, the first mask opening and the second mask opening are formed in different steps based on the same photomask by adopting the pull-back process, the sacrificial side wall on the side wall of the opening of the silicon nitride layer is used for protecting the trench oxide layer from being lost in the subsequent removal process of the liner oxide layer, and the problem of a sunken region at the top edge of the shallow trench isolation region can be avoided or improved.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

A semiconductor device includes a substrate, a shallow trench isolation, and a plurality of bit line structures. The substrate includes a plurality of active regions. The shallow trench isolation is arranged in the substrate and comprises a first insulating layer higher than the surface of the substrate and a second insulating layer lower than the surface of the substrate. The bit line structure is arranged on the substrate and at least comprises a conductive layer. At least one bit line structure crosses the active region and the first insulating layer and the second insulating layer of the shallow trench isolation, and is respectively provided with a first insulating stack structure, a second insulating stack structure and a third insulating stack structure. The first insulating stack structure, the second insulating stack structure, and the third insulating stack structure include top surfaces coplanar with each other and different stack materials. Therefore, the assembly efficiency of the bit line structure is improved, and the operation performance of the semiconductor device is optimized.

The invention discloses a semiconductor structure forming method and a semiconductor structure. The method comprises the steps of providing a substrate; forming a shallow trench isolation structure connected with the buried oxide layer in the top layer silicon, wherein the shallow trench isolation structure is provided with a capacitor region; forming a first interlayer dielectric layer on the substrate; at least two adjacent and mutually independent capacitor openings and a plurality of first conductive openings are formed, the projection of each capacitor opening on the surface of the shallow trench isolation structure is located in the capacitor area, and the projection of each first conductive opening on the surface of the shallow trench isolation structure is located outside the capacitor area; the capacitor opening and the first conductive opening penetrate through the first interlayer dielectric layer, the shallow trench isolation structure and the buried oxide layer; a capacitor conductive structure is formed in each capacitor opening, a first conductive structure is formed in the first conductive opening, and the capacitor conductive structures form MOM capacitors with adjacent positive and negative plates. According to the invention, high integration level is considered while large capacitance is provided.

The invention provides a preparation method of a shallow trench isolation structure and a semiconductor device, and the preparation method comprises the following steps: providing a substrate which comprises a substrate and a patterned hard mask layer on the substrate; depositing a hard mask oxide layer on the substrate, wherein the hard mask oxide layer covers the surface of the hard mask layer and the side wall and the bottom wall of the pattern; etching the substrate to form a plurality of first grooves corresponding to the patterns on the hard mask layer, wherein the first grooves extend to the substrate, and hard mask oxide layers are reserved on the side walls of the patterns of the hard mask layer; removing the hard mask oxide layer on the side wall of the pattern of the hard mask layer through wet etching to form a second groove; forming a liner oxide layer on the side wall and the bottom wall of the second groove; filling the second groove; removing the hard mask layer; and growing a sacrificial oxide layer in the active region. According to the preparation method of the shallow trench isolation structure, the unfilled corner problem of shallow trench isolation can be reduced, the electric leakage of a semiconductor device is improved, and the overall performance of the semiconductor device is improved.

The present application discloses an HV device, comprising: a gate dielectric layer formed in a first trench, a gate conductive material layer formed on the surface of the gate dielectric layer, and a second dielectric layer filling a second trench formed between a second side face of a drain shallow trench isolation and a first side face of the first trench. The depths of the first trench and the second trench are equal. The first trench and the second trench connect with each other to form an overall trench. Bottom surfaces of the second dielectric layer and the gate dielectric layer are flush with each other. A first side face of the gate conductive material layer extends to the surface of the second dielectric layer. The present application also discloses a method for manufacturing the HV device.

The invention belongs to the technical field of visible light detection, and aims to realize accurate detection of multicolor visible light and monolithic integration of a multi-wavelength receiver. The invention provides a fully-integrated multicolor visible light detector based on a sub-wavelength polycrystalline silicon grating, which comprises three detectors capable of selectively detecting blue, green and red signals respectively. The principle is as follows: a one-dimensional sub-wavelength polycrystalline silicon grating in the multicolor detector is embedded in an upper SiO2 layer and a lower shallow trench isolation region to form a dielectric waveguide structure of which the middle is a high-refractive-index medium and the periphery is a low-refractive-index oxide layer. The period and the grating width of the sub-wavelength grating are changed, so that the incident polarized light and the sub-wavelength periodic structure are strongly coupled to cause a guided-mode resonance effect, and the sub-wavelength grating can be applied to a transmission optical filter. The size and the cost of the multicolor visible light communication system can be effectively reduced, and the data transmission rate of the system is greatly improved.

A method for forming a semiconductor structure and a semiconductor structure, the method comprising: providing a substrate including a high-voltage gate oxide region and high-voltage source and drain regions, the high-voltage source and drain regions being located at two sides of the high-voltage gate oxide region, and a shallow trench isolation structure between the high-voltage gate oxide region and the high-voltage source and drain regions; forming an isolating membrane on the surface of the preset region of the substrate, wherein the isolating membrane exposes the high-voltage gate oxide region; forming a first photoresist layer on the surface of the high-voltage gate oxide region, wherein the first photoresist layer exposes an edge region adjacent to the shallow trench isolation structure in the high-voltage gate oxide region; etching the exposed edge region in the high-voltage gate oxide region by taking the isolating film and the first photoresist layer as masks so as to reduce the height of the surface of the edge region of the high-voltage gate oxide region; and removing the first photoresist layer to expose the high-voltage gate oxide region, and forming a high-voltage device gate oxide layer on the high-voltage gate oxide region. The performance of the high-voltage device can be optimized, and the reliability of the high-voltage device is improved.

The invention discloses a shallow trench isolation structure and a preparation method thereof, and belongs to the technical field of semiconductors, and the preparation method comprises the steps: providing a semiconductor substrate, and sequentially forming a liner oxide layer and a nitride layer on the semiconductor substrate; forming grooves in the liner oxide layer, the nitride layer and the semiconductor substrate; the grooves extend into the semiconductor substrate from the nitride layer and divide the semiconductor substrate into a plurality of active regions; performing back etching on the pad oxide layer and the nitride layer on the two sides of the groove so as to expose the top surface of the active region of the semiconductor substrate close to the top of the side wall of the groove; forming an epitaxial layer on the inner wall of the groove and the exposed top surface of the active region of the semiconductor substrate; smoothing the top corner of the exposed active region of the semiconductor substrate to form a line oxide layer; and forming an isolation region in the groove, performing planarization processing on the isolation region to expose the nitride layer, and removing the nitride layer.

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor comprises a substrate which is divided into a plurality of active regions by a shallow trench isolation structure; the photodiode, the charge storage region and the floating diffusion region are arranged in the substrate at intervals; the global transmission grid is arranged between the photodiode and the charge storage region and comprises a first branch arranged on the active region and a second branch arranged on the shallow trench isolation structure; the transfer gate is arranged between the charge storage region and the floating diffusion region and comprises a first gate arranged on the active region and a second gate arranged on the shallow trench isolation structure; the first mask layer is arranged on the global transmission gate and the transfer gate, and the second mask layer is arranged on the first mask layer on the first branch and the first gate; the shading structure covers the first subsection, the charge storage area and part of the transfer grid electrode. According to the image sensor and the manufacturing method thereof, the parasitic light response is improved, and the manufacturing yield is improved.

A wrap-around dielectric structure prevents backside contacts shorting to gates in nanosheet field effect transistors (FETs). A method of making same includes providing a sacrificial layer under a nanosheet stack adjacent shallow trench isolation (STI) regions, recessing the STI regions' liner to from gaps in communication with the sacrificial layer, removing the sacrificial layer to form a cavity, and filling the cavity and gaps with a continuous dielectric material which wraps around a subsequently formed backside contact.

Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.

A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.

The invention relates to the technical field of semiconductor manufacturing, and discloses a method for manufacturing a semiconductor isolation structure, which comprises the following steps of: (1) forming a plurality of shallow isolation corrosion grooves on one surface of a monocrystalline silicon substrate by using an STI (shallow trench isolation) process; forming a plurality of deep isolation corrosion grooves in the other surface of the monocrystalline silicon substrate by using a Trench process; (2) etching and forming an isolation channel with the design thickness of d1 on the monocrystalline silicon substrate with the plurality of shallow isolation etching grooves and the plurality of deep isolation etching grooves by using a wet etching process, so that the isolation channel, the plurality of shallow isolation etching grooves and the plurality of deep isolation etching grooves are communicated with one another to form an isolation structure; and (3) putting the monocrystalline silicon substrate with the isolation structure into thermal oxidation equipment, filling the isolation structure with silicon dioxide by using a thermal oxidation process, and expanding the thickness of an isolation channel from a design thickness d1 to a target thickness d2. The isolation structure prepared by the method is good in electrical isolation capability, and can meet the requirements of products with high working voltage and large working current.

The invention provides a radio frequency switch and a forming method, and the method comprises the steps: providing an SOI which comprises a switch region and a control region which are adjacent to each other; forming a plurality of first shallow trench isolation structures which are arranged at intervals in the top layer silicon of the switch region and the control region; the first shallow trench isolation structure, the buried oxide layer and partial thickness of the bottom layer silicon of the switch region are etched to form second shallow trenches which are arranged at intervals, and the width, located on the bottom layer silicon, of each second shallow trench is larger than the width, located on the buried oxide layer, of each second shallow trench; the second shallow trench is filled with oxide to form a second shallow trench isolation structure, and the thickness of the second shallow trench isolation structure is larger than that of the first shallow trench isolation structure; gate structures of the MOS transistor are formed on the surface of the top layer silicon of the switch region and the control region, a source end and a drain end of the MOS transistor are formed in the top layer silicon on the two sides of each gate structure respectively, and the second shallow trench isolation structure is partially located below the source end and the drain end of the switch region.