430 results about "Shallow trench isolation" patented technology

The invention discloses a method for forming a shallow trench isolation structure, and belongs to the technical field of semiconductors, the method for forming the shallow trench isolation structure comprises the steps of forming a first stop layer on a substrate, etching the first stop layer and a part of the substrate, and forming a trench; an insulating material is deposited in the groove and on the first stop layer, a second stop layer and a sacrificial layer are sequentially deposited on the insulating material, and the insulating material, the second stop layer and the sacrificial layer are provided with recesses in the groove; the sacrificial layer is ground and thinned until the second stop layer is exposed, and part of the sacrificial layer is reserved at the concave position of the second stop layer; and synchronously etching the second stop layer and the sacrificial layer until the second stop layer is completely removed. A stop layer and a sacrificial layer are deposited on an unground insulating material, the height difference of a wafer surface film layer is preliminarily compensated by using a grinding process, and then the residual film layer is synchronously consumed by using an etching process, so that the height difference of the insulating material is reduced, and the difficulty of a CMP (Chemical Mechanical Polishing) process is reduced.

The invention provides a manufacturing method of a shallow trench isolation structure. The manufacturing method comprises the following steps: patterning a pad oxide layer-silicon nitride layer laminated structure based on a photomask to obtain a first mask opening; etching the substrate to obtain an isolation groove; carrying out a pull-back process; depositing a sacrificial layer material in the isolation trench and the first mask opening; forming a shielding layer; patterning the shielding layer based on the photomask to obtain a second mask opening; removing the sacrificial layer material in the isolation groove and obtaining a sacrificial side wall located on the side wall of the opening of the silicon nitride layer; removing the shielding layer and depositing a silicon oxide layer in the isolation groove and the first mask opening; and removing the silicon nitride layer, the liner oxide layer and the sacrificial side wall. According to the method, the first mask opening and the second mask opening are formed in different steps based on the same photomask by adopting the pull-back process, the sacrificial side wall on the side wall of the opening of the silicon nitride layer is used for protecting the trench oxide layer from being lost in the subsequent removal process of the liner oxide layer, and the problem of a sunken region at the top edge of the shallow trench isolation region can be avoided or improved.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

The invention belongs to the technical field of visible light detection, and aims to realize accurate detection of multicolor visible light and monolithic integration of a multi-wavelength receiver. The invention provides a fully-integrated multicolor visible light detector based on a sub-wavelength polycrystalline silicon grating, which comprises three detectors capable of selectively detecting blue, green and red signals respectively. The principle is as follows: a one-dimensional sub-wavelength polycrystalline silicon grating in the multicolor detector is embedded in an upper SiO2 layer and a lower shallow trench isolation region to form a dielectric waveguide structure of which the middle is a high-refractive-index medium and the periphery is a low-refractive-index oxide layer. The period and the grating width of the sub-wavelength grating are changed, so that the incident polarized light and the sub-wavelength periodic structure are strongly coupled to cause a guided-mode resonance effect, and the sub-wavelength grating can be applied to a transmission optical filter. The size and the cost of the multicolor visible light communication system can be effectively reduced, and the data transmission rate of the system is greatly improved.

The invention discloses a shallow trench isolation structure and a preparation method thereof, and belongs to the technical field of semiconductors, and the preparation method comprises the steps: providing a semiconductor substrate, and sequentially forming a liner oxide layer and a nitride layer on the semiconductor substrate; forming grooves in the liner oxide layer, the nitride layer and the semiconductor substrate; the grooves extend into the semiconductor substrate from the nitride layer and divide the semiconductor substrate into a plurality of active regions; performing back etching on the pad oxide layer and the nitride layer on the two sides of the groove so as to expose the top surface of the active region of the semiconductor substrate close to the top of the side wall of the groove; forming an epitaxial layer on the inner wall of the groove and the exposed top surface of the active region of the semiconductor substrate; smoothing the top corner of the exposed active region of the semiconductor substrate to form a line oxide layer; and forming an isolation region in the groove, performing planarization processing on the isolation region to expose the nitride layer, and removing the nitride layer.

Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.

A semiconductor device includes a backside contact, a shallow trench isolation (STI), and a backside dielectric trench isolation (BDTI) below the STI. A top surface of the BDTI is connected to the STI on a backside of a high voltage region of the semiconductor device, a bottom surface of the BDTI is connected to a backside power interconnect, and the BDTI isolates a backside contact from a substrate.

Embodiments of the invention include a semiconductor structure having first stacked transistors including a first upper transistor over a first lower transistor. Second stacked transistors are adjacent to the first stacked transistors. A gate structure includes a gate extension into a shallow trench isolation region, where a non-conductive frontside gate cut through the gate structure isolates the first stacked transistors and the second stacked transistors, where a contact through the non-conductive frontside gate cut contacts the gate extension and is coupled to the first lower transistor.

A semiconductor device includes a logic device including a first portion of a first substrate extending vertically below a first source / drain region, a second portion of the first substrate extending vertically below a second source / drain region, a first shallow trench isolation (STI) extending vertically and isolating the first portion of the first substrate and the second portion of the first substrate, a backside power delivery network (BSPDN) below the logic device, a first dielectric layer extending vertically through sidewalls of a backside contact. The first dielectric layer isolates the backside contact from the first portion of the first substrate and the second portion of the first substrate.

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

This invention provides a method for fabricating a dummy gate process in a semiconductor chip, comprising: providing a substrate in which a plurality of shallow trench isolation structures are formed; forming an ONO layer on the surface of the substrate with the shallow trench isolation structures; forming photoresist at the position of the dummy gate pattern corresponding to the shallow trench isolation structure; wet etching to remove the top silicon oxide layer in the ONO layer not covering the photoresist; after removing the photoresist, wet etching to remove the silicon nitride layer and silicon oxide layer in the ONO layer; forming a gate oxide layer; forming a dummy gate pattern on the surface of the substrate with the gate oxide layer; forming a sidewall layer on the surface of the dummy gate pattern; etching the substrate on both sides of the dummy gate pattern and forming source / drain regions using epitaxy; filling the source / drain regions with an intermediate dielectric layer, and then removing the dummy gate pattern. This invention avoids device failure caused by device short circuits, thereby improving device reliability.

Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

The application discloses a vertical parasitic NPN triode device and a manufacturing method thereof, and the vertical parasitic NPN triode device comprises the following steps: an N-type deep well is arranged on a P-type substrate, the N-type deep well is formed into a segmented structure on both sides of the P-type substrate at a corresponding position of an emission area, both ends of the segmented N-type deep well are connected to each other, and the N-type deep well serves as a collector area; a shallow trench isolation is arranged on an N well and a P well, the N well is arranged in the N-type deep well; the P well is arranged on an inner side of the segmented N-type deep well between the N wells, and serves as a base area; an N-type heavily doped area is arranged on a surface of the P well, and serves as the emission area; and a P-type heavily doped area is arranged on the surface of the P well, is arranged on both sides of the N-type heavily doped area, and is electrically connected to the P well to serve as a base area lead-out end. The application can overcome the defect that the low Early voltage of the existing vertical parasitic NPN triode is caused by the low net doping concentration of the base area, and meanwhile, the adverse effects caused by directly increasing the P well concentration of the base area on other devices of a process platform can be avoided.

The invention belongs to the technical field of semiconductor manufacturing, and discloses a method for manufacturing double shallow trench isolation and a semiconductor structure. The method comprises the following steps: sequentially depositing a substrate oxide layer, a substrate silicon nitride layer, a sacrificial layer, a bottom anti-reflection coating and photoresist on a selected semiconductor substrate, and forming a patterned sacrificial layer through a photoetching process; sequentially depositing a grinding barrier layer with a preset thickness and a first dielectric layer on the patterned sacrificial layer, processing the first dielectric layer through a chemical mechanical grinding process, removing the grinding barrier layer through an etching process, and sequentially forming a channel of a logic region and a channel of a pixel region; and depositing a second dielectric layer and carrying out chemical mechanical grinding to finally obtain the double-shallow-trench isolation structure. According to the technical scheme, the technical problems that in the prior art, silicon nitride residues are generated, and the heights of silicon oxide in the logic area and the pixel area are different are solved.

Semiconductor devices are provided that include a conductor structure located in a shallow trench isolation structure that is positioned between two field effect transistors of a same conductivity type. The conductor structure is electrically connected to a backside contact structure, and the backside contact structure is electrically connected to at least one well region that straddles a sidewall of the backside contact structure. The area of contact between the backside contact structure and the well region provides a local well tap to the semiconductor device.

The application provides a preparation method of a semiconductor structure, and belongs to the field of semiconductors. The method comprises the following steps: sequentially forming a doped layer, a pad oxide layer and a pad nitride layer on a substrate; etching the pad nitride layer, the pad oxide layer, the doped layer and part of the substrate to form a shallow trench, then depositing an insulating material in the shallow trench until the insulating material in the shallow trench protrudes from the pad nitride layer; first planarizing the insulating material until the pad nitride layer is exposed; sequentially etching and removing the pad nitride layer and the pad oxide layer until the doped layer is exposed; depositing a compensating insulating material on the doped layer and the insulating material in the shallow trench; second planarizing the compensating insulating material and the insulating material until the doped layer is exposed to form a shallow trench isolation structure; and removing the doped layer. The preparation method of the semiconductor structure can improve the corner recess phenomenon of the shallow trench isolation structure.

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a source region and a drain region having a first conductivity type disposed in a semiconductor layer having an opposite second conductivity type, a shallow trench isolation structure disposed in the semiconductor layer between the source region and the drain region, a gate dielectric layer disposed over the semiconductor layer and extending between the source region and the shallow trench isolation structure, a gate electrode disposed over the gate dielectric layer and extending toward the drain region and over the shallow trench isolation structure, and a field plate spacer between the gate electrode and the shallow trench isolation structure.

The present application provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device adds a selective deposition process after removing the liner oxide layer by a first wet etching process in the manufacturing process of the shallow trench isolation structure, thereby forming a dielectric repair layer on the exposed surface of the formed shallow trench isolation structure by the selective deposition process, and the dielectric repair layer fills the side trench of the top edge of the shallow trench isolation structure, thereby solving the problem of weakening the isolation effect of the shallow trench isolation structure caused by the side trench formed at the top edge of the shallow trench isolation structure, and improving the electrical performance of the device. The semiconductor device of the present application can ensure the required isolation effect of the shallow trench isolation structure because the dielectric repair layer is filled in the side trench of the top edge of the shallow trench isolation structure by the selective deposition process, thereby improving the electrical performance and reliability of the device.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a contact structure. The substrate includes a shallow trench isolation (STI) structure and active structures separated by the STI structure. The contact structure includes a first contact structure and a second contact structure that are laminated, where the first contact structure covers a part of a top surface and a part of a side wall of the active structure.

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.

The application relates to a shallow trench isolation structure and a preparation method thereof and a semiconductor structure. The preparation method comprises the following steps: providing a substrate, sequentially stacking a pad oxide layer and a hard mask layer on the surface of the substrate; etching the pad oxide layer and the substrate with the patterned hard mask layer as a mask to form an opening in the pad oxide layer and a trench in the substrate; forming a substrate oxide layer in the trench; forming a first barrier layer covering the hard mask layer and the substrate oxide layer; forming a first oxide layer covering the first barrier layer; removing the first barrier layer and the first oxide layer on the upper surface of the hard mask layer; and removing the pad oxide layer and the hard mask layer on the upper surface of the substrate to form a second barrier layer. The application can improve the isolation performance of the shallow trench isolation structure, and improve the use reliability and yield of the semiconductor structure.

A method includes forming a shallow trench isolation region in a semiconductor substrate, forming a first protruding fin and a second protruding fin higher than, and on opposing sides of, the shallow trench isolation region, and forming a hard mask over the shallow trench isolation region. The hard mask includes a first portion closer to the first protruding fin and overlapping a first part of the shallow trench isolation region, and a second portion closer to the second protruding fin and overlapping a second part of the shallow trench isolation region. The method further includes patterning the hard mask to remove the second portion of the hard mask and leaving the first portion of the hard mask over the first part of the shallow trench isolation region, and forming a gate stack over the first portion of the hard mask.

The invention provides a ferroelectric memory and a forming method thereof, a capacitor structure in the ferroelectric memory is in a groove type and is arranged in a matrix, and the capacitor structure at least penetrates through an intermetallic dielectric layer and an interlayer dielectric layer and extends into a shallow groove isolation structure. The groove type capacitor structure is integrated at the rear section, the bottom end of the groove type capacitor structure at least extends into the shallow groove isolation structure, the depth and the surface area of the capacitor are increased through the groove type capacitor structure, a read-write window is further improved, and the groove type capacitor structure is not limited by the number of metal layers at the rear section. And one transistor and a plurality of capacitor structures are adopted, and a groove type capacitor structure matrix is formed above the shallow groove isolation structure, so that the capacitance density and the process uniformity can be improved.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

A laterally-diffused metal-oxide semiconductor (LDMOS) device may include a semiconductor layer having a trench therein, and a superlattice liner in the trench. The superlattice liner may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, and each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The LDMOS may further include a shallow trench isolation (STI) region within the trench, spaced-apart source and drain regions in the semiconductor layer on opposite sides of the trench, a gate on the semiconductor layer between the source and drain regions, and a drift region in the semiconductor layer surrounding the trench and separated from the STI region by the superlattice liner.

This invention provides a method for integrating low-voltage devices in a high-voltage process. The method includes: after forming gate dielectric layers for high-voltage and medium-voltage device regions, forming a front dielectric layer covering all regions; forming a mask layer covering the medium-voltage and low-voltage device regions, exposing the input / output and high-voltage device regions; removing the exposed front dielectric layer to form the gate dielectric layer for the input / output device regions; and finally forming a mask layer to expose the low-voltage device regions, removing the surface dielectric layer to form the gate dielectric layer for the low-voltage device regions. This invention protects the low-voltage device regions through a mask layer, avoiding damage and silicon loss caused by prolonged exposure of the silicon surface and repeated etching and resist removal, reducing defect introduction, improving the height difference between the active region and the shallow trench isolation structure, and enhancing the reliability of the low-voltage devices and the local uniformity of saturated leakage current.

An image sensor can include a semiconductor substrate of a first conductivity type; an isolation structure in the semiconductor substrate to define a plurality of pixel regions; a shallow trench isolation pattern in the semiconductor substrate to define an active portion in each of the plurality of pixel regions; a transfer gate electrode in each of the plurality of pixel regions between a photoelectric conversion region and a floating diffusion region; and a plurality of pixel transistors in the plurality of pixel regions, respectively. Each of the plurality of pixel transistors can include a pixel gate electrode on the active portion and a plurality of source / drain regions in the active portion at two sides of the pixel gate electrode. The transfer gate electrode on the plurality of pixel regions and the pixel gate electrodes of the plurality of pixel transistors can include dopants of the first conductivity type. The plurality of source / drain regions can include dopants of a second conductivity type.

A semiconductor device includes a passive device including a first backside contact on a first side of the passive device, a second backside contract on a second side of the passive device, a spacer liner over sidewalls of the first backside contact and the second backside contact, and a shallow trench isolation (STI) above the first backside contact and the second backside contact and partially covering a top surface of the first backside contact and the second backside contact. The spacer liner is configured to prevent carrier transportation from the passive device.

The present invention relates to a vertically-charge-transferring pixel sensor (VPS) and methods of manufacture and operation thereof. In the VPS, deep trench isolation (DTI) structures and shallow trench isolation (STI) structures in a substrate contain deep trench electrodes and shallow trench electrodes, respectively. In a light sensing operation, a positive bias voltage can be applied between the substrate and the deep and shallow trench electrodes to raise a potential barrier at boundaries of the DTI and STI structures and the substrate. This reduces the likelihood of photoelectrons being captured at the boundaries, thus reducing loss of photoelectrons and contributing to enhanced quantum efficiency. In addition, in the STI structures, the shallow trench electrodes may be offset toward light sensing regions beside the STI structures. In this way, a voltage applied to the shallow trench electrodes has a greater impact on potentials in the light sensing regions than on potentials in charge readout regions, thus additionally reducing loss of photoelectrons and minimizing the influence on MOS transistors in the charge readout regions.

Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the STI is doped with an n-type impurity, in regions of the STI adjacent to the source and / or drain regions, to provide dopant diffusion reduction. In some embodiments, the STI region is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the thickness of the doped STI region may range between 10 and 100 nanometers.