204 results about "Lattice mismatch" patented technology

The invention discloses a deep ultraviolet LED epitaxial structure, a deep ultraviolet LED device comprising the same and a preparation method, and the epitaxial structure sequentially comprises a sapphire substrate, an AlN nanowire array layer, an AlN intrinsic layer and an AlGaN light-emitting structure layer from bottom to top. The AlGaN light-emitting structure layer further comprises an n-type AlGaN electron injection layer, a quantum well active layer, a p-type AlGaN electron blocking layer and other device structures. According to the invention, the vertically arranged AlN nanowire array is introduced to replace a traditional AlN buffer layer, so that lattice mismatching stress caused by a substrate is significantly released, and the dislocation density of an epitaxial layer is effectively reduced; meanwhile, the introduction of the AlN intrinsic layer further flattens the epitaxial interface and optimizes the lattice quality, thereby providing a high-quality template for the growth of a high-performance AlGaN material. The epitaxial structure is suitable for an LED device in a deep ultraviolet band, and the crystal quality, the electrical property and the luminous efficiency of the device can be improved.

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial structure which comprises a substrate, and a graphene composite nano layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer are sequentially stacked on the substrate. The graphene composite nano layer comprises a modified graphene layer and a ZnO sub-layer which are stacked in sequence, the modified graphene layer is arranged on the substrate, and the ZnO sub-layer is arranged on the modified graphene layer; the modified graphene layer is subjected to nitrogen plasma treatment, and the thickness of the modified graphene layer is 10-100 nm; and the thickness of the ZnO sub layer is 20 nm to 200 nm. According to the invention, lattice mismatch dislocation, residual stress and thermal mismatch of the epitaxial material grown on the heterogeneous substrate can be effectively modulated, the scattering efficiency under high current is improved, the probability of radiation recombination of the heterogeneous epitaxial material is improved, and the requirement of heterogeneous epitaxy is relaxed at the same time.

The invention discloses a high-quality silicon carbide homoepitaxial wafer and a preparation method thereof, the epitaxial wafer comprises an epitaxial layer, a SiC substrate and a regulation and control layer, the regulation and control layer is located outside the back surface of the substrate or inside the back surface of the substrate, and the epitaxial layer is located on the front surface of the substrate; wherein the lattice mismatch degree between the regulation and control layer and the substrate has the same sign as the lattice mismatch degree between the epitaxial layer and the substrate, but the absolute value is larger; the preparation method comprises the following steps: preparing the regulation and control layer on the back surface of the SiC substrate; front deposition and surface scratch of the substrate caused by the previous step are eliminated through chemical mechanical polishing; growing an epitaxial layer on the front surface of the substrate through epitaxial deposition; and finally, chemically and mechanically polishing to eliminate micro pits and step coalescence morphology on the surface of the epitaxial layer to obtain the epitaxial wafer. The regulation and control layer is introduced to the back surface of the substrate, lattice mismatch between the epitaxial layer and the substrate is weakened through the regulation and control layer, dislocation proliferation and slippage are reduced, and the high-quality silicon carbide homoepitaxial wafer with low defect density and small deformation is prepared.

The invention provides a photoelectric detector and a preparation method thereof, which are applied to the technical field of semiconductors, and the photoelectric detector comprises a gallium oxide light absorption layer; the two-dimensional Van der Waals material layer is arranged on the gallium oxide light absorption layer and is combined with the gallium oxide light absorption layer through Van der Waals force to form a vertical heterojunction; the metal electrode is formed on the surfaces of the gallium oxide light absorption layer and the two-dimensional Van der Waals material layer; wherein the work function of the two-dimensional Van der Waals material layer is matched with the work function of the gallium oxide light absorption layer, so that staggered energy band arrangement is formed at the interface of the vertical heterojunction. According to the invention, interface defects caused by lattice mismatch can be avoided, and non-radiative recombination of photon-generated carriers can be reduced, so that the response speed and photoelectric conversion efficiency of the photoelectric detector can be greatly improved.

The application discloses a graphene-diamond composite coating and a preparation method and application thereof, and belongs to the technical field of materials. The graphene-diamond composite coating comprises a diamond coating and a graphene coating; graphene sp2 bond structure is covalently combined with diamond sp3 bond structure; and the graphene coating has a graphene structure with non-parallel growth mainly in a vertical direction. The graphene-diamond composite coating has small lattice mismatch between the diamond and the graphene, avoids volume expansion caused in a friction heat process, and has the advantages that the diamond coating can provide a support layer for the graphene, forms super-strong C-C covalent bonds at an interface, and significantly improves the adhesion strength of the graphene; the graphene can avoid brittle fracture of the diamond, and significantly improves the lubricating performance of the surface of the diamond coating. The composite coating has better wear resistance, a low friction coefficient and excellent oxidation resistance, and can remain stable under high-temperature and high-load working conditions, so that the service life and processing efficiency of wear-resistant parts are improved.

The invention discloses a silicon-based indium phosphide laser and a preparation method thereof, and relates to the technical field of semiconductor devices, the silicon-based indium phosphide laser comprises a silicon substrate, a composite insulating layer, a Van der Waals buffer layer and an indium phosphide epitaxial structure which are stacked in sequence; the indium phosphide epitaxial structure comprises a first epitaxial structure stacked on the Van der Waals buffer layer and a second epitaxial structure stacked on the first epitaxial structure; the first epitaxial structure at least comprises a lower cladding layer, a lower limiting layer, a lower waveguide layer, a spacing layer, a multi-quantum well active region, an upper limiting layer, an etching stop layer, an upper waveguide layer and an upper cladding layer which are sequentially stacked, a Bragg grating is manufactured in the upper waveguide layer, and the second epitaxial structure comprises a regrowth cladding layer and a contact layer which are sequentially stacked; the Van der Waals buffer layer is a two-dimensional material film, and the problems of lattice mismatch, thermal expansion coefficient mismatch and polarity structure difference of integration of the silicon substrate and the InP epitaxial layer are thoroughly solved from a physical mechanism by introducing the single-layer two-dimensional material Van der Waals buffer layer.

The invention is applicable to the technical field of LED (light-emitting diode) preparation, and provides a growth method of a green-light LED epitaxial structure, which comprises the following steps of: sequentially growing a nucleating layer, a U-shaped high-temperature GaN layer which is not doped, an N-shaped high-temperature GaN layer which is continuously doped with Si, a multi-quantum well light-emitting layer, a P-shaped AlGaN layer which is doped with Al and Mg and a high-temperature P-shaped GaN layer which is doped with Mg by adopting an MOCVD (metal organic chemical vapor deposition) process; the composite nucleating layer replaces a traditional single GaN nucleating layer, lattice mismatch and stress accumulation are reduced from the source, and the dislocation defect of the multi-quantum well layer is reduced; according to the invention, electric leakage of a green light LED device is effectively reduced, the luminous efficiency and the antistatic capability are improved, and the method is suitable for preparation of a high-brightness GaN-based green light LED epitaxial wafer.

This invention relates to the field of memory technology, specifically to a ferroelectric metal-controlled memristor and chip based on a single layer of gallium oxide and a single layer of blue phosphorus. The ferroelectric metal-controlled memristor includes a top electrode layer, a control layer, and a bottom electrode layer, which are sequentially contacted from top to bottom. It combines the unique ferroelectric properties of gallium oxide with the excellent electrical properties of blue phosphorus, a two-dimensional material. The control layer formed by these two materials interacts through van der Waals forces, and the polarization direction of the gallium oxide layer is switched by applying voltages in different directions to the heterojunction, enabling memristor writing and reading. This avoids the interface defects and lattice mismatch problems introduced by strong chemical bonds in traditional memristors, thus reducing the operating power consumption of the memristor while improving its read / write speed and stability.

This invention discloses an MSM interdigitated wideband ultraviolet photodetector and its fabrication method, belonging to the field of semiconductor technology. The detector includes: a substrate; an AlN nucleation layer on the substrate surface; a heterostructure on the surface of the AlN nucleation layer away from the substrate, wherein the heterostructure includes GaN, GaON, and Ga2O3 layers stacked sequentially from bottom to top; and interdigitated electrodes on the surface of the Ga2O3 layer away from the substrate. This invention introduces a GaON layer between the Ga2O3 and GaN heterojunctions. This GaON layer acts as a lattice buffer layer, effectively releasing the lattice mismatch stress between Ga2O3 and GaN, significantly improving the interface quality of the heterojunction, and enhancing the separation and collection efficiency of charge carriers, thus significantly improving the overall performance of the MSM interdigitated ultraviolet photodetector.

The application relates to a molecular beam epitaxy preparation method of epitaxial high-quality AlN on a Si substrate and an AlN epitaxial wafer, and the preparation method comprises the following steps: S1, obtaining a substrate, performing infrared lamp baking on the substrate, performing high-temperature deoxidization after heating pretreatment, and obtaining a pretreated substrate; S2, adopting a molecular beam epitaxy method to pre-deposit an Al layer on the pretreated substrate; S3, adopting the molecular beam epitaxy method to grow an AlN epitaxial layer on the pre-deposited Al layer; and S4, continuously introducing a nitrogen plasma post-treatment, and cooling to a wafer transfer temperature to obtain an epitaxial wafer. In the technical scheme, the pre-deposited Al layer can inhibit the reaction between the substrate and N in the AlN layer, the formation of amorphous particles is avoided, the AlN morphology is improved, meanwhile, the pre-deposited Al layer not only relieves the lattice mismatch problem between the substrate material and the AlN, but also improves the Al atom migration rate for the growth of the subsequent AlN layer, promotes two-dimensional growth, and thus the AlN crystal quality is improved.

The invention relates to AlGaN based on porous AlN growth and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: step 1, providing a sapphire-based AlN substrate; step 2, preparing an alkaline melt solution, completely immersing the substrate into the alkaline melt solution for corrosion, then taking out the substrate, cleaning and drying to obtain a sapphire-based AlN substrate intermediate; corrosion holes are formed in the surface of the AlN layer of the sapphire-based AlN substrate intermediate, and the hole diameter of the corrosion holes is 50-100 nm. 3, after water and oxygen removal treatment is carried out on the sapphire-based AlN substrate intermediate, an AlGaN layer is deposited; the thickness of the AlGaN layer is 1 to 1.5 [mu] m. According to the preparation method, lattice mismatch of AlN and AlGaN is relieved through the lateral epitaxial process in the AlGaN growth process, relaxation stress is achieved, the crystal quality is improved, the surface damage function is reduced, and growth of the thick-film AlGaN with the high quality and the good surface is achieved.

The application relates to the technical field of semiconductor material preparation, in particular to a liquid phase epitaxial growth method and equipment for dynamically regulating lattice mismatch. The specific content is as follows: a substrate is pretreated to prepare micro pits and grooves of the substrate, and a uniform solution is prepared according to phase diagram information; a temperature gradient is set in a multi-zone temperature control epitaxial furnace, and the epitaxial growth of the substrate is controlled through a boat device; the substrate and the solution pool are sequentially moved into the furnace; during the epitaxial growth process, the lattice constant error, morphology and photoelectric properties of the growth are detected, and when the detection signal deviates from the predetermined threshold, the lattice mismatch is compensated by adjusting the solution concentration and the temperature; during the displacement process, the mother liquor remaining between different layers is poured into the grooves of the substrate through the inclined substrate. The application solves the problem of lattice mismatch control by real-time detection and real-time regulation of the lattice mismatch, and improves the quality and performance of the epitaxial layer.

Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer / second doped layer, but also can improve surface roughness of the first doped layer / second doped layer.

The invention provides a semiconductor power device and a forming method thereof, the semiconductor power device comprises a substrate and a nucleating layer, a buffer layer and a dislocation regulation and control layer which are sequentially formed on the substrate, the dislocation regulation and control layer comprises a first high-resistance layer, a patterned lattice mismatch layer and a second high-resistance layer, the first high-resistance layer is formed on the buffer layer, and the second high-resistance layer is formed on the patterned lattice mismatch layer. The patterned lattice mismatch layer is formed on the first high-resistance layer and exposes a part of the first high-resistance layer, the second high-resistance layer covers the exposed first high-resistance layer and extends to cover the patterned lattice mismatch layer, and the second high-resistance layer has blade type dislocation. Due to the existence of the blade type dislocation, continuously distributed hole traps can be induced around the blade type dislocation and are coupled with the original traps in the buffer layer, a channel for hole transmission can be formed, hole redistribution is realized through the channel, electron accumulation in the buffer layer can be effectively relieved, and the dynamic performance degradation of the device can be inhibited.

The invention discloses a manufacturing method of a semiconductor epitaxial layer, which comprises the following steps that doping is carried out in a semiconductor substrate to form a well region, and a first defect on the top surface of the semiconductor substrate comprises a lattice mismatch defect caused by impurities of the well region; and executing more than one cycle step to form the transition layer, wherein the cycle step comprises the step of performing a first interface repair process to repair the exposed defect on the surface of the front layer. And performing first epitaxial growth to form a non-doped first epitaxial sub-layer on the surface of the front layer. And forming a main body layer of the semiconductor epitaxial layer, wherein a second interface repairing process is performed to repair the defect exposed on the surface of the transition layer. And performing second epitaxial growth to form the non-doped main body layer on the surface of the transition layer. The rate of the first epitaxial growth is smaller than that of the second epitaxial growth, and the thickness of the main body layer is larger than that of each first epitaxial sub-layer. According to the invention, defects, especially pit defects, formed on the surface of the semiconductor epitaxial layer due to the influence of doped impurities on the surface of the semiconductor substrate can be improved.

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, and relates to the technical field of semiconductors. The first doping type well region is formed in the substrate along the first side of the substrate, the stress region and the second doping type source region are formed in the first doping type well region, and the second doping type drain region is formed in the stress region; the gate structure is formed on the substrate along the first side of the substrate; wherein the stress region is formed by growing a material which is in lattice mismatch with the substrate material, and along the thickness direction of the substrate, the gate structure covers a part of the stress region and a part of the top of the first doping type well region, and is connected with the second doping type drain region and the second doping type source region. According to the technical scheme, the electron mobility can be improved, and then the current capacity of the nLDMOS is improved.

The invention discloses a gallium nitride / molybdenum disulfide heterojunction photoelectric detector and a preparation method, and belongs to the field of photoelectric detectors, and the photoelectric detector comprises a gallium nitride layer with a first conduction type; the passivation layer covers the surface of the gallium nitride layer and is provided with an open pore area exposing the gallium nitride layer; the molybdenum disulfide thin film is transferred to the surface of the passivation layer, and at least part of the molybdenum disulfide thin film is in direct contact with the gallium nitride layer through the opening area to form a heterojunction; and the first electrode and the second electrode are electrically connected with the gallium nitride layer and the molybdenum disulfide film respectively. The heterojunction is formed by combining the two-dimensional material and the three-dimensional material, so that the performance of the device can be effectively improved; meanwhile, the molybdenum disulfide thin film is directly transferred to the surface of the passivation layer and is in direct contact with the gallium nitride layer through the opening area, chemical bond connection does not exist between the molybdenum disulfide thin film and the gallium nitride layer, and the molybdenum disulfide thin film and the gallium nitride layer are combined through Van der Waals force, so that the problem of lattice mismatch between the molybdenum disulfide thin film and the gallium nitride layer can be effectively solved; and the performance of the device can be improved.

The embodiment of the application provides a reflector and an optical device, which comprises a first electrode, a diamond substrate layer, a first graphene layer, a buffer heat conduction layer, an active region and a second electrode which are sequentially stacked from bottom to top. The diamond substrate layer is provided with a groove, and the first graphene layer extends into the groove to form a heat conduction path of the active region to the diamond substrate layer. The heat conduction path is formed by the diamond substrate layer and the first graphene layer extending into the groove, high-efficiency heat conduction is realized in combination with the buffer heat conduction layer, the lattice mismatch between the diamond and the semiconductor material is relieved by using the graphene, and the advantages of significantly reducing the interface thermal resistance, improving the heat dissipation efficiency of the device and the working stability are achieved.

A light-emitting element having high emission output power and light emission efficiency and a method of manufacturing of the same are provided. A light-emitting element according to the present disclosure includes an n-type semiconductor layer; an InAsSbP active layer containing at least In and As on the n-type semiconductor layer; a p-type semiconductor layer that is lattice-matched with the InAsSbP active layer, on the InAsSbP active layer; and a p-type InGaAs window layer that is lattice-mismatched with the p-type semiconductor layer, on the p-type semiconductor layer, wherein the p-type semiconductor layer has a thickness of 20 nm or more and 520 nm or less.

This invention provides a SiC epitaxial structure with two-dimensional electron gas and two-dimensional hole gas, and its fabrication method. The SiC epitaxial structure includes, sequentially arranged, a Si-faced 3C-SiC barrier layer, a 2DHG, a Si-faced 4H-SiC channel layer, a Si-faced N-type 4H-SiC drift layer, a Si-faced N-type 4H-SiC buffer layer, a Si-faced conductive substrate, a C-faced N-type 4H-SiC buffer layer, a C-faced N-type 4H-SiC drift layer, a C-faced 4H-SiC channel layer, a 2DEG, and a C-faced 3C-SiC barrier layer. In this invention, the lattice mismatch between 3C-SiC and 4H-SiC in the (0001) plane is less than 0.1%, solving the problems of lattice mismatch and thermal mismatch, resulting in better device stability and reliability.

A magnetic recording medium is described that includes a substrate and an amorphous soft underlayer (SUL). An Ni—Pt seed layer is formed on the SUL where the Pt atoms have substitutionally replaced at least some of the Ni atoms within an Ni lattice structure of the Ni—Pt to form a solid solution of Ni—Pt. In some examples, the Ni—Pt seed layer is formed of Ni40Pt60. An Ru interlayer is formed on the seed layer. In some examples, the Ni—Pt seed layer has a lattice mismatch with the Ru interlayer of 0.4% or less. A magnetic recording layer is formed on the Ru interlayer. Additional layers or films may be provided. The medium may be configured for use with perpendicular magnetic recording (PMR). A data storage device that includes the magnetic recording medium is described. Methods for fabricating the magnetic recording medium are set forth herein as well.

The application discloses a gallium nitride / molybdenum disulfide heterojunction photodetector and a preparation method thereof, and belongs to the photodetector field. The photodetector comprises a gallium nitride layer with a first conductive type; a passivation layer covering the surface of the gallium nitride layer and having an opening area exposing the gallium nitride layer; a molybdenum disulfide film transferred to the surface of the passivation layer and directly contacting the gallium nitride layer through the opening area to form a heterojunction; and a first electrode and a second electrode electrically connected with the gallium nitride layer and the molybdenum disulfide film, respectively. The application combines two-dimensional materials and three-dimensional materials to form a heterojunction, which can effectively improve the device performance. Meanwhile, the molybdenum disulfide film is directly transferred to the surface of the passivation layer and directly contacts the gallium nitride layer through the opening area, and there is no chemical bond between the molybdenum disulfide film and the gallium nitride layer, but they are combined through van der Waals force, so that the lattice mismatch problem between the molybdenum disulfide film and the gallium nitride layer can be effectively solved, and the device performance can be improved.

A magnetic recording medium is described that includes a substrate and an amorphous soft underlayer (SUL). A Ni-Pt seed layer is formed on the SUL in which Pt atoms have substituted at least some of the Ni atoms within the Ni lattice structure of Ni-Pt to form a solid solution of Ni-Pt. In some examples, the Ni-Pt seed layer is formed from Ni40Pt60. A Ru intermediate layer is formed on the seed layer. In some examples, the lattice mismatch of the Ni-Pt seed layer and the Ru intermediate layer is 0.4% or less. A magnetic recording layer is formed on the Ru intermediate layer. Additional layers or films may be provided. The media may be configured for use with perpendicular magnetic recording (PMR). A data storage device is described that includes the magnetic recording medium. Methods for manufacturing the magnetic recording media are also described herein.

The application discloses a 4-inch heteroepitaxial diamond wafer and relates to the technical field of semiconductor substrate materials, characterized in that: from bottom to top, the 4-inch heteroepitaxial diamond wafer comprises a hetero-substrate layer, a composite buffer layer and a diamond epitaxial layer in sequence, the composite buffer layer is arranged between the hetero-substrate layer and the diamond epitaxial layer, and the composite buffer layer comprises a YSZ layer and a graphene layer. At present, the 4-inch diamond wafer is mainly prepared through a homoepitaxy method, but natural large-size diamond seeds are scarce and high in cost, and problems of too high dislocation density and excessive surface roughness are prone to occurring in the growth process. The composite buffer layer comprising the YSZ layer and the graphene layer arranged between the hetero-substrate layer and the diamond epitaxial layer can effectively relieve interface stress generated at a hetero-interface due to lattice mismatch and thermal expansion difference, reduce generation of dislocations, cracks and other defects in the epitaxial growth process, and improve the crystallization quality, structural stability and growth uniformity of the diamond epitaxial layer.

The invention relates to a method for processing optoelectronic devices comprising a plurality of semiconductor materials characterized by mismatched lattice parameters, wherein a light emitting layer is patterned to form stripes, the stripes causing relaxation of strain within the semiconductor layers caused by the lattice mismatch, thereby increasing quantum efficiency. The patterning is additionally used to achieve a significantly higher density of defects on the sidewalls of the semiconductor stripes, allowing for higher modulation speeds through increased non-radiative recombination effects.

A method for preparing a strain channel FinFET, which method belongs to the technical field of integrated circuit manufacturing. After the manufacturing of a fin line is completed, amorphous silicon is generated by means of an amorphization implantation method; after being covered by a strain dielectric layer and annealed at a high temperature, the amorphous silicon is recrystallized, and in this case, tensile stress / compressive stress required by an N / PMOS can be formed between the crystalline silicon and a strain dielectric; and a strain dielectric material is then selectively removed to implement the preparation of a strain channel FinFET. In the method, the lattice mismatch between the strain dielectric material and the crystalline silicon is used to generate tensile stress or compressive stress required by a FinFET device. A single strain material is used to realize N / PMOS channel strain, so that the flow of channel stress engineering is simplified, the process complexity is reduced, and the method has the potential to be applied to technology nodes of 14 nm and above.

This invention relates to the field of optoelectronic device technology, and in particular to a laser based on a top-surface metal layer and a planar metal grating, and its fabrication method. The laser comprises a gain chip, an optical waveguide, a planar metal grating, a capping layer, and a metal layer. The planar metal grating fabricated using an electronic evaporation deposition process replaces the traditional complex three-dimensional etching, significantly improving the controllable precision and flatness of the grating structure. It eliminates the InP secondary epitaxial process, simplifying the overall process flow, reducing production costs, and simultaneously improving product performance consistency and yield. It also significantly improves reflection filtering efficiency, ensures the purity of the Bragg reflection spectrum, and helps achieve narrow linewidth performance in lasers. The capping layer above the planar metal grating effectively solves the problem of lattice mismatch in semiconductor secondary epitaxy, and can also confine diffracted light, reducing light energy leakage. The external cavity structure design increases the degree of freedom.

A nanoparticle (1) is specified. The nanoparticle (1) comprises a core (2) comprising a first semiconductor material, an emission shell (3) comprising a second semiconductor material, and an outer shell (4) comprising a third semiconductor material, wherein the emission shell (3) is arranged between the core (2) and the outer shell (4), and a lattice mismatch between the first semiconductor material and the second semiconductor material is at least 3%. Furthermore, a method for producing a nanoparticle and a light-emitting device, in particular comprising a micro-LED, are specified.

This invention relates to a lateral homo-heterojunction memory device and its fabrication method. The memory device includes a substrate gate layer, a first dielectric layer, a second dielectric layer, a two-dimensional semiconductor channel layer, and ohmic electrodes. The first and second dielectric layers are both located on the substrate gate layer and are in contact with each other. The two-dimensional semiconductor channel layer is located on the first and second dielectric layers. The ohmic electrodes are located at both ends of the two-dimensional semiconductor channel layer. This memory device uses a composite dielectric layer to perform dielectric modulation and electrostatic gate modulation on the two-dimensional semiconductor channel layer, thereby forming a lateral heterojunction in a homogeneous material. The cross-section of the formed lateral heterojunction is located at the junction of the first and second dielectric layers, and the interface of the formed lateral heterojunction consists of only one line, reducing defects at the interface. Furthermore, since the heterojunction is formed using the same material, there is no lattice mismatch problem between different materials, thus improving the electrical performance of the memory.

The invention belongs to the technical field of semiconductor photoelectronic device manufacturing, and particularly relates to an epitaxial structure for improving LED luminous efficiency and a preparation method thereof, an epitaxial junction sequentially comprises a substrate, a buffer layer, a UGaN layer, an NGaN layer, a multi-quantum well active layer and an electron blocking layer from bottom to top, and in M Loop cycles of the multi-quantum well active layer, M is an integer greater than or equal to 1, and M is an integer greater than or equal to 2. N Loop quantum barrier layers closest to the electron barrier layer are selected to be doped with Zn sources. By doping Zn, holes can be introduced into a valence band of a GaN quantum barrier, so that the potential barrier of the holes injected into a quantum well from a p region is effectively reduced, and the recombination efficiency of the holes and carriers is improved. The introduction of Zn atoms can partially compensate the stress generated by lattice mismatch of the InGaN / GaN interface. According to the method, only a Zn flow control system needs to be added during growth of the quantum barrier in the existing mature MOCVD process, the overall structure does not need to be changed or complex parameters such as temperature do not need to be greatly adjusted, and industrial application is easy.