318 results about "Lattice mismatch" patented technology

The invention discloses a high-strength and high-toughness aluminum nitride ceramic and a preparation method thereof, and relates to the technical field of ceramics, a sol-gel method is adopted to coat the surface of aluminum nitride with a stable shell layer to form a core-shell structure, meanwhile, the low lattice mismatch rate of a core-shell interface is utilized to reduce thermal resistance, and toughness and thermal conductivity are both considered; according to the external magnetic field tape casting method, the magnetic dipole moment orientation principle is utilized, an external magnetic field is applied in the tape casting stage, the in-plane mechanical property is improved, and the fracture toughness is improved through the magnetism of aluminum nitride whiskers; a reinforcement is introduced to improve the mechanical property and corrosion resistance of the aluminum nitride ceramic material, multi-granularity powder is compounded, large-particle aluminum nitride powder is used as a sintering and heat-conducting framework material, and high activity provided by submicron particles is utilized to promote sintering, so that the sintering temperature of aluminum nitride can be remarkably reduced, and the performance is greatly improved; and the aluminum nitride substrate expands more application fields on a future packaging circuit.

The invention discloses a deep ultraviolet LED epitaxial structure, a deep ultraviolet LED device comprising the same and a preparation method, and the epitaxial structure sequentially comprises a sapphire substrate, an AlN nanowire array layer, an AlN intrinsic layer and an AlGaN light-emitting structure layer from bottom to top. The AlGaN light-emitting structure layer further comprises an n-type AlGaN electron injection layer, a quantum well active layer, a p-type AlGaN electron blocking layer and other device structures. According to the invention, the vertically arranged AlN nanowire array is introduced to replace a traditional AlN buffer layer, so that lattice mismatching stress caused by a substrate is significantly released, and the dislocation density of an epitaxial layer is effectively reduced; meanwhile, the introduction of the AlN intrinsic layer further flattens the epitaxial interface and optimizes the lattice quality, thereby providing a high-quality template for the growth of a high-performance AlGaN material. The epitaxial structure is suitable for an LED device in a deep ultraviolet band, and the crystal quality, the electrical property and the luminous efficiency of the device can be improved.

The present invention discloses a preparation method and application of a MOF-on-MOF heterojunction metal-organic framework material rich in oxygen defects, belonging to the technical field of electrocatalytic oxygen evolution reaction. The present invention first grows Ni NDC nanosheets in situ on a carrier by a solvothermal method, and then grows Fe BDC nanosheets on the surface of the Ni NDC nanosheets by a solvothermal method to form Ni NDC@Fe BDC ultra-thin nanosheets. This method can synthesize a MOF-on-MOF type metal-organic framework under the premise of lattice mismatch. The synthesized Ni NDC@Fe BDC combines the advantages of multi-component material hybridization, ultra-thin nanosheets and defect induction, which can increase the number of active sites and promote the rapid transfer / redistribution of electrons in the catalytic process. The MOF-on-MOF heterojunction metal-organic framework has good electrocatalytic performance and excellent total water decomposition performance in alkaline oxygen evolution reaction.

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial structure and a preparation method thereof. The light-emitting diode epitaxial structure comprises a substrate, an h-BN / O2 layer, a low-temperature GaN buffer layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer which are arranged in sequence, the h-BN / O2 layer subjected to oxygen plasma treatment is inserted between the heterogeneous substrate and the GaN epitaxial layer, the low-temperature GaN buffer layer is grown on the h-BN / O2 layer by controlling the process conditions, and the h-BN / O2 layer and the low-temperature GaN buffer layer are matched, so that lattice mismatch dislocation, residual stress and thermal mismatch of an epitaxial material grown on the heterogeneous substrate can be effectively modulated, the scattering efficiency under high current is improved, and the light emitting efficiency is improved. The probability of radiation recombination of the heteroepitaxial material is improved, and the requirement for heteroepitaxy is lowered.

The invention relates to an electrochemical induced metal oriented growth method based on a gallium-based liquid metal substrate, and belongs to the technical field of electrochemical materials. According to the present invention, the dynamic smooth interface and the low lattice mismatch characteristic of the liquid metal are utilized, the reduction kinetics of the metal ions is regulated and controlled through the constant current mode, the high orientation degree growth of the crystal along the specific crystal face (such as Zn (002) and In (111)) is achieved, and the prepared deposited metal dominant crystal face has the high orientation degree. The problems of stress accumulation and dendritic crystals of a traditional solid substrate can be solved, and the method is suitable for green preparation of nanowire arrays and functional coatings; and the process is simple and convenient to operate, easy in control of process parameters and suitable for batch production.

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial structure which comprises a substrate, and a graphene composite nano layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer are sequentially stacked on the substrate. The graphene composite nano layer comprises a modified graphene layer and a ZnO sub-layer which are stacked in sequence, the modified graphene layer is arranged on the substrate, and the ZnO sub-layer is arranged on the modified graphene layer; the modified graphene layer is subjected to nitrogen plasma treatment, and the thickness of the modified graphene layer is 10-100 nm; and the thickness of the ZnO sub layer is 20 nm to 200 nm. According to the invention, lattice mismatch dislocation, residual stress and thermal mismatch of the epitaxial material grown on the heterogeneous substrate can be effectively modulated, the scattering efficiency under high current is improved, the probability of radiation recombination of the heterogeneous epitaxial material is improved, and the requirement of heterogeneous epitaxy is relaxed at the same time.

The invention discloses a high-quality silicon carbide homoepitaxial wafer and a preparation method thereof, the epitaxial wafer comprises an epitaxial layer, a SiC substrate and a regulation and control layer, the regulation and control layer is located outside the back surface of the substrate or inside the back surface of the substrate, and the epitaxial layer is located on the front surface of the substrate; wherein the lattice mismatch degree between the regulation and control layer and the substrate has the same sign as the lattice mismatch degree between the epitaxial layer and the substrate, but the absolute value is larger; the preparation method comprises the following steps: preparing the regulation and control layer on the back surface of the SiC substrate; front deposition and surface scratch of the substrate caused by the previous step are eliminated through chemical mechanical polishing; growing an epitaxial layer on the front surface of the substrate through epitaxial deposition; and finally, chemically and mechanically polishing to eliminate micro pits and step coalescence morphology on the surface of the epitaxial layer to obtain the epitaxial wafer. The regulation and control layer is introduced to the back surface of the substrate, lattice mismatch between the epitaxial layer and the substrate is weakened through the regulation and control layer, dislocation proliferation and slippage are reduced, and the high-quality silicon carbide homoepitaxial wafer with low defect density and small deformation is prepared.

The invention provides a photoelectric detector and a preparation method thereof, which are applied to the technical field of semiconductors, and the photoelectric detector comprises a gallium oxide light absorption layer; the two-dimensional Van der Waals material layer is arranged on the gallium oxide light absorption layer and is combined with the gallium oxide light absorption layer through Van der Waals force to form a vertical heterojunction; the metal electrode is formed on the surfaces of the gallium oxide light absorption layer and the two-dimensional Van der Waals material layer; wherein the work function of the two-dimensional Van der Waals material layer is matched with the work function of the gallium oxide light absorption layer, so that staggered energy band arrangement is formed at the interface of the vertical heterojunction. According to the invention, interface defects caused by lattice mismatch can be avoided, and non-radiative recombination of photon-generated carriers can be reduced, so that the response speed and photoelectric conversion efficiency of the photoelectric detector can be greatly improved.

The epitaxial structure comprises a substrate layer, a polymerization layer, a high-resistance layer, a middle layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, the polymerization layer comprises a combination of a buffer layer and a transition layer, the channel layer is provided with a two-dimensional electron conducting channel, and the high-resistance layer is arranged between the high-resistance layer and the middle layer. The material composition of the barrier layer is ALInGaN, and the channel layer is formed at the interface of the barrier layer and the intermediate layer. According to the epitaxial structure disclosed in the technical scheme, AlInGaN is adopted as a barrier layer material to replace a traditional AlGaN barrier layer, the lattice constant of the barrier layer can be adjusted by introducing the In element, lattice mismatch between the barrier layer and a GaN channel layer is reduced, and meanwhile high polarization intensity is kept, so that the two-dimensional electron gas concentration is improved, and meanwhile the performance of the epitaxial structure is improved. The interface defects are reduced, and the electron mobility is improved.

The application discloses a graphene-diamond composite coating and a preparation method and application thereof, and belongs to the technical field of materials. The graphene-diamond composite coating comprises a diamond coating and a graphene coating; graphene sp2 bond structure is covalently combined with diamond sp3 bond structure; and the graphene coating has a graphene structure with non-parallel growth mainly in a vertical direction. The graphene-diamond composite coating has small lattice mismatch between the diamond and the graphene, avoids volume expansion caused in a friction heat process, and has the advantages that the diamond coating can provide a support layer for the graphene, forms super-strong C-C covalent bonds at an interface, and significantly improves the adhesion strength of the graphene; the graphene can avoid brittle fracture of the diamond, and significantly improves the lubricating performance of the surface of the diamond coating. The composite coating has better wear resistance, a low friction coefficient and excellent oxidation resistance, and can remain stable under high-temperature and high-load working conditions, so that the service life and processing efficiency of wear-resistant parts are improved.

The invention discloses a silicon-based indium phosphide laser and a preparation method thereof, and relates to the technical field of semiconductor devices, the silicon-based indium phosphide laser comprises a silicon substrate, a composite insulating layer, a Van der Waals buffer layer and an indium phosphide epitaxial structure which are stacked in sequence; the indium phosphide epitaxial structure comprises a first epitaxial structure stacked on the Van der Waals buffer layer and a second epitaxial structure stacked on the first epitaxial structure; the first epitaxial structure at least comprises a lower cladding layer, a lower limiting layer, a lower waveguide layer, a spacing layer, a multi-quantum well active region, an upper limiting layer, an etching stop layer, an upper waveguide layer and an upper cladding layer which are sequentially stacked, a Bragg grating is manufactured in the upper waveguide layer, and the second epitaxial structure comprises a regrowth cladding layer and a contact layer which are sequentially stacked; the Van der Waals buffer layer is a two-dimensional material film, and the problems of lattice mismatch, thermal expansion coefficient mismatch and polarity structure difference of integration of the silicon substrate and the InP epitaxial layer are thoroughly solved from a physical mechanism by introducing the single-layer two-dimensional material Van der Waals buffer layer.

The invention discloses a preparation method of a gallium oxide semi-insulating substrate and the gallium oxide semi-insulating substrate, which comprises the following steps: performing proton irradiation treatment on a gallium oxide single-crystal substrate to introduce lattice defects into the gallium oxide single-crystal substrate, and performing annealing treatment on the gallium oxide single-crystal substrate into which the lattice defects are introduced to obtain the gallium oxide semi-insulating substrate. According to the technical scheme, lattice defects are introduced into the gallium oxide single crystal substrate by adopting a proton irradiation process to form a deep energy level trap to effectively capture free carriers, so that the carrier concentration of the material is remarkably reduced, and the resistivity of the material is increased, thereby realizing stable conversion from a conductive state to a semi-insulating state; therefore, the conditions of poor doping uniformity, insufficient thermal stability and local resistivity fluctuation existing in a traditional element doping method are overcome, meanwhile, the defects of lattice mismatch, insufficient thermal conductivity and the like caused by a heterogeneous substrate are avoided, and the electrical property uniformity and the material structure integrity of the gallium oxide substrate are effectively improved. The method has the advantages of non-contact, low cost, easy regulation and control and the like.

The invention is applicable to the technical field of LED (light-emitting diode) preparation, and provides a growth method of a green-light LED epitaxial structure, which comprises the following steps of: sequentially growing a nucleating layer, a U-shaped high-temperature GaN layer which is not doped, an N-shaped high-temperature GaN layer which is continuously doped with Si, a multi-quantum well light-emitting layer, a P-shaped AlGaN layer which is doped with Al and Mg and a high-temperature P-shaped GaN layer which is doped with Mg by adopting an MOCVD (metal organic chemical vapor deposition) process; the composite nucleating layer replaces a traditional single GaN nucleating layer, lattice mismatch and stress accumulation are reduced from the source, and the dislocation defect of the multi-quantum well layer is reduced; according to the invention, electric leakage of a green light LED device is effectively reduced, the luminous efficiency and the antistatic capability are improved, and the method is suitable for preparation of a high-brightness GaN-based green light LED epitaxial wafer.

The application provides a high-entropy particle reinforced heat-resistant copper alloy, a preparation method and application thereof. The high-entropy particle reinforced heat-resistant copper alloy comprises a copper matrix phase and FeCoNiCrSi high-entropy particle phases dispersed in the copper matrix phase; and the chemical formula of the high-entropy particle reinforced heat-resistant copper alloy is (Fe a Co b Ni c Cr d Si e ) x Cu 100‑x , wherein a is 15-30, b is 25-45, c is 1-5, d is 10-20, e is 10-40, and x is 4-6. In the copper alloy, the FeCoNiCrSi high-entropy particle phase serves as a reinforcing core, effectively prevents dislocation movement through dislocation pinning effect, significantly improves the mechanical strength of the obtained copper alloy, minimizes the stress generated by lattice mismatch to ensure the toughness of the obtained alloy, prevents high-temperature creep of the copper alloy, and significantly improves the heat resistance of the copper alloy.

The application provides a ferroelectric thin film with a two-dimensional layered electrode and a preparation method thereof. The ferroelectric thin film comprises a ferroelectric hafnium oxide thin film and a two-dimensional layered calcium nitride electrode arranged on the ferroelectric hafnium oxide thin film. The calcium nitride of the application has excellent in-plane lattice matching with hafnium oxide (111), and the lattice mismatch degree is extremely low, which is beneficial to realize high-quality epitaxial growth of the heterostructure and provides a structural basis for device manufacturing. The calcium nitride of the application can form stable chemical bonds (such as Hf-N and O-Ca) with hafnium oxide at the interface, can effectively enhance the interface bonding force, and improve the structural stability of the device. The calcium nitride of the application can significantly inhibit the depolarization field in the hafnium oxide thin film, restore and exceed the ferroelectric polarization intensity of the hafnium oxide bulk, and significantly improve the ferroelectric performance of the hafnium oxide.

A capacitor includes first and second electrodes spaced apart from each other, a dielectric layer disposed between the first and second electrodes, the dielectric layer including at least one of hafnium and zirconium, a first insertion layer disposed between the first electrode and the dielectric layer, and a second insertion layer disposed between the dielectric layer and the second electrode. The first insertion layer includes a first conductive material different from the hafnium or zirconium forming the dielectric layer. The second insertion layer includes a second conductive material different from the hafnium or zirconium forming the dielectric layer. The first and second conductive materials each have a lattice constant with a lattice mismatch of 2% or less from a horizontal lattice constant of a dielectric material of the dielectric layer.

This invention relates to the field of memory technology, specifically to a ferroelectric metal-controlled memristor and chip based on a single layer of gallium oxide and a single layer of blue phosphorus. The ferroelectric metal-controlled memristor includes a top electrode layer, a control layer, and a bottom electrode layer, which are sequentially contacted from top to bottom. It combines the unique ferroelectric properties of gallium oxide with the excellent electrical properties of blue phosphorus, a two-dimensional material. The control layer formed by these two materials interacts through van der Waals forces, and the polarization direction of the gallium oxide layer is switched by applying voltages in different directions to the heterojunction, enabling memristor writing and reading. This avoids the interface defects and lattice mismatch problems introduced by strong chemical bonds in traditional memristors, thus reducing the operating power consumption of the memristor while improving its read / write speed and stability.

This invention discloses an MSM interdigitated wideband ultraviolet photodetector and its fabrication method, belonging to the field of semiconductor technology. The detector includes: a substrate; an AlN nucleation layer on the substrate surface; a heterostructure on the surface of the AlN nucleation layer away from the substrate, wherein the heterostructure includes GaN, GaON, and Ga2O3 layers stacked sequentially from bottom to top; and interdigitated electrodes on the surface of the Ga2O3 layer away from the substrate. This invention introduces a GaON layer between the Ga2O3 and GaN heterojunctions. This GaON layer acts as a lattice buffer layer, effectively releasing the lattice mismatch stress between Ga2O3 and GaN, significantly improving the interface quality of the heterojunction, and enhancing the separation and collection efficiency of charge carriers, thus significantly improving the overall performance of the MSM interdigitated ultraviolet photodetector.

The application relates to a molecular beam epitaxy preparation method of epitaxial high-quality AlN on a Si substrate and an AlN epitaxial wafer, and the preparation method comprises the following steps: S1, obtaining a substrate, performing infrared lamp baking on the substrate, performing high-temperature deoxidization after heating pretreatment, and obtaining a pretreated substrate; S2, adopting a molecular beam epitaxy method to pre-deposit an Al layer on the pretreated substrate; S3, adopting the molecular beam epitaxy method to grow an AlN epitaxial layer on the pre-deposited Al layer; and S4, continuously introducing a nitrogen plasma post-treatment, and cooling to a wafer transfer temperature to obtain an epitaxial wafer. In the technical scheme, the pre-deposited Al layer can inhibit the reaction between the substrate and N in the AlN layer, the formation of amorphous particles is avoided, the AlN morphology is improved, meanwhile, the pre-deposited Al layer not only relieves the lattice mismatch problem between the substrate material and the AlN, but also improves the Al atom migration rate for the growth of the subsequent AlN layer, promotes two-dimensional growth, and thus the AlN crystal quality is improved.

The present invention discloses a low lattice mismatch MISHEMT interface buffer layer, a preparation method thereof, and a MISHEMT device containing the same, relating to the field of semiconductor technology. The interface buffer layer is disposed below a gate dielectric layer and comprises: a first AlGaN layer; a second AlGaN layer, the second AlGaN layer being deposited on the upper surface of the first AlGaN layer; a third AlGaN layer, the third AlGaN layer being deposited on the upper surface of the second AlGaN layer; and an AlN layer, the AlN layer being deposited between the third AlGaN layer and the gate dielectric layer; the Al content in the first AlGaN layer, the second AlGaN layer, and the third AlGaN layer increasing in sequence. The interface buffer layer provided by the present invention significantly reduces the lattice mismatch between adjacent materials, with the overall lattice mismatch being far less than 2.4%, and can effectively reduce deep energy level defects caused by energy level arrangement mutations.

The invention relates to AlGaN based on porous AlN growth and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: step 1, providing a sapphire-based AlN substrate; step 2, preparing an alkaline melt solution, completely immersing the substrate into the alkaline melt solution for corrosion, then taking out the substrate, cleaning and drying to obtain a sapphire-based AlN substrate intermediate; corrosion holes are formed in the surface of the AlN layer of the sapphire-based AlN substrate intermediate, and the hole diameter of the corrosion holes is 50-100 nm. 3, after water and oxygen removal treatment is carried out on the sapphire-based AlN substrate intermediate, an AlGaN layer is deposited; the thickness of the AlGaN layer is 1 to 1.5 [mu] m. According to the preparation method, lattice mismatch of AlN and AlGaN is relieved through the lateral epitaxial process in the AlGaN growth process, relaxation stress is achieved, the crystal quality is improved, the surface damage function is reduced, and growth of the thick-film AlGaN with the high quality and the good surface is achieved.

The application relates to the technical field of semiconductor material preparation, in particular to a liquid phase epitaxial growth method and equipment for dynamically regulating lattice mismatch. The specific content is as follows: a substrate is pretreated to prepare micro pits and grooves of the substrate, and a uniform solution is prepared according to phase diagram information; a temperature gradient is set in a multi-zone temperature control epitaxial furnace, and the epitaxial growth of the substrate is controlled through a boat device; the substrate and the solution pool are sequentially moved into the furnace; during the epitaxial growth process, the lattice constant error, morphology and photoelectric properties of the growth are detected, and when the detection signal deviates from the predetermined threshold, the lattice mismatch is compensated by adjusting the solution concentration and the temperature; during the displacement process, the mother liquor remaining between different layers is poured into the grooves of the substrate through the inclined substrate. The application solves the problem of lattice mismatch control by real-time detection and real-time regulation of the lattice mismatch, and improves the quality and performance of the epitaxial layer.

The application discloses a substrate, a forming method of the substrate and a light emitting diode. The substrate comprises a modification layer and a body layer. The modification layer extends from a first surface of the substrate to a second surface in a direction perpendicular to the substrate. The body layer extends from a side of the modification layer away from the first surface to the second surface. A side of the body layer away from the modification layer is formed as the second surface of the substrate. The modification layer comprises a diffusion element other than the body layer. The diffusion element can change a lattice parameter of a surface of the substrate, ensure a crystal form of the substrate unchanged, and reduce a lattice mismatch between the substrate and an epitaxial layer and a dislocation density of the epitaxial layer. The application performs annealing treatment on the substrate when forming the modification layer. Therefore, the content of doped atoms and the lattice parameter of the modification layer gradually change from the first surface to the second surface of the substrate. The lattice matching degree with the epitaxial layer is greatly improved. The problem that high temperature warping divergence is caused by excessive residual stress of the substrate is solved. The internal quantum efficiency and wavelength uniformity of the epitaxial layer are optimized.

Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer / second doped layer, but also can improve surface roughness of the first doped layer / second doped layer.

The invention provides a semiconductor power device and a forming method thereof, the semiconductor power device comprises a substrate and a nucleating layer, a buffer layer and a dislocation regulation and control layer which are sequentially formed on the substrate, the dislocation regulation and control layer comprises a first high-resistance layer, a patterned lattice mismatch layer and a second high-resistance layer, the first high-resistance layer is formed on the buffer layer, and the second high-resistance layer is formed on the patterned lattice mismatch layer. The patterned lattice mismatch layer is formed on the first high-resistance layer and exposes a part of the first high-resistance layer, the second high-resistance layer covers the exposed first high-resistance layer and extends to cover the patterned lattice mismatch layer, and the second high-resistance layer has blade type dislocation. Due to the existence of the blade type dislocation, continuously distributed hole traps can be induced around the blade type dislocation and are coupled with the original traps in the buffer layer, a channel for hole transmission can be formed, hole redistribution is realized through the channel, electron accumulation in the buffer layer can be effectively relieved, and the dynamic performance degradation of the device can be inhibited.

The invention relates to the technical field of optoelectronic devices, in particular to a laser based on a top surface HR layer and a planar metal grating and a preparation method, and the laser comprises a gain chip, an optical waveguide, the planar metal grating and a covering layer, the planar metal grating prepared by adopting an electronic evaporation plating process replaces traditional complex three-dimensional etching, so that the controllable precision and flatness of the grating structure are greatly improved, an InP secondary epitaxy process is abandoned, the whole process flow is simplified, the production cost is reduced, the product performance consistency and the product yield are improved, and the production cost is reduced. The reflection filtering efficiency is remarkably improved, the purity of the Bragg reflection spectrum is guaranteed, the narrow linewidth performance of the laser is achieved, the covering layer covers the plane metal grating, the problem that semiconductor secondary epitaxial lattices are not matched is effectively solved, diffraction light can be restrained, light energy overflow is reduced, and the freedom degree is increased through the design of the outer cavity structure.

The invention discloses a manufacturing method of a semiconductor epitaxial layer, which comprises the following steps that doping is carried out in a semiconductor substrate to form a well region, and a first defect on the top surface of the semiconductor substrate comprises a lattice mismatch defect caused by impurities of the well region; and executing more than one cycle step to form the transition layer, wherein the cycle step comprises the step of performing a first interface repair process to repair the exposed defect on the surface of the front layer. And performing first epitaxial growth to form a non-doped first epitaxial sub-layer on the surface of the front layer. And forming a main body layer of the semiconductor epitaxial layer, wherein a second interface repairing process is performed to repair the defect exposed on the surface of the transition layer. And performing second epitaxial growth to form the non-doped main body layer on the surface of the transition layer. The rate of the first epitaxial growth is smaller than that of the second epitaxial growth, and the thickness of the main body layer is larger than that of each first epitaxial sub-layer. According to the invention, defects, especially pit defects, formed on the surface of the semiconductor epitaxial layer due to the influence of doped impurities on the surface of the semiconductor substrate can be improved.

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, and relates to the technical field of semiconductors. The first doping type well region is formed in the substrate along the first side of the substrate, the stress region and the second doping type source region are formed in the first doping type well region, and the second doping type drain region is formed in the stress region; the gate structure is formed on the substrate along the first side of the substrate; wherein the stress region is formed by growing a material which is in lattice mismatch with the substrate material, and along the thickness direction of the substrate, the gate structure covers a part of the stress region and a part of the top of the first doping type well region, and is connected with the second doping type drain region and the second doping type source region. According to the technical scheme, the electron mobility can be improved, and then the current capacity of the nLDMOS is improved.

The invention discloses a gallium nitride / molybdenum disulfide heterojunction photoelectric detector and a preparation method, and belongs to the field of photoelectric detectors, and the photoelectric detector comprises a gallium nitride layer with a first conduction type; the passivation layer covers the surface of the gallium nitride layer and is provided with an open pore area exposing the gallium nitride layer; the molybdenum disulfide thin film is transferred to the surface of the passivation layer, and at least part of the molybdenum disulfide thin film is in direct contact with the gallium nitride layer through the opening area to form a heterojunction; and the first electrode and the second electrode are electrically connected with the gallium nitride layer and the molybdenum disulfide film respectively. The heterojunction is formed by combining the two-dimensional material and the three-dimensional material, so that the performance of the device can be effectively improved; meanwhile, the molybdenum disulfide thin film is directly transferred to the surface of the passivation layer and is in direct contact with the gallium nitride layer through the opening area, chemical bond connection does not exist between the molybdenum disulfide thin film and the gallium nitride layer, and the molybdenum disulfide thin film and the gallium nitride layer are combined through Van der Waals force, so that the problem of lattice mismatch between the molybdenum disulfide thin film and the gallium nitride layer can be effectively solved; and the performance of the device can be improved.

The present invention provides an LED epitaxial wafer, an epitaxial growth method, and an LED chip. The epitaxial growth method includes controlling the growth temperature to gradually decrease from a high temperature to a low temperature when growing a P-type contact layer, and at the same time, doping Mg, controlling the Mg introduction concentration to be higher than the Mg concentration of the P-type GaN layer, and gradually increasing the Mg introduction concentration as the growth temperature decreases. This is because growing the Mg-doped GaN layer at a higher temperature can obtain a Mg-doped GaN layer with higher crystal quality. At the same time, at high temperatures, Mg is more easily doped into the GaN layer, but at low temperatures, the Mg doping efficiency decreases significantly. By increasing the introduction Mg concentration at low temperatures, the problem of low Mg doping concentration at low temperatures can be improved. Furthermore, since Mg is gradually incorporated during the cooling process from high temperature to low temperature, the lattice mismatch of the Mg-doped GaN layer is effectively reduced, thereby reducing the contact resistance of the P-type contact layer while ensuring the crystal quality.