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508 results about "Lattice mismatch" patented technology

High-strength and high-toughness aluminum nitride ceramic and preparation method thereof

The invention discloses a high-strength and high-toughness aluminum nitride ceramic and a preparation method thereof, and relates to the technical field of ceramics, a sol-gel method is adopted to coat the surface of aluminum nitride with a stable shell layer to form a core-shell structure, meanwhile, the low lattice mismatch rate of a core-shell interface is utilized to reduce thermal resistance, and toughness and thermal conductivity are both considered; according to the external magnetic field tape casting method, the magnetic dipole moment orientation principle is utilized, an external magnetic field is applied in the tape casting stage, the in-plane mechanical property is improved, and the fracture toughness is improved through the magnetism of aluminum nitride whiskers; a reinforcement is introduced to improve the mechanical property and corrosion resistance of the aluminum nitride ceramic material, multi-granularity powder is compounded, large-particle aluminum nitride powder is used as a sintering and heat-conducting framework material, and high activity provided by submicron particles is utilized to promote sintering, so that the sintering temperature of aluminum nitride can be remarkably reduced, and the performance is greatly improved; and the aluminum nitride substrate expands more application fields on a future packaging circuit.
Owner:四川富乐华半导体科技有限公司 +1

Gallium oxide heteroepitaxial substrate and preparation method thereof

The invention relates to the technical field of semiconductors, in particular to a gallium oxide heteroepitaxial substrate and a preparation method thereof. The gallium oxide heteroepitaxial substrate comprises: a sapphire substrate; the sapphire substrate is provided with a beveled surface; a periodic pattern structure is arranged on the beveled surface of the sapphire substrate; the depth of a repetitive unit of the periodic pattern structure is 200 nm to 20 [mu] m, the maximum envelope size is 100 nm to 50 [mu] m, and the period interval is 200 nm to 100 [mu] m. The sapphire substrate is subjected to beveling processing and patterning processing, lattice mismatch is remarkably relieved, stress is released, accordingly, dislocation density is reduced, defects in the gallium oxide thin film are reduced, the gallium oxide single crystal thin film with better crystal quality is obtained, and the method has important application value in the field of gallium oxide thin film semiconductor material preparation.
Owner:GALLIUM TECHNOLOGY (CHANGZHOU) CO LTD

Deep ultraviolet LED device and epitaxial growth method thereof

According to the deep ultraviolet LED device provided by the invention, a first stress regulation and control layer and a second stress regulation and control layer are sequentially arranged between an electron injection layer and a quantum well active layer, and the Al component content x2 of the first stress regulation and control layer and the Al component content x3 of the second stress regulation and control layer meet the following relations: x3 < = (x4 + x5) / 2, x2 > = (x1 + x3) / 2, x4 > x3 > x5; according to the invention, by regulating and controlling the Al component content of each layer, the lattice mismatch between the second stress regulation and control layer and the quantum well active layer is reduced, and the lattice mismatch among the electron injection layer, the first stress regulation and control layer and the second stress regulation and control layer is reduced, so that the tensile stress can be applied to the quantum well active layer, and the performance of the device is improved. Therefore, the pressure stress generated by the bottom epitaxial structure on the quantum well active layer is compensated, and the light-emitting efficiency of the deep ultraviolet LED device is finally improved.
Owner:SUZHOU UVCANTEK CO LTD

Deep ultraviolet LED epitaxial structure, deep ultraviolet LED device comprising same and preparation method of deep ultraviolet LED epitaxial structure

The invention discloses a deep ultraviolet LED epitaxial structure, a deep ultraviolet LED device comprising the same and a preparation method, and the epitaxial structure sequentially comprises a sapphire substrate, an AlN nanowire array layer, an AlN intrinsic layer and an AlGaN light-emitting structure layer from bottom to top. The AlGaN light-emitting structure layer further comprises an n-type AlGaN electron injection layer, a quantum well active layer, a p-type AlGaN electron blocking layer and other device structures. According to the invention, the vertically arranged AlN nanowire array is introduced to replace a traditional AlN buffer layer, so that lattice mismatching stress caused by a substrate is significantly released, and the dislocation density of an epitaxial layer is effectively reduced; meanwhile, the introduction of the AlN intrinsic layer further flattens the epitaxial interface and optimizes the lattice quality, thereby providing a high-quality template for the growth of a high-performance AlGaN material. The epitaxial structure is suitable for an LED device in a deep ultraviolet band, and the crystal quality, the electrical property and the luminous efficiency of the device can be improved.
Owner:WUHAN TEXTILE UNIV

Integrated gallium nitride and gallium oxide power chip, preparation method thereof and electronic equipment

The invention provides an integrated gallium nitride and gallium oxide power chip, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. According to the epitaxial structure in the integrated gallium nitride and gallium oxide power chip, a GaN layer and a Ga2O3 layer are integrated and epitaxially arranged on the same substrate, heteroepitaxial lattice mismatch is reduced by adopting a method of epitaxially extending the Ga2O3 layer on the GaN layer, and the crystal quality is improved. According to the epitaxial structure, a first functional component is formed on the first area, a second functional component is formed on the second area, the surface of the first area is the surface of the side, deviating from the substrate, of the barrier layer, the surface of the second area is the surface of the side, deviating from the substrate, of the Ga2O3 layer, and the aim that a Ga2O3 power chip and a GaN power chip are integrally arranged on the same substrate is achieved. The processes of lead interconnection, bonding and the like are reduced, the size of a wide bandgap semiconductor power system can be further reduced, and the problems of parasitic loss, response delay, noise and the like caused when discrete chips are integrated are avoided.
Owner:XIAMEN CHANGELIGHT CO LTD

Planar short wave infrared detector and preparation method and application thereof

The invention discloses a planar short-wave infrared detector and a preparation method and application thereof. The preparation method comprises the following steps: S1, sequentially growing the buffer layer, the N-type contact layer, the absorption layer, the undoped P-type layer and the cap layer on the substrate; s2, growing a layer of dielectric film on the surface of the cap layer; corroding the exposed cap layer by adopting a wet etching process; s3, removing the dielectric film after corrosion is finished; p-doped Al < 1-w > InwAs is grown in the corrosion area; s4, removing the cap layer and the P-doped Al < 1-w > InwAs on the upper surface of the undoped P-type layer; s5, growing a layer of passivation film on all the exposed upper surfaces; and forming a pattern of a metal contact layer on the surface of the passive film by photoetching to form a P electrode and an N electrode. According to the invention, the problem of high Zn diffusion process difficulty caused by large lattice mismatch between the epitaxial layer with high In component and the substrate is solved, and the performance of the device is improved.
Owner:ZHONGSHAN DEHUA CHIP TECH CO LTD

Preparation method and application of MOF-on-MOF heterojunction metal-organic framework material rich in oxygen defects

The present invention discloses a preparation method and application of a MOF-on-MOF heterojunction metal-organic framework material rich in oxygen defects, belonging to the technical field of electrocatalytic oxygen evolution reaction. The present invention first grows Ni NDC nanosheets in situ on a carrier by a solvothermal method, and then grows Fe BDC nanosheets on the surface of the Ni NDC nanosheets by a solvothermal method to form Ni NDC@Fe BDC ultra-thin nanosheets. This method can synthesize a MOF-on-MOF type metal-organic framework under the premise of lattice mismatch. The synthesized Ni NDC@Fe BDC combines the advantages of multi-component material hybridization, ultra-thin nanosheets and defect induction, which can increase the number of active sites and promote the rapid transfer / redistribution of electrons in the catalytic process. The MOF-on-MOF heterojunction metal-organic framework has good electrocatalytic performance and excellent total water decomposition performance in alkaline oxygen evolution reaction.
Owner:GUANGXI NORMAL UNIV

Epitaxial layer of lattice transition type gallium nitride HEMT device and manufacturing method

The invention discloses an epitaxial layer of a lattice transition type gallium nitride HEMT device and a manufacturing method of the epitaxial layer. The epitaxial layer comprises a substrate, and an AlN nucleating layer, an AlGaN buffer layer, a superlattice buffer layer, an AlGaN transition layer, a high-carbon GaN layer, a low-carbon GaN channel layer, an AlGaN barrier layer and a cap layer which are sequentially stacked on the surface of the substrate in the longitudinal direction. According to the invention, after the AlGaN transition layer is inserted between the superlattice buffer layer and the high-carbon GaN layer, the superlattice buffer layer with high aluminum content is firstly transited to the AlGaN transition layer with medium aluminum content and then transited to the high-carbon GaN layer without aluminum, so that lattice mismatch between layers is reduced, and deformation and warping of a wafer are reduced.
Owner:SHENZHEN GALLIUM SEMICON TECH CO LTD

Light emitting diode epitaxial structure and preparation method thereof

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial structure and a preparation method thereof. The light-emitting diode epitaxial structure comprises a substrate, an h-BN / O2 layer, a low-temperature GaN buffer layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer which are arranged in sequence, the h-BN / O2 layer subjected to oxygen plasma treatment is inserted between the heterogeneous substrate and the GaN epitaxial layer, the low-temperature GaN buffer layer is grown on the h-BN / O2 layer by controlling the process conditions, and the h-BN / O2 layer and the low-temperature GaN buffer layer are matched, so that lattice mismatch dislocation, residual stress and thermal mismatch of an epitaxial material grown on the heterogeneous substrate can be effectively modulated, the scattering efficiency under high current is improved, and the light emitting efficiency is improved. The probability of radiation recombination of the heteroepitaxial material is improved, and the requirement for heteroepitaxy is lowered.
Owner:JIANGXI ZHAO CHI SEMICON CO LTD

Additive manufacturing low-stress high-entropy alloy design system and method based on lattice mismatch

The invention relates to the technical field of additive manufacturing, in particular to an additive manufacturing low-stress high-entropy alloy design system and method based on lattice mismatch, which are used for effectively reducing interface stress of gradient materials, and the method comprises the following steps: analyzing a matrix crystal structure, and determining a high-entropy alloy crystal structure type consistent with the matrix crystal structure; based on a high-entropy alloy crystal structure, a high-entropy alloy virtual lattice approximate structure model is established; performing structure geometric optimization on the model to obtain a high-entropy alloy lattice constant under a stable structure; according to the obtained lattice constants, the proportion of all elements of the high-entropy alloy is adjusted by comparing the lattice constants of the base body, and the redesigned high-entropy alloy is calculated till the lattice mismatch degree of the high-entropy alloy and the base body is low; and gradient design is conducted on the designed high-entropy alloy with the low lattice mismatch degree and the base body, and the design result of the low lattice mismatch degree and the low interface stress of the additive manufacturing high-entropy alloy gradient material is obtained.
Owner:XI AN JIAOTONG UNIV +1

Electrochemically induced metal oriented growth method based on gallium-based liquid metal substrate

PendingCN120844162ALattice mismatchLiquid metal
The invention relates to an electrochemical induced metal oriented growth method based on a gallium-based liquid metal substrate, and belongs to the technical field of electrochemical materials. According to the present invention, the dynamic smooth interface and the low lattice mismatch characteristic of the liquid metal are utilized, the reduction kinetics of the metal ions is regulated and controlled through the constant current mode, the high orientation degree growth of the crystal along the specific crystal face (such as Zn (002) and In (111)) is achieved, and the prepared deposited metal dominant crystal face has the high orientation degree. The problems of stress accumulation and dendritic crystals of a traditional solid substrate can be solved, and the method is suitable for green preparation of nanowire arrays and functional coatings; and the process is simple and convenient to operate, easy in control of process parameters and suitable for batch production.
Owner:KUNMING UNIV OF SCI & TECH

Method and device for improving Q value of bulk acoustic wave resonator

The invention relates to the technical field of integrated circuit manufacturing, and particularly discloses a method and device for improving the Q value of a bulk acoustic wave resonator, and the method comprises the steps: respectively generating a bottom electrode and a dielectric layer of the resonator on a substrate, and respectively defining the regions where the bottom electrode and the dielectric layer are located into a resonant region and a non-resonant region; generating a piezoelectric layer lattice regulation and control layer in the non-resonance area; and a piezoelectric layer and a top electrode of the resonator are sequentially generated on the piezoelectric layer crystal lattice regulation and control layer and the bottom electrode. Before the piezoelectric layer is grown in the non-resonant region, a layer of material which is mismatched with the lattice of the piezoelectric layer is grown, and when the piezoelectric layer is grown on substrate materials with different crystal orientations, atoms on two sides of an interface cannot realize an ideal one-to-one pairing state, so that the characteristic of relatively large lattice mismatch is easily formed; therefore, the crystal orientation of the piezoelectric layer in the non-resonance area can be regulated and controlled, and the Q value of the resonator is improved.
Owner:NINGBO SEMICON INT CORP

UVB LED epitaxial structure based on Mg-doped AlN template and preparation method thereof

The invention belongs to the field of semiconductor materials, and particularly relates to a UVB LED epitaxial structure and a preparation method thereof. The UVB LED epitaxial structure sequentially comprises a plain film substrate, a PVDAlN layer, an AlN high-temperature layer, an Mg-doped AlN high-temperature layer, an AlGaN / AlN superlattice transition layer, an n-type AlGaN layer, an Al < x > Ga < 1-x > N / Al < y > Ga < 1-y > N multi-quantum well active layer, an Mg-doped p-type AlGaN barrier layer, an Mg-doped p-type AlGaN layer and an Mg-doped p-type GaN layer from top to bottom. According to the method, the AlN template is subjected to doping treatment through Mg, so that the in-plane lattice constant of the Mg-doped AlN template is increased, lattice mismatch and threading dislocation between the AlN template and the upper AlGaN layer are successfully improved, a low-internal-stress efficient UVB-LED is developed, and the optical performance of the UVB-LED is improved.
Owner:NINGBO ANN SEMICON CO LTD

Light emitting diode epitaxial structure and preparation method thereof

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial structure which comprises a substrate, and a graphene composite nano layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer are sequentially stacked on the substrate. The graphene composite nano layer comprises a modified graphene layer and a ZnO sub-layer which are stacked in sequence, the modified graphene layer is arranged on the substrate, and the ZnO sub-layer is arranged on the modified graphene layer; the modified graphene layer is subjected to nitrogen plasma treatment, and the thickness of the modified graphene layer is 10-100 nm; and the thickness of the ZnO sub layer is 20 nm to 200 nm. According to the invention, lattice mismatch dislocation, residual stress and thermal mismatch of the epitaxial material grown on the heterogeneous substrate can be effectively modulated, the scattering efficiency under high current is improved, the probability of radiation recombination of the heterogeneous epitaxial material is improved, and the requirement of heterogeneous epitaxy is relaxed at the same time.
Owner:JIANGXI ZHAO CHI SEMICON CO LTD

High-quality silicon carbide homoepitaxial wafer and preparation method thereof

The invention discloses a high-quality silicon carbide homoepitaxial wafer and a preparation method thereof, the epitaxial wafer comprises an epitaxial layer, a SiC substrate and a regulation and control layer, the regulation and control layer is located outside the back surface of the substrate or inside the back surface of the substrate, and the epitaxial layer is located on the front surface of the substrate; wherein the lattice mismatch degree between the regulation and control layer and the substrate has the same sign as the lattice mismatch degree between the epitaxial layer and the substrate, but the absolute value is larger; the preparation method comprises the following steps: preparing the regulation and control layer on the back surface of the SiC substrate; front deposition and surface scratch of the substrate caused by the previous step are eliminated through chemical mechanical polishing; growing an epitaxial layer on the front surface of the substrate through epitaxial deposition; and finally, chemically and mechanically polishing to eliminate micro pits and step coalescence morphology on the surface of the epitaxial layer to obtain the epitaxial wafer. The regulation and control layer is introduced to the back surface of the substrate, lattice mismatch between the epitaxial layer and the substrate is weakened through the regulation and control layer, dislocation proliferation and slippage are reduced, and the high-quality silicon carbide homoepitaxial wafer with low defect density and small deformation is prepared.
Owner:NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD

Preparation method of strain channel FinFET

The invention discloses a preparation method of a strain channel FinFET, and belongs to the technical field of integrated circuit manufacturing. According to the method, after the Fin line is manufactured, amorphous silicon is generated through an injection amorphization method, the amorphous silicon is recrystallized after a strain medium layer is adopted for covering and high-temperature annealing is conducted, at the moment, tensile stress / compressive stress needed by an N / PMOS can be formed between the crystalline silicon and a strain medium, and then the strain medium material is selectively removed, so that preparation of the strain channel FinFET is achieved. According to the invention, lattice mismatch between the strain dielectric material and the crystalline silicon is utilized to generate tensile stress or compressive stress required by a FinFET device, N / PMOS channel strain is realized by using a single strain material, the process of channel stress engineering is simplified, the process complexity is reduced, and the method has the potential of being applied to technical nodes of 14 nm and above.
Owner:PEKING UNIV +1

Quantum Dot and Preparation Method Therefor, Composition, and Optoelectronic Device

The present disclosure provides a quantum dot and its preparation method, composition and optoelectronic device, the quantum dot includes an inner core and a ZnSe shell located on a surface of the inner core, wherein the ZnSe shell includes at least 4 ZnSe monolayers, surface ligands of the quantum dot include long chain linear zinc carboxylate ligands, branched-chain zinc carboxylate ligands, and short chain linear zinc carboxylate ligands, and the quantum dot is a spherical quantum dot. The quantum dot has a controllable shape and size and uniform morphology. The tensile strain generated inside the ZnSe shell due to lattice mismatch can be significantly alleviated, and the inner core experiences weaker compression strain. Under the synergistic effect of surface ligands of the quantum dot, the quantum dot has a PL quantum yield of close to 100%, and the photophysical stability and photochemical stability are improved.
Owner:ZHEJIANG UNIV +1

Wafer bonding method and heterogeneous wafer

The invention discloses a wafer bonding method and a heterogeneous wafer, and relates to the technical field of semiconductor materials.The wafer bonding method comprises the steps that contact pressing is conducted, at least one of a first wafer and a second wafer is made to rotate around the axis of the first wafer and the second wafer, so that the relative rotation angle of the first wafer and the second wafer in the circumferential direction reaches a preset value, and the first wafer and the second wafer are laminated under a preset pressure, and the preset value is adjusted according to the materials of the first wafer and the second wafer. According to the wafer bonding method, the bonded wafers rotate around the axes of the wafers in the contact pressing step, the chemical matching environment of the bonding interface is improved by adjusting the relative rotation angle of the two wafers in the circumferential direction, the adverse effect on wafer bonding caused by stress generated by lattice mismatch is reduced, the overall bonding quality is improved, and the wafer bonding quality is improved. The bonding strength is greatly improved, and the bonding stability is enhanced.
Owner:INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD

Photoelectric detector and preparation method thereof

The invention provides a photoelectric detector and a preparation method thereof, which are applied to the technical field of semiconductors, and the photoelectric detector comprises a gallium oxide light absorption layer; the two-dimensional Van der Waals material layer is arranged on the gallium oxide light absorption layer and is combined with the gallium oxide light absorption layer through Van der Waals force to form a vertical heterojunction; the metal electrode is formed on the surfaces of the gallium oxide light absorption layer and the two-dimensional Van der Waals material layer; wherein the work function of the two-dimensional Van der Waals material layer is matched with the work function of the gallium oxide light absorption layer, so that staggered energy band arrangement is formed at the interface of the vertical heterojunction. According to the invention, interface defects caused by lattice mismatch can be avoided, and non-radiative recombination of photon-generated carriers can be reduced, so that the response speed and photoelectric conversion efficiency of the photoelectric detector can be greatly improved.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Phase field dynamics method for simulating precipitation evolution of gamma'phase in nickel-based superalloy under external stress

The invention relates to the field of metallurgical casting, in particular to a phase field dynamics method for simulating precipitation evolution of a gamma'phase in nickel-based superalloy under external stress. The method comprises the following steps: S1, acquiring thermal and dynamic information of a gamma phase and a gamma'phase by adopting a CALPHAD method according to target components of the nickel-based superalloy; s2, constructing a strain energy item containing plastic strain, and defining stress-free strain generated by lattice mismatch during gamma-to-gamma 'phase transformation and a gradient energy item capable of considering different slip system information; s3, establishing a phase field model, solving a phase field control equation at a two-phase interface by adopting a Kim-Kim-Suzuki interface model to obtain a sequence parameter result value, and investigating the influence of different forms of external stress loads and different plastic strains on gamma'phase precipitation growth; and S4, the gamma'phase precipitation evolution structure in the nickel-based high-temperature alloy is subjected to visualization treatment, and the influence rule of the external stress and the plastic strain on gamma 'phase precipitation evolution is clarified.
Owner:INST OF METAL RESEARCH - CHINESE ACAD OF SCI

Neuromorphic transistor taking lithium niobate or lithium tantalate single crystal as gate medium and preparation method thereof

PendingCN119603993Agood ferroelectric propertiesreduce generationGate dielectricLattice mismatch
The invention discloses a neuromorphic transistor taking lithium niobate or lithium tantalate single crystal as a gate medium and a preparation method of the neuromorphic transistor, and belongs to the technical field of semiconductor devices. The neuromorphic transistor comprises a substrate layer, a bottom gate electrode layer, a gate dielectric layer and a patterned electrode assembly which are arranged from top to bottom. The material of the substrate layer comprises single crystal LiNbO3 (0001) or single crystal LiTaO3 (0001); the bottom gate electrode layer comprises a single crystal ZnSnO3 thin film; and the gate dielectric layer comprises a single crystal LiNbO3 film or a single crystal LiTaO3 film. A gate dielectric layer can be directly deposited after a single crystal ZnSnO3 thin film is epitaxially grown on the single crystal LiNbO3 (0001) or single crystal LiTaO3 (0001) substrate, the situation of lattice mismatch is effectively avoided, meanwhile, introduction of a buffer layer is reduced, thin film growing methods in a device structure are physical vapor deposition methods, safety is higher, and process cost is lower.
Owner:YONGJIANG LAB

Gallium nitride-based high electron mobility transistor epitaxial structure and preparation method thereof

The epitaxial structure comprises a substrate layer, a polymerization layer, a high-resistance layer, a middle layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, the polymerization layer comprises a combination of a buffer layer and a transition layer, the channel layer is provided with a two-dimensional electron conducting channel, and the high-resistance layer is arranged between the high-resistance layer and the middle layer. The material composition of the barrier layer is ALInGaN, and the channel layer is formed at the interface of the barrier layer and the intermediate layer. According to the epitaxial structure disclosed in the technical scheme, AlInGaN is adopted as a barrier layer material to replace a traditional AlGaN barrier layer, the lattice constant of the barrier layer can be adjusted by introducing the In element, lattice mismatch between the barrier layer and a GaN channel layer is reduced, and meanwhile high polarization intensity is kept, so that the two-dimensional electron gas concentration is improved, and meanwhile the performance of the epitaxial structure is improved. The interface defects are reduced, and the electron mobility is improved.
Owner:GUANGXI YUNXIN SEMICON TECH CO LTD

Graphene-diamond composite coating, and preparation method and application thereof

The application discloses a graphene-diamond composite coating and a preparation method and application thereof, and belongs to the technical field of materials. The graphene-diamond composite coating comprises a diamond coating and a graphene coating; graphene sp2 bond structure is covalently combined with diamond sp3 bond structure; and the graphene coating has a graphene structure with non-parallel growth mainly in a vertical direction. The graphene-diamond composite coating has small lattice mismatch between the diamond and the graphene, avoids volume expansion caused in a friction heat process, and has the advantages that the diamond coating can provide a support layer for the graphene, forms super-strong C-C covalent bonds at an interface, and significantly improves the adhesion strength of the graphene; the graphene can avoid brittle fracture of the diamond, and significantly improves the lubricating performance of the surface of the diamond coating. The composite coating has better wear resistance, a low friction coefficient and excellent oxidation resistance, and can remain stable under high-temperature and high-load working conditions, so that the service life and processing efficiency of wear-resistant parts are improved.
Owner:GUANGDONG INST OF NEW MATERIALS

Two-color infrared detector

A GaSb substrate, a GaSb buffer layer, an epitaxial thin film, a first electrode and a second electrode are adopted, the GaSb substrate, the GaSb buffer layer and the epitaxial thin film are sequentially stacked, and the epitaxial thin film comprises a first contact layer, a long wave absorption layer, a medium wave absorption layer and a second contact layer which are sequentially stacked; the first contact layer is in contact with the GaSb buffer layer; and etching is carried out on the basis of the epitaxial thin film to form a step, the depth of the step reaches the first contact layer, the first electrode is conducted with the first contact layer, the second electrode is conducted with the second contact layer, finally, a two-color infrared detector structure is formed, 12ML InAs / 2ML InAs0. 5Sb0. 5 superlattice is used as a material of the medium-wave absorption layer, good lattice matching is formed between the medium-wave absorption layer and the long-wave absorption layer, and the performance of the two-color infrared detector is improved. Therefore, interface defects and stress accumulation caused by lattice mismatch are reduced, and a smooth and uniform interface is provided for subsequent growth of the epitaxial layer, so that the growth difficulty of the epitaxial layer can be reduced.
Owner:SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD

Silicon-based indium phosphide laser and preparation method thereof

The invention discloses a silicon-based indium phosphide laser and a preparation method thereof, and relates to the technical field of semiconductor devices, the silicon-based indium phosphide laser comprises a silicon substrate, a composite insulating layer, a Van der Waals buffer layer and an indium phosphide epitaxial structure which are stacked in sequence; the indium phosphide epitaxial structure comprises a first epitaxial structure stacked on the Van der Waals buffer layer and a second epitaxial structure stacked on the first epitaxial structure; the first epitaxial structure at least comprises a lower cladding layer, a lower limiting layer, a lower waveguide layer, a spacing layer, a multi-quantum well active region, an upper limiting layer, an etching stop layer, an upper waveguide layer and an upper cladding layer which are sequentially stacked, a Bragg grating is manufactured in the upper waveguide layer, and the second epitaxial structure comprises a regrowth cladding layer and a contact layer which are sequentially stacked; the Van der Waals buffer layer is a two-dimensional material film, and the problems of lattice mismatch, thermal expansion coefficient mismatch and polarity structure difference of integration of the silicon substrate and the InP epitaxial layer are thoroughly solved from a physical mechanism by introducing the single-layer two-dimensional material Van der Waals buffer layer.
Owner:JIANGXI ZHAOCHI INTEGRATED TECHNOLOGY CO LTD +1

Preparation method of gallium oxide semi-insulating substrate and gallium oxide semi-insulating substrate

The invention discloses a preparation method of a gallium oxide semi-insulating substrate and the gallium oxide semi-insulating substrate, which comprises the following steps: performing proton irradiation treatment on a gallium oxide single-crystal substrate to introduce lattice defects into the gallium oxide single-crystal substrate, and performing annealing treatment on the gallium oxide single-crystal substrate into which the lattice defects are introduced to obtain the gallium oxide semi-insulating substrate. According to the technical scheme, lattice defects are introduced into the gallium oxide single crystal substrate by adopting a proton irradiation process to form a deep energy level trap to effectively capture free carriers, so that the carrier concentration of the material is remarkably reduced, and the resistivity of the material is increased, thereby realizing stable conversion from a conductive state to a semi-insulating state; therefore, the conditions of poor doping uniformity, insufficient thermal stability and local resistivity fluctuation existing in a traditional element doping method are overcome, meanwhile, the defects of lattice mismatch, insufficient thermal conductivity and the like caused by a heterogeneous substrate are avoided, and the electrical property uniformity and the material structure integrity of the gallium oxide substrate are effectively improved. The method has the advantages of non-contact, low cost, easy regulation and control and the like.
Owner:SHENZHEN UNIV

Growth method of green light LED epitaxial structure

The invention is applicable to the technical field of LED (light-emitting diode) preparation, and provides a growth method of a green-light LED epitaxial structure, which comprises the following steps of: sequentially growing a nucleating layer, a U-shaped high-temperature GaN layer which is not doped, an N-shaped high-temperature GaN layer which is continuously doped with Si, a multi-quantum well light-emitting layer, a P-shaped AlGaN layer which is doped with Al and Mg and a high-temperature P-shaped GaN layer which is doped with Mg by adopting an MOCVD (metal organic chemical vapor deposition) process; the composite nucleating layer replaces a traditional single GaN nucleating layer, lattice mismatch and stress accumulation are reduced from the source, and the dislocation defect of the multi-quantum well layer is reduced; according to the invention, electric leakage of a green light LED device is effectively reduced, the luminous efficiency and the antistatic capability are improved, and the method is suitable for preparation of a high-brightness GaN-based green light LED epitaxial wafer.
Owner:XIANGNENG HUALEI OPTOELECTRONICS

High-entropy particle reinforced heat-resistant copper alloy, preparation method and application thereof

The application provides a high-entropy particle reinforced heat-resistant copper alloy, a preparation method and application thereof. The high-entropy particle reinforced heat-resistant copper alloy comprises a copper matrix phase and FeCoNiCrSi high-entropy particle phases dispersed in the copper matrix phase; and the chemical formula of the high-entropy particle reinforced heat-resistant copper alloy is (Fe a Co b Ni c Cr d Si e ) x Cu 100‑x , wherein a is 15-30, b is 25-45, c is 1-5, d is 10-20, e is 10-40, and x is 4-6. In the copper alloy, the FeCoNiCrSi high-entropy particle phase serves as a reinforcing core, effectively prevents dislocation movement through dislocation pinning effect, significantly improves the mechanical strength of the obtained copper alloy, minimizes the stress generated by lattice mismatch to ensure the toughness of the obtained alloy, prevents high-temperature creep of the copper alloy, and significantly improves the heat resistance of the copper alloy.
Owner:CHINALCO RES INST OF SCI & TECH CO LTD

High-storage-density medium buffer layer sandwich structure phase change storage thin film material and preparation method and application thereof

The invention relates to a high-storage-density medium buffer layer sandwich structure phase change storage thin film material and a preparation method and application thereof.The phase change storage thin film material is of a sandwich structure, and the phase change storage thin film material is prepared by alternately arranging two different phase change layer materials and medium layer materials through a magnetron sputtering method; and a similar superlattice structure is formed. The structural general formula of the multilayer film structure is [M (a nm)-A (b nm)-N (c nm)] n, M and N are two different phase change layer materials, and A is a dielectric layer material.Compared with the prior art, the multilayer film structure has the advantages that the dielectric layer with the nanoscale thickness is introduced into the multilayer film structure, the interface stress between adjacent film layers can be effectively relieved, the lattice mismatch phenomenon is reduced, and therefore the stability of the multilayer film structure is remarkably improved. In addition, the introduction of the dielectric layer can also regulate and control the electrical characteristics of the thin film in the phase change process, enhance the distinction degree of multi-stage resistance states, further improve the storage density, and solve the problem that the storage capacity of a traditional phase change memory is limited.
Owner:SHANGHAI INST OF TECH

Gallium oxide thin film based on low-oxygen-content gallium oxide buffer layer and preparation method of gallium oxide thin film

The invention provides a gallium oxide thin film based on a low-oxygen-content gallium oxide buffer layer and a preparation method of the gallium oxide thin film, and relates to the technical field of semiconductor material manufacturing processes. The preparation method of the gallium oxide thin film comprises the following steps: performing magnetron sputtering on the surface of a substrate by adopting gallium oxide as a target material in a rare gas atmosphere to obtain the substrate with a low-oxygen-content gallium oxide buffer layer; performing magnetron sputtering on the surface of the low-oxygen-content gallium oxide buffer layer of the substrate with the low-oxygen-content gallium oxide buffer layer by adopting gallium oxide as a target material in a mixed atmosphere of oxygen and rare gas to obtain a gallium oxide thin film; and annealing the gallium oxide thin film to obtain the gallium oxide thin film based on the low-oxygen-content gallium oxide buffer layer. According to the invention, the gallium oxide buffer layer with low oxygen content is prepared on the substrate and then the gallium oxide thin film is prepared, so that the influence of thermal mismatch and lattice mismatch on the crystallization performance of the gallium oxide thin film in the high-temperature annealing process is reduced.
Owner:SHANGHAI UNIV