304 results about "Silicon-germanium" patented technology

Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

A semiconductor structure including a substrate, a first stack of channel layers on the substrate and a second stack of channel layers vertically aligned above the first stack. The width of the first is greater than the second. Additionally, the first channel layers can be cladded with germanium while the second channel layers can have a dog-bone shape.

A transistor includes a channel that has sidewall that consists of an angular indent that is directly connected to the source / drain region without a channel extension region therebetween. For example, the transistor may be a p-type transistor in which the channel may be composed of silicon germanium (SiGe) and may be directly connected to a p-type source / drain region. Unlike some traditional pFETs, there is not a traditional channel extension region (e.g., a Si channel extension region) between the SiGe channel and the p-type source / drain regions. As such, the resistance between the channel and the source / drain is relatively reduced.

A device includes silicon nanostructures above in an n-type region, and silicon germanium nanostructures in a p-type region, wherein at least one of the silicon germanium nanostructures includes a silicon core region having a first concentration of germanium of about 20% or less, a silicon germanium region having a first interface between the silicon core region and the silicon germanium region, and a second silicon germanium region having a second interface between the silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second concentration of germanium up to about 40%. A concentration gradient of germanium increases from the first concentration of germanium to the second concentration of germanium. A high-k dielectric layer surrounds at least one of the silicon nanostructures and at least one of the silicon germanium nanostructures.

Semiconductor devices (e.g., gate-all-around (GAA) devices), processing tools for fabricating GAA devices, methods for fabricating GAA devices, and internal spacer liners and internal spacers for GAA devices are described. The methods include forming an internal spacer liner within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) arranged alternately in a plurality of stacked pairs. The internal spacer liner includes a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner can be doped with a dopant (e.g., with a p-type dopant or an n-type dopant). One or more steps of the methods described herein are performed in situ in an integrated processing tool system.

Integrated circuit structures having direct backside source or drain contacts implemented by silicon germanium etch stops are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fins and the second plurality of horizontally stacked nanowires or fins, the epitaxial source or drain structure over and electrically coupled to the corresponding conductive back contact, the conductive back contact extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

A dopant may included in one or more sacrificial layers, e.g., silicon layers or silicon germanium layers, used for forming nanoribbon transistors. Adding a dopant to a silicon germanium layer may cause the silicon germanium to be more stress neutral, to prevent relaxation after etching stacks of individuated nanoribbons. Alternatively, when added to one or more sacrificial layers of silicon, the doped silicon layers may counteract elastic stress from the silicon germanium layers. The dopant layers may be included at various positions in a stack of materials. The dopant layer may include one or more dopants selected from carbon, arsenic, boron, and phosphorus.

A film stack is formed a workpiece. The film stack is fabricated by sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form a carbon-doped silicon-germanium and silicon mini-stack disposed on a substrate during a deposition cycle. The deposition cycle comprises exposing a workpiece including the substrate to a first gas including a first precursor to deposit a first silicon-germanium layer and exposing the workpiece to a second gas including the first precursor to deposit a carbon-silicon-germanium layer on the first silicon-germanium layer. Further, the deposition cycle includes exposing the workpiece to a third gas including the first precursor to deposit a second silicon-germanium layer on the carbon-silicon-germanium layer. The deposition cycle further includes exposing the workpiece to a fourth gas including a second precursor to deposit the silicon film on the second silicon-germanium layer. The second precursor differs from the first precursor.

The present invention discloses a method and structure for integrating CMOS and self-aligned silicon-germanium (SGe) HBTs. The method comprises: forming multiple shallow trench isolation regions on a silicon substrate; forming polysilicon gates, gate silicon oxide, and lightly doped regions in the CMOS active region; opening a base window in the HBT region and forming a selective ion implantation region; forming a SiGe base region; forming a sacrificial emitter region; etching to expose the surface of the outer region of the SiGe base region and forming an extrinsic base region; forming an emitter window and exposing the SiGe surface of the underlying SiGe base region; forming a silicon emitter region in the emitter window, and photolithographically patterning the emitter region and the extrinsic base region. The present invention utilizes a novel sacrificial emitter process, combined with a method for self-aligning the raised extrinsic base region and the emitter region, effectively reducing process complexity and making the device process compatible with standard CMOS and other passive device processes.

An etching composition that includes a quaternary ammonium salt having 8 or more carbon atoms and selectively dissolves silicon over silicon germanium, and may further include a chelating agent, an etching method comprising etching a structure that contains silicon and silicon germanium by using the etching composition, a method for manufacturing a semiconductor device, and a method for manufacturing a gate-all-around-type transistor using the etching composition.

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source / drain (S / D) regions on the first and second fin structures, respectively, forming first and second oxidation stop layers on the n- and p-type S / D regions, respectively, epitaxially growing first and second semiconductor layers on the first and second oxidation stop layers, respectively, converting the first and second semiconductor layers into first and second semiconductor oxide layers, respectively, forming a first silicide-germanide layer on the p-type S / D region, and forming a second silicide-germanide layer on the first silicide-germanide layer and on the n-type S / D region.

The invention provides a semiconductor manufacturing method, which comprises providing a substrate, forming a silicon germanium epitaxial layer in the substrate, forming a first silicon layer on the silicon germanium epitaxial layer, wherein the first silicon layer is a pure silicon layer, and forming a second silicon layer on the first silicon layer, wherein the second silicon layer comprises a silicon layer doped with boron atoms.

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, the semiconductor substrate comprises a first region and a second region, a silicon layer is formed on the surface of the semiconductor substrate in the first region, a silicon germanium layer is formed on the surface of the semiconductor substrate in the second region, and the silicon germanium layer is formed on the surface of the semiconductor substrate in the second region. The surface of the silicon layer is flush with the surface of the silicon germanium layer; and the fins are respectively located in the first region and the second region, the heights of the fins in the first region and the second region are the same, the fin in the first region is composed of a part of the semiconductor substrate and the silicon layer, and the fin in the second region is composed of a part of the semiconductor substrate and the silicon germanium layer. According to the semiconductor structure and the forming method thereof, the depths of the silicon fins and the silicon germanium fins can be consistent, and the defects of fin merging, fin bending and the like caused by the fact that the silicon germanium fins are too deep are avoided.

A method of selectively etching silicon germanium with respect to silicon in a stack located on a chuck in an etch chamber is provided. The chuck is maintained at a temperature of 15 DEG C or less. The stack is exposed to an etch gas comprising a fluorine-containing gas to selectively etch the silicon germanium with respect to silicon.

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region, the second region including a first edge region and a middle region; forming a first edge trench in the first edge region, the first edge trench having a first aspect ratio; filling a first edge layer in the first edge trench; forming a middle trench in the middle region; removing the first edge layer to form an epitaxial trench, the epitaxial trench having a second aspect ratio, the first aspect ratio being greater than the second aspect ratio; and forming an epitaxial layer in the epitaxial trench. Since the first aspect ratio of the first edge trench is high, a round corner span at a bottom of the first edge trench is small, and thus a round corner at a bottom of the epitaxial trench is small. In this way, after a patterning process, a portion of a first fin portion is doped with material of the epitaxial layer, and a portion of a second fin portion has less silicon germanium material, thereby affecting performance of the semiconductor structure formed finally.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

The present invention relates to a monolithic integrated high-speed modulation silicon-based optical chip and a preparation method thereof, which comprises, from bottom to top, a silicon-based optoelectronic layer (I), an intermediate layer (II), a lithium niobate layer or a lithium tantalate layer (III); the silicon-based optoelectronic layer (I) comprises, from bottom to top, a substrate (1), an insulating layer (2), a silicon waveguide (3), an InP laser (4), a silicon germanium photodetector (5), and a thermo-optical phase shifter (6). Based on the excellent electro-optical modulation performance of lithium niobate (or lithium tantalate), the present invention focuses on a special bonding method and a CMOS-compatible silicon photonic flow-through process, obtains a lithium niobate (or lithium tantalate)-silicon multilayer structure, and further realizes a fully integrated transceiver optical chip with a laser, a photodetector, and an electro-optical modulator, which can meet the current requirements of on-chip optical systems for high compactness and low power consumption.

Methods of reducing wafer bowing in 3D DRAM devices are described using stacks including one or more of epitaxial silicon (Si), carbon doped silicon (SiC), silicon germanium (SiGe), and carbon-doped silicon germanium (SiGeC). A plurality of film stacks is formed on a substrate surface, each of the film stacks comprises two doped silicon layers having different dopant amounts and a sacrificial layer that may be doped or undoped. 3D DRAM devices are also described.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

A semiconductor apparatus may include a substrate including a first region and a second region; a first device on the first region; and a second device on the second region. The first device may include a channel structure including an insulating isolation pattern, first semiconductor patterns stacked under a lower surface of the insulating isolation pattern and including silicon germanium, and second semiconductor patterns stacked on an upper surface of the insulating isolation pattern and including silicon. The second device may include a semiconductor stack at a level corresponding to a level of the channel structure. The semiconductor stack may include an intermediate semiconductor layer, first lower semiconductor layers and second lower semiconductor layers alternately stacked under a lower surface of the intermediate semiconductor layer, and first upper semiconductor layers and second upper semiconductor layers alternately stacked on an upper surface of the intermediate semiconductor layer.

Provided is an integrated circuit device and method of manufacturing same, the integrated circuit device including: a substrate including a memory cell area and a peripheral circuit area around the memory cell area; a cell transistor in the memory cell area; a peripheral circuit transistor in the peripheral circuit area; a capacitor structure including a lower electrode on the cell transistor, a dielectric film on a surface of the lower electrode, and an upper electrode on the dielectric film; a stacked plate structure covering the capacitor structure; and an interlayer insulating film covering the stacked plate structure in the memory cell area and covering the peripheral circuit transistor in the peripheral circuit area, wherein the stacked plate structure includes: a first plate layer including doped silicon germanium (SiGe); a middle layer conformally covering the first plate layer and including a metal silicide (MxSiy) including a metal (M); and a second plate layer conformally covering the middle layer and including the metal (M) of the metal silicide.

This invention relates to a composition and its application for the selective removal of silicon-germanium from silicon-germanium / silicon stacks in microelectronic devices. The composition comprises the following components in weight fractions: 0.0001-10 wt% polyalkyleneimide; 0.001-10 wt% fluoride; 0.1-70 wt% oxidant; 0.01-50 wt% buffer composition; 0.00001-1 wt% silicon inhibitor; 0.0001-1 wt% silicon-germanium etching stabilizer; 0.0001-20 wt% defoamer; and the balance being water. The composition of this invention can be used to selectively remove silicon-germanium from microelectronic devices having silicon and silicon-germanium stacks thereon during the manufacture of microelectronic devices.

A semiconductor structure, and a method for manufacturing a semiconductor structure. The semiconductor structure comprises: a substrate; a stack structure, which is located on the substrate, wherein the stack structure comprises a plurality of stack units stacked in a direction perpendicular to a surface of the substrate, and each stack unit at least comprises a stack of one memory cell element and one isolation structure; and a stress adjustment layer, which is located between the stack structure and the substrate, wherein the stress adjustment layer comprises a first silicon germanium layer, the material of the first silicon germanium layer comprises germanium-doped silicon, the content of germanium is a first composition ratio, the first composition ratio is linearly correlated with the ratio of the thickness of the memory cell element or the thickness of the isolation structure to the thickness of the stack unit, and the direction of thickness is the direction perpendicular to the surface of the substrate. By means of the semiconductor structure, a semiconductor device in which the problem of warping is ameliorated can be obtained.

The application relates to the technical field of semiconductors, in particular to a capacitor, which comprises a bottom electrode, a dielectric layer formed on the bottom electrode, and a top electrode assembly formed on the dielectric layer, wherein the top electrode assembly comprises a first top electrode, a second top electrode and a third top electrode which are sequentially stacked from one side of the dielectric layer; the first top electrode is a metal layer, the second top electrode is a carbon and boron doped silicon germanium layer, and the third top electrode is a boron doped silicon germanium layer. By forming the carbon and boron doped silicon germanium layer between the first top electrode and the third top electrode, a double structure of the carbon and boron doped silicon germanium layer and the boron doped silicon germanium layer is formed on the first top electrode, the resistance increase is greatly reduced, the residual stress of the boron doped silicon germanium layer is also reduced, the mechanical stress generated by the boron doped silicon germanium layer on the dielectric layer of the capacitor is lowered, and the dielectric leakage problem of the dielectric layer is solved.

The application provides a semiconductor structure manufacturing method, which comprises the following steps: providing a substrate; forming a first electrode layer on one side of the substrate; forming a dielectric layer on the surface of the first electrode layer far from the substrate; forming a second electrode layer on the surface of the dielectric layer far from the first electrode layer; performing chlorine removal pretreatment on the second electrode layer; and forming a third electrode layer on the surface of the second electrode layer far from the dielectric layer. The method solves the problem that chlorine ions at the junction of a silicon germanium layer in the prior art affect the interface reliability.

Executable processing methods can produce semiconductor structures that can include high-k dielectric materials. A method can include forming a silicon layer over a semiconductor substrate. The semiconductor substrate can include silicon germanium. The method can include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate to form a sacrificial oxide. The method can include removing the sacrificial oxide. The method can include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The method can include forming a high-k dielectric material overlying the oxygen-containing material.

A method for forming a doped layer is disclosed. The doped layer can be used in NMOS or silicon germanium applications. For example, a halide precursor can be used to create a doped layer in an n-type dopant application.

The present invention relates to the use of a composition for selectively etching a silicon layer in the presence of a layer comprising a silicon germanium alloy, the composition comprising: (a) 0.1% to 5% by weight of a pyridine having the formula (E1) wherein RE1 is a substituent selected from the group consisting of-(XE3) s-COORE2,-(XE3) s-OH,-(XE3) s-NH2,-(XE3) s-CONH2 and-(XE3) s-CN; m is the number of substituents RE1 and is 1 or 2; xE3 is a C1 to C4 alkanediyl group; rE2 is H or a C1 to C4 alkyl group; and s is 0 or 1; rE1 must not be in position 2 except if m is 1 and RE1 is-(XE3) s-NH2; (b) 0.1% to 10% by weight of an amine having the formula (E2) if RE1 is-(XE3) s-COOH wherein XE1, XE2 are independently selected from C2-C3 alkanediyl; yE is selected from NH2 and OH; n is 0, 1, 2 or 3; and (c) water. (E1) (E2)

The application discloses a space correlation disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment, and belongs to the technical field of electronic equipment heat dissipation, in particular to a thermoelectric refrigeration system based on space correlation disordered silicon germanium (SiGe) nanowire. The system comprises a hot end 1, a cold end 6 and a thermoelectric conversion module. The thermoelectric material layer 4 is used for responding to direct current provided by the power driving circuit 5, generating a temperature difference between two ends to enhance the refrigeration effect. The thermoelectric material layer 4 is also used for adjusting the temperature difference between two ends of the thermoelectric material layer 4 by adjusting the current value of the direct current provided by the power driving circuit 5, and then adjusting the temperature difference between the hot end 1 and the cold end 6. The space correlation disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment is suitable for heat dissipation of electronic equipment.