235 results about "Silicon-germanium" patented technology

Semiconductor devices (e.g., gate-all-around (GAA) devices), processing tools for fabricating GAA devices, methods for fabricating GAA devices, and internal spacer liners and internal spacers for GAA devices are described. The methods include forming an internal spacer liner within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) arranged alternately in a plurality of stacked pairs. The internal spacer liner includes a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner can be doped with a dopant (e.g., with a p-type dopant or an n-type dopant). One or more steps of the methods described herein are performed in situ in an integrated processing tool system.

A dopant may included in one or more sacrificial layers, e.g., silicon layers or silicon germanium layers, used for forming nanoribbon transistors. Adding a dopant to a silicon germanium layer may cause the silicon germanium to be more stress neutral, to prevent relaxation after etching stacks of individuated nanoribbons. Alternatively, when added to one or more sacrificial layers of silicon, the doped silicon layers may counteract elastic stress from the silicon germanium layers. The dopant layers may be included at various positions in a stack of materials. The dopant layer may include one or more dopants selected from carbon, arsenic, boron, and phosphorus.

A film stack is formed a workpiece. The film stack is fabricated by sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form a carbon-doped silicon-germanium and silicon mini-stack disposed on a substrate during a deposition cycle. The deposition cycle comprises exposing a workpiece including the substrate to a first gas including a first precursor to deposit a first silicon-germanium layer and exposing the workpiece to a second gas including the first precursor to deposit a carbon-silicon-germanium layer on the first silicon-germanium layer. Further, the deposition cycle includes exposing the workpiece to a third gas including the first precursor to deposit a second silicon-germanium layer on the carbon-silicon-germanium layer. The deposition cycle further includes exposing the workpiece to a fourth gas including a second precursor to deposit the silicon film on the second silicon-germanium layer. The second precursor differs from the first precursor.

The present invention discloses a method and structure for integrating CMOS and self-aligned silicon-germanium (SGe) HBTs. The method comprises: forming multiple shallow trench isolation regions on a silicon substrate; forming polysilicon gates, gate silicon oxide, and lightly doped regions in the CMOS active region; opening a base window in the HBT region and forming a selective ion implantation region; forming a SiGe base region; forming a sacrificial emitter region; etching to expose the surface of the outer region of the SiGe base region and forming an extrinsic base region; forming an emitter window and exposing the SiGe surface of the underlying SiGe base region; forming a silicon emitter region in the emitter window, and photolithographically patterning the emitter region and the extrinsic base region. The present invention utilizes a novel sacrificial emitter process, combined with a method for self-aligning the raised extrinsic base region and the emitter region, effectively reducing process complexity and making the device process compatible with standard CMOS and other passive device processes.

An etching composition that includes a quaternary ammonium salt having 8 or more carbon atoms and selectively dissolves silicon over silicon germanium, and may further include a chelating agent, an etching method comprising etching a structure that contains silicon and silicon germanium by using the etching composition, a method for manufacturing a semiconductor device, and a method for manufacturing a gate-all-around-type transistor using the etching composition.

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source / drain (S / D) regions on the first and second fin structures, respectively, forming first and second oxidation stop layers on the n- and p-type S / D regions, respectively, epitaxially growing first and second semiconductor layers on the first and second oxidation stop layers, respectively, converting the first and second semiconductor layers into first and second semiconductor oxide layers, respectively, forming a first silicide-germanide layer on the p-type S / D region, and forming a second silicide-germanide layer on the first silicide-germanide layer and on the n-type S / D region.

The invention provides a semiconductor manufacturing method, which comprises providing a substrate, forming a silicon germanium epitaxial layer in the substrate, forming a first silicon layer on the silicon germanium epitaxial layer, wherein the first silicon layer is a pure silicon layer, and forming a second silicon layer on the first silicon layer, wherein the second silicon layer comprises a silicon layer doped with boron atoms.

A method of selectively etching silicon germanium with respect to silicon in a stack located on a chuck in an etch chamber is provided. The chuck is maintained at a temperature of 15 DEG C or less. The stack is exposed to an etch gas comprising a fluorine-containing gas to selectively etch the silicon germanium with respect to silicon.

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region, the second region including a first edge region and a middle region; forming a first edge trench in the first edge region, the first edge trench having a first aspect ratio; filling a first edge layer in the first edge trench; forming a middle trench in the middle region; removing the first edge layer to form an epitaxial trench, the epitaxial trench having a second aspect ratio, the first aspect ratio being greater than the second aspect ratio; and forming an epitaxial layer in the epitaxial trench. Since the first aspect ratio of the first edge trench is high, a round corner span at a bottom of the first edge trench is small, and thus a round corner at a bottom of the epitaxial trench is small. In this way, after a patterning process, a portion of a first fin portion is doped with material of the epitaxial layer, and a portion of a second fin portion has less silicon germanium material, thereby affecting performance of the semiconductor structure formed finally.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

Methods of reducing wafer bowing in 3D DRAM devices are described using stacks including one or more of epitaxial silicon (Si), carbon doped silicon (SiC), silicon germanium (SiGe), and carbon-doped silicon germanium (SiGeC). A plurality of film stacks is formed on a substrate surface, each of the film stacks comprises two doped silicon layers having different dopant amounts and a sacrificial layer that may be doped or undoped. 3D DRAM devices are also described.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

A semiconductor apparatus may include a substrate including a first region and a second region; a first device on the first region; and a second device on the second region. The first device may include a channel structure including an insulating isolation pattern, first semiconductor patterns stacked under a lower surface of the insulating isolation pattern and including silicon germanium, and second semiconductor patterns stacked on an upper surface of the insulating isolation pattern and including silicon. The second device may include a semiconductor stack at a level corresponding to a level of the channel structure. The semiconductor stack may include an intermediate semiconductor layer, first lower semiconductor layers and second lower semiconductor layers alternately stacked under a lower surface of the intermediate semiconductor layer, and first upper semiconductor layers and second upper semiconductor layers alternately stacked on an upper surface of the intermediate semiconductor layer.

This invention relates to a composition and its application for the selective removal of silicon-germanium from silicon-germanium / silicon stacks in microelectronic devices. The composition comprises the following components in weight fractions: 0.0001-10 wt% polyalkyleneimide; 0.001-10 wt% fluoride; 0.1-70 wt% oxidant; 0.01-50 wt% buffer composition; 0.00001-1 wt% silicon inhibitor; 0.0001-1 wt% silicon-germanium etching stabilizer; 0.0001-20 wt% defoamer; and the balance being water. The composition of this invention can be used to selectively remove silicon-germanium from microelectronic devices having silicon and silicon-germanium stacks thereon during the manufacture of microelectronic devices.

A semiconductor structure, and a method for manufacturing a semiconductor structure. The semiconductor structure comprises: a substrate; a stack structure, which is located on the substrate, wherein the stack structure comprises a plurality of stack units stacked in a direction perpendicular to a surface of the substrate, and each stack unit at least comprises a stack of one memory cell element and one isolation structure; and a stress adjustment layer, which is located between the stack structure and the substrate, wherein the stress adjustment layer comprises a first silicon germanium layer, the material of the first silicon germanium layer comprises germanium-doped silicon, the content of germanium is a first composition ratio, the first composition ratio is linearly correlated with the ratio of the thickness of the memory cell element or the thickness of the isolation structure to the thickness of the stack unit, and the direction of thickness is the direction perpendicular to the surface of the substrate. By means of the semiconductor structure, a semiconductor device in which the problem of warping is ameliorated can be obtained.

The application relates to the technical field of semiconductors, in particular to a capacitor, which comprises a bottom electrode, a dielectric layer formed on the bottom electrode, and a top electrode assembly formed on the dielectric layer, wherein the top electrode assembly comprises a first top electrode, a second top electrode and a third top electrode which are sequentially stacked from one side of the dielectric layer; the first top electrode is a metal layer, the second top electrode is a carbon and boron doped silicon germanium layer, and the third top electrode is a boron doped silicon germanium layer. By forming the carbon and boron doped silicon germanium layer between the first top electrode and the third top electrode, a double structure of the carbon and boron doped silicon germanium layer and the boron doped silicon germanium layer is formed on the first top electrode, the resistance increase is greatly reduced, the residual stress of the boron doped silicon germanium layer is also reduced, the mechanical stress generated by the boron doped silicon germanium layer on the dielectric layer of the capacitor is lowered, and the dielectric leakage problem of the dielectric layer is solved.

The application provides a semiconductor structure manufacturing method, which comprises the following steps: providing a substrate; forming a first electrode layer on one side of the substrate; forming a dielectric layer on the surface of the first electrode layer far from the substrate; forming a second electrode layer on the surface of the dielectric layer far from the first electrode layer; performing chlorine removal pretreatment on the second electrode layer; and forming a third electrode layer on the surface of the second electrode layer far from the dielectric layer. The method solves the problem that chlorine ions at the junction of a silicon germanium layer in the prior art affect the interface reliability.

Executable processing methods can produce semiconductor structures that can include high-k dielectric materials. A method can include forming a silicon layer over a semiconductor substrate. The semiconductor substrate can include silicon germanium. The method can include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate to form a sacrificial oxide. The method can include removing the sacrificial oxide. The method can include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The method can include forming a high-k dielectric material overlying the oxygen-containing material.

A method for forming a doped layer is disclosed. The doped layer can be used in NMOS or silicon germanium applications. For example, a halide precursor can be used to create a doped layer in an n-type dopant application.

The present invention relates to the use of a composition for selectively etching a silicon layer in the presence of a layer comprising a silicon germanium alloy, the composition comprising: (a) 0.1% to 5% by weight of a pyridine having the formula (E1) wherein RE1 is a substituent selected from the group consisting of-(XE3) s-COORE2,-(XE3) s-OH,-(XE3) s-NH2,-(XE3) s-CONH2 and-(XE3) s-CN; m is the number of substituents RE1 and is 1 or 2; xE3 is a C1 to C4 alkanediyl group; rE2 is H or a C1 to C4 alkyl group; and s is 0 or 1; rE1 must not be in position 2 except if m is 1 and RE1 is-(XE3) s-NH2; (b) 0.1% to 10% by weight of an amine having the formula (E2) if RE1 is-(XE3) s-COOH wherein XE1, XE2 are independently selected from C2-C3 alkanediyl; yE is selected from NH2 and OH; n is 0, 1, 2 or 3; and (c) water. (E1) (E2)

The application discloses a space correlation disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment, and belongs to the technical field of electronic equipment heat dissipation, in particular to a thermoelectric refrigeration system based on space correlation disordered silicon germanium (SiGe) nanowire. The system comprises a hot end 1, a cold end 6 and a thermoelectric conversion module. The thermoelectric material layer 4 is used for responding to direct current provided by the power driving circuit 5, generating a temperature difference between two ends to enhance the refrigeration effect. The thermoelectric material layer 4 is also used for adjusting the temperature difference between two ends of the thermoelectric material layer 4 by adjusting the current value of the direct current provided by the power driving circuit 5, and then adjusting the temperature difference between the hot end 1 and the cold end 6. The space correlation disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment is suitable for heat dissipation of electronic equipment.

Embodiments utilize a silicon germanium layer deposited to a low germanium percentage under a substrate. The substrate is used to form a field effect transistor FET structure. After formation of the FET, the silicon germanium layer is oxidized to drive germanium to a concentrated sublayer of the silicon germanium layer. The sublayer is used as a stop layer to remove the oxidized portion of the silicon germanium layer.

A semiconductor device is provided. The semiconductor device includes a substrate, a gate stack layer formed over the substrate, a silicon germanium (SiGe) channel layer formed in the substrate and covered by the gate stack layer, first and second source / drain (S / D) regions, and first and second lightly doped drain (LDD) layers. The first and second S / D regions are formed in the substrate on a first side and a second side opposite to the first side of the gate stack layer, respectively. The first LDD layer is disposed between the SiGe channel layer and the first S / D region, and the second LDD layer is disposed between the SiGe channel layer and the second S / D region. The first and second LDD layers include SiGe materials.

Some examples herein provide a method of forming a doped silicon germanium layer. The method may include simultaneously exposing a substrate to (a) a silicon precursor, (b), a germanium precursor, (c) a boron precursor, and (d) a heteroleptic gallium precursor. The heteroleptic gallium precursor may include (i) at least one straight chain alkyl group in which a terminal carbon is directly bonded to gallium, and (ii) at least one tertiary alkyl group in which a tertiary carbon is directly bonded to gallium. The method may include reacting the silicon precursor, the germanium precursor, the boron precursor, and the heteroleptic gallium precursor to form a silicon germanium layer on the substrate that is doped with boron and gallium.

The application provides a back contact structure of a laminated battery, a preparation method of the back contact structure and a photovoltaic cell. The back contact structure of the laminated battery comprises a tunneling oxide layer, a silicon germanium crystallization layer, an amorphous silicon buffer layer and a polycrystalline silicon transfer layer which are sequentially stacked. The content of germanium in the silicon germanium crystallization layer increases from the tunneling oxide layer to the amorphous silicon buffer layer. The lattice constant of the silicon germanium crystallization layer changes in a gradient from the tunneling oxide layer to the amorphous silicon buffer layer. The application effectively reduces the lattice mismatch degree and improves the battery conversion efficiency by optimizing the carrier transfer and interface characteristics.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device for reducing on-resistance and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate, a drift region, a source region, a drain region and a gate structure, wherein the drift region, the source region and the drain region are formed in the semiconductor substrate. The key point is that a high carrier mobility layer is formed in the drift region, and the layer forms a part of a conductive path between the channel and the drain region. The high carrier mobility layer can be a selective epitaxial growth silicon germanium layer, and can also be a germanium-containing layer formed by ion implantation. By introducing the high mobility layer, the migration rate of carriers in the drift region is remarkably improved, the drift region resistance and the total on-resistance of the device are effectively reduced, and meanwhile, the influence on the breakdown voltage is small. According to the LDMOS device, the restrictive relation between the on-resistance and the breakdown voltage in a traditional LDMOS device is broken, low on-resistance and high breakdown voltage are achieved at the same time, and the power efficiency and the overall performance of the device are improved.

The invention discloses a fishbone-shaped nanosheet semiconductor device and a preparation method thereof, and relates to the field of semiconductor materials, the fishbone-shaped nanosheet semiconductor device comprises a substrate and a fishbone-shaped structure extending from the substrate; the fishbone-shaped structure comprises a trunk perpendicular to the substrate, the trunk comprises at least one stacked silicon germanium layer and a silicon layer, and the silicon layer is arranged on the silicon germanium layer; the trunk comprises at least one stage of annular groove; and the annular groove is generated based on oxidation and etching of the silicon germanium layer. According to the fishbone-shaped nanosheet semiconductor structure provided by the invention, the nanosheet channel which is vertical and parallel to the substrate is constructed in a mode of oxidizing and etching the silicon germanium layer, so that the fishbone-shaped nanosheet semiconductor device combines the advantages of FinFET and GAANS; the problem that in the prior art, the electrical properties of an NFET and a PFET are not matched due to the fact that the electron mobility of the crystal face of a GAANS device (100) is far higher than the hole mobility is effectively solved, and the driving capacity of a semiconductor device is improved.

The present invention discloses a method for manufacturing a semiconductor device, which relates to the field of semiconductor technology and is intended to improve the yield of semiconductor devices. The method for manufacturing a semiconductor device comprises: forming a fin-shaped structure on a semiconductor substrate. The fin-shaped structure comprises an alternating first sacrificial layer and a channel layer, and an alternating second sacrificial layer and a third sacrificial layer. The material of one of the second sacrificial layer and the third sacrificial layer comprises silicon or silicon germanium, and the material of the other comprises silicon germanium or germanium. The difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%, and the second sacrificial layer is doped with an etching aid. A mask structure is formed across the fin-shaped structure. At least under the accelerated etching action of the etching aid, the second sacrificial layer is selectively removed to form a first dielectric filling region. A first middle dielectric isolation layer is formed within the first dielectric filling region. The first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the third sacrificial layer not covered by the mask structure are removed.

A semiconductor structure and a manufacturing method for a semiconductor structure. The semiconductor structure comprises: a substrate (10); a capacitor structure (107) located on the substrate (10), the capacitor structure (107) comprising a first electrode layer (1071), a capacitor dielectric layer (1072), and a second electrode layer (1073) which are sequentially stacked; a conductive plate (108) located on the surface of the second electrode layer (1073), the conductive plate (108) at least comprising a base layer and a first transition layer (1082) located on the surface of the base layer; and a contact member (109) inserted into the conductive plate (108), the contact member (109) being electrically connected to the second electrode layer (1073) by means of the conductive plate (108). The base layer comprises a first silicon germanium layer (1081), and the first transition layer (1082) comprises a first boron-doped polycrystalline silicon layer (1082b) and a second silicon germanium layer (1082a) arranged in a stack. The semiconductor structure has high reliability and stability.