366 results about "Silicon-germanium" patented technology

Disclosed herein is a composition for selectively etching a first silicon germanium layer having a first germanium content in the presence of a silicon layer or a second silicon germanium layer having a second germanium content, where the first germanium content is higher than the second germanium content, the composition including:(a) from 0.1 to 10% by weight of an oxidizing agent;(b) from 1 to 20% by weight of an etchant including a source of fluoride ions;(c) from 0.001 to 3% by weight of a selectivity enhancer of formula Si(d) from 0.001 to 3% by weight of an additional selectivity enhancer of formula S41or derivatives thereof obtained by homocondensation of the compounds of formula S41 or by co-condensation of the compounds of formula S41 with silanes of formula S42 in a weight ratio of 0.1 or moreand(e) water.

The invention provides a semiconductor device and a preparation method thereof. According to the preparation method of the semiconductor device, after a silicon germanium groove structure is formed, a sacrificial layer is adopted as a sacrificial medium, and a hard mask layer is formed on the surface of each exposed gate structure so as to fill the height difference of the surfaces of the gate structures. And carrying out planarization treatment on the hard mask layer by adopting a chemical mechanical polishing process, so that the heights of the gate structures are recovered to the same horizontal plane. Based on this, the gate structures with the same height not only are beneficial to carrying out chemical mechanical grinding of a larger window by adopting the same load parameter in the subsequent preparation process, but also are beneficial to etching and cleaning the pseudo gate and fully filling the polycrystalline silicon in the subsequent technological process of removing the pseudo gate and filling the polycrystalline silicon; and a better process effect is ensured, so that ideal key parameters can be obtained, and the device yield is improved.

Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

A semiconductor structure including a substrate, a first stack of channel layers on the substrate and a second stack of channel layers vertically aligned above the first stack. The width of the first is greater than the second. Additionally, the first channel layers can be cladded with germanium while the second channel layers can have a dog-bone shape.

The invention provides a CMOS device and a forming method thereof, and the forming method of the CMOS device comprises the steps: firstly executing a first etching process, and etching a first anti-reflection coating and a second dielectric layer of a second well region, so as to enable the top surface of the second dielectric layer to be lower than the top surface of a first dielectric layer; a second etching process is executed, the first dielectric layer is etched while germanium-silicon grooves are formed in the first well region on the two sides of the first grid electrode, and the top surface of the first dielectric layer is flush with the top surface of the second dielectric layer. A second dielectric layer is etched in advance in a first etching process before a first extension region is formed in a second well region to the etched height of a subsequent first dielectric layer when a germanium-silicon groove is formed, and then when the germanium-silicon groove is formed, the etched height of the first dielectric layer is the same as the height of the second dielectric layer. Therefore, the problem of the height difference of the gate structures on the first well region and the second well region is solved, namely, the height difference of the gate structures of the PMOS device and the NMOS device is reduced, no additional process is needed, and the production cost is reduced.

A transistor includes a channel that has sidewall that consists of an angular indent that is directly connected to the source / drain region without a channel extension region therebetween. For example, the transistor may be a p-type transistor in which the channel may be composed of silicon germanium (SiGe) and may be directly connected to a p-type source / drain region. Unlike some traditional pFETs, there is not a traditional channel extension region (e.g., a Si channel extension region) between the SiGe channel and the p-type source / drain regions. As such, the resistance between the channel and the source / drain is relatively reduced.

The present disclosure is directed to etching methods that are useful for, e.g., selectively removing silicon germanium (SiGe) from a semiconductor substrate as an intermediate step in a multistep semiconductor manufacturing process.

A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source / drain region contacts the spaced-apart channel regions. The source / drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.

A device includes silicon nanostructures above in an n-type region, and silicon germanium nanostructures in a p-type region, wherein at least one of the silicon germanium nanostructures includes a silicon core region having a first concentration of germanium of about 20% or less, a silicon germanium region having a first interface between the silicon core region and the silicon germanium region, and a second silicon germanium region having a second interface between the silicon germanium region and the second silicon germanium region, the second silicon germanium region having a second concentration of germanium up to about 40%. A concentration gradient of germanium increases from the first concentration of germanium to the second concentration of germanium. A high-k dielectric layer surrounds at least one of the silicon nanostructures and at least one of the silicon germanium nanostructures.

Semiconductor devices (e.g., gate-all-around (GAA) devices), processing tools for fabricating GAA devices, methods for fabricating GAA devices, and internal spacer liners and internal spacers for GAA devices are described. The methods include forming an internal spacer liner within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) arranged alternately in a plurality of stacked pairs. The internal spacer liner includes a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner can be doped with a dopant (e.g., with a p-type dopant or an n-type dopant). One or more steps of the methods described herein are performed in situ in an integrated processing tool system.

Integrated circuit structures having direct backside source or drain contacts implemented by silicon germanium etch stops are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fins and the second plurality of horizontally stacked nanowires or fins, the epitaxial source or drain structure over and electrically coupled to the corresponding conductive back contact, the conductive back contact extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.

A dopant may included in one or more sacrificial layers, e.g., silicon layers or silicon germanium layers, used for forming nanoribbon transistors. Adding a dopant to a silicon germanium layer may cause the silicon germanium to be more stress neutral, to prevent relaxation after etching stacks of individuated nanoribbons. Alternatively, when added to one or more sacrificial layers of silicon, the doped silicon layers may counteract elastic stress from the silicon germanium layers. The dopant layers may be included at various positions in a stack of materials. The dopant layer may include one or more dopants selected from carbon, arsenic, boron, and phosphorus.

A film stack is formed a workpiece. The film stack is fabricated by sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form a carbon-doped silicon-germanium and silicon mini-stack disposed on a substrate during a deposition cycle. The deposition cycle comprises exposing a workpiece including the substrate to a first gas including a first precursor to deposit a first silicon-germanium layer and exposing the workpiece to a second gas including the first precursor to deposit a carbon-silicon-germanium layer on the first silicon-germanium layer. Further, the deposition cycle includes exposing the workpiece to a third gas including the first precursor to deposit a second silicon-germanium layer on the carbon-silicon-germanium layer. The deposition cycle further includes exposing the workpiece to a fourth gas including a second precursor to deposit the silicon film on the second silicon-germanium layer. The second precursor differs from the first precursor.

A semiconductor device and a method of forming the device are disclosed. The semiconductor device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode (136, 236) on the MTJ stack. At least one of the bottom and top electrodes (136, 236) includes doped SiGeSn.

The invention relates to a composition suitable for a microelectronic device to selectively remove silicon germanium relative to silicon from a silicon germanium / silicon lamination and application. The composition comprises the following components in percentage by mass: 0.0001-10wt% of polyalkyleneimine, 0.0001-10wt% of a cosolvent, 0.0001-10wt% of an antioxidant and the 0.001 to 10 wt% of fluoride; 0.1 to 70 wt% of an oxidant; 0.01 to 50 wt% of a buffer composition; 0.00001 to 1 wt% of a silicon inhibitor; 0.0001 to 1 wt% of a silicon germanium etching stabilizer; 0.0001 to 20 weight percent of a defoaming agent; and the balance of water. The inventive compositions are useful for selectively removing silicon germanium relative to silicon from microelectronic devices having silicon and silicon germanium stacks thereon during fabrication of the microelectronic devices.

The present invention discloses a method and structure for integrating CMOS and self-aligned silicon-germanium (SGe) HBTs. The method comprises: forming multiple shallow trench isolation regions on a silicon substrate; forming polysilicon gates, gate silicon oxide, and lightly doped regions in the CMOS active region; opening a base window in the HBT region and forming a selective ion implantation region; forming a SiGe base region; forming a sacrificial emitter region; etching to expose the surface of the outer region of the SiGe base region and forming an extrinsic base region; forming an emitter window and exposing the SiGe surface of the underlying SiGe base region; forming a silicon emitter region in the emitter window, and photolithographically patterning the emitter region and the extrinsic base region. The present invention utilizes a novel sacrificial emitter process, combined with a method for self-aligning the raised extrinsic base region and the emitter region, effectively reducing process complexity and making the device process compatible with standard CMOS and other passive device processes.

An etching composition that includes a quaternary ammonium salt having 8 or more carbon atoms and selectively dissolves silicon over silicon germanium, and may further include a chelating agent, an etching method comprising etching a structure that contains silicon and silicon germanium by using the etching composition, a method for manufacturing a semiconductor device, and a method for manufacturing a gate-all-around-type transistor using the etching composition.

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source / drain (S / D) regions on the first and second fin structures, respectively, forming first and second oxidation stop layers on the n- and p-type S / D regions, respectively, epitaxially growing first and second semiconductor layers on the first and second oxidation stop layers, respectively, converting the first and second semiconductor layers into first and second semiconductor oxide layers, respectively, forming a first silicide-germanide layer on the p-type S / D region, and forming a second silicide-germanide layer on the first silicide-germanide layer and on the n-type S / D region.

The invention provides a semiconductor manufacturing method, which comprises providing a substrate, forming a silicon germanium epitaxial layer in the substrate, forming a first silicon layer on the silicon germanium epitaxial layer, wherein the first silicon layer is a pure silicon layer, and forming a second silicon layer on the first silicon layer, wherein the second silicon layer comprises a silicon layer doped with boron atoms.

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, the semiconductor substrate comprises a first region and a second region, a silicon layer is formed on the surface of the semiconductor substrate in the first region, a silicon germanium layer is formed on the surface of the semiconductor substrate in the second region, and the silicon germanium layer is formed on the surface of the semiconductor substrate in the second region. The surface of the silicon layer is flush with the surface of the silicon germanium layer; and the fins are respectively located in the first region and the second region, the heights of the fins in the first region and the second region are the same, the fin in the first region is composed of a part of the semiconductor substrate and the silicon layer, and the fin in the second region is composed of a part of the semiconductor substrate and the silicon germanium layer. According to the semiconductor structure and the forming method thereof, the depths of the silicon fins and the silicon germanium fins can be consistent, and the defects of fin merging, fin bending and the like caused by the fact that the silicon germanium fins are too deep are avoided.

A method of selectively etching silicon germanium with respect to silicon in a stack located on a chuck in an etch chamber is provided. The chuck is maintained at a temperature of 15 DEG C or less. The stack is exposed to an etch gas comprising a fluorine-containing gas to selectively etch the silicon germanium with respect to silicon.

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region, the second region including a first edge region and a middle region; forming a first edge trench in the first edge region, the first edge trench having a first aspect ratio; filling a first edge layer in the first edge trench; forming a middle trench in the middle region; removing the first edge layer to form an epitaxial trench, the epitaxial trench having a second aspect ratio, the first aspect ratio being greater than the second aspect ratio; and forming an epitaxial layer in the epitaxial trench. Since the first aspect ratio of the first edge trench is high, a round corner span at a bottom of the first edge trench is small, and thus a round corner at a bottom of the epitaxial trench is small. In this way, after a patterning process, a portion of a first fin portion is doped with material of the epitaxial layer, and a portion of a second fin portion has less silicon germanium material, thereby affecting performance of the semiconductor structure formed finally.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

The present invention relates to a monolithic integrated high-speed modulation silicon-based optical chip and a preparation method thereof, which comprises, from bottom to top, a silicon-based optoelectronic layer (I), an intermediate layer (II), a lithium niobate layer or a lithium tantalate layer (III); the silicon-based optoelectronic layer (I) comprises, from bottom to top, a substrate (1), an insulating layer (2), a silicon waveguide (3), an InP laser (4), a silicon germanium photodetector (5), and a thermo-optical phase shifter (6). Based on the excellent electro-optical modulation performance of lithium niobate (or lithium tantalate), the present invention focuses on a special bonding method and a CMOS-compatible silicon photonic flow-through process, obtains a lithium niobate (or lithium tantalate)-silicon multilayer structure, and further realizes a fully integrated transceiver optical chip with a laser, a photodetector, and an electro-optical modulator, which can meet the current requirements of on-chip optical systems for high compactness and low power consumption.

An etchant composition for etching a silicon germanium film includes, based on a total weight of the etchant composition, about 5 wt % to about 14 wt % of an oxidant, about 0.01 wt % to about 5 wt % of a fluorine compound, about 0.01 wt % to about 5 wt % of an amine compound, about 0.01 wt % to about 1 wt % of an alcohol compound having a hydrophilic head and a hydrophobic tail, about 60 wt % to about 90 wt % of an organic solvent, and a balance of water. A method of manufacturing an integrated circuit device includes: forming, on a substrate, a structure in which a plurality of silicon films and a plurality of silicon germanium films are alternately stacked; and selectively removing the plurality of silicon germanium films by using the etchant composition.

An integrated circuit device includes a p-type field effect transistor that includes a strained channel, the strained channel comprising a silicon channel and silicon germanium cladding layers on opposing surfaces thereof, the silicon germanium cladding layers abutting the silicon channel without being grown therefrom.

Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a carbon-doped silicon-germanium and silicon mini-stack is produced with relatively low defects or crystal imperfections. A multi-layered epitaxial stack containing a plurality of the carbon-doped silicon-germanium and silicon mini-stacks is deposited on a substrate. Each multi-layered epitaxial stack contains a carbon-doped silicon germanium stack and a silicon film. The carbon-doped silicon germanium stack contains a carbon-silicon-germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. The silicon film contains the silicon bulk layer disposed on the silicon seed layer. In some embodiments, a method for fabricating the epitaxial film stack includes sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form the carbon-doped silicon-germanium and silicon mini-stack during a deposition cycle.

Methods of reducing wafer bowing in 3D DRAM devices are described using stacks including one or more of epitaxial silicon (Si), carbon doped silicon (SiC), silicon germanium (SiGe), and carbon-doped silicon germanium (SiGeC). A plurality of film stacks is formed on a substrate surface, each of the film stacks comprises two doped silicon layers having different dopant amounts and a sacrificial layer that may be doped or undoped. 3D DRAM devices are also described.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.