137 results about "Silicon-germanium" patented technology

Semiconductor devices (e.g., gate-all-around (GAA) devices), processing tools for fabricating GAA devices, methods for fabricating GAA devices, and internal spacer liners and internal spacers for GAA devices are described. The methods include forming an internal spacer liner within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) arranged alternately in a plurality of stacked pairs. The internal spacer liner includes a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner can be doped with a dopant (e.g., with a p-type dopant or an n-type dopant). One or more steps of the methods described herein are performed in situ in an integrated processing tool system.

An etching composition that includes a quaternary ammonium salt having 8 or more carbon atoms and selectively dissolves silicon over silicon germanium, and may further include a chelating agent, an etching method comprising etching a structure that contains silicon and silicon germanium by using the etching composition, a method for manufacturing a semiconductor device, and a method for manufacturing a gate-all-around-type transistor using the etching composition.

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region, the second region including a first edge region and a middle region; forming a first edge trench in the first edge region, the first edge trench having a first aspect ratio; filling a first edge layer in the first edge trench; forming a middle trench in the middle region; removing the first edge layer to form an epitaxial trench, the epitaxial trench having a second aspect ratio, the first aspect ratio being greater than the second aspect ratio; and forming an epitaxial layer in the epitaxial trench. Since the first aspect ratio of the first edge trench is high, a round corner span at a bottom of the first edge trench is small, and thus a round corner at a bottom of the epitaxial trench is small. In this way, after a patterning process, a portion of a first fin portion is doped with material of the epitaxial layer, and a portion of a second fin portion has less silicon germanium material, thereby affecting performance of the semiconductor structure formed finally.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

Methods of reducing wafer bowing in 3D DRAM devices are described using stacks including one or more of epitaxial silicon (Si), carbon doped silicon (SiC), silicon germanium (SiGe), and carbon-doped silicon germanium (SiGeC). A plurality of film stacks is formed on a substrate surface, each of the film stacks comprises two doped silicon layers having different dopant amounts and a sacrificial layer that may be doped or undoped. 3D DRAM devices are also described.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

This invention relates to a composition and its application for the selective removal of silicon-germanium from silicon-germanium / silicon stacks in microelectronic devices. The composition comprises the following components in weight fractions: 0.0001-10 wt% polyalkyleneimide; 0.001-10 wt% fluoride; 0.1-70 wt% oxidant; 0.01-50 wt% buffer composition; 0.00001-1 wt% silicon inhibitor; 0.0001-1 wt% silicon-germanium etching stabilizer; 0.0001-20 wt% defoamer; and the balance being water. The composition of this invention can be used to selectively remove silicon-germanium from microelectronic devices having silicon and silicon-germanium stacks thereon during the manufacture of microelectronic devices.

The application provides a semiconductor structure manufacturing method, which comprises the following steps: providing a substrate; forming a first electrode layer on one side of the substrate; forming a dielectric layer on the surface of the first electrode layer far from the substrate; forming a second electrode layer on the surface of the dielectric layer far from the first electrode layer; performing chlorine removal pretreatment on the second electrode layer; and forming a third electrode layer on the surface of the second electrode layer far from the dielectric layer. The method solves the problem that chlorine ions at the junction of a silicon germanium layer in the prior art affect the interface reliability.

Executable processing methods can produce semiconductor structures that can include high-k dielectric materials. A method can include forming a silicon layer over a semiconductor substrate. The semiconductor substrate can include silicon germanium. The method can include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate to form a sacrificial oxide. The method can include removing the sacrificial oxide. The method can include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The method can include forming a high-k dielectric material overlying the oxygen-containing material.

A method for forming a doped layer is disclosed. The doped layer can be used in NMOS or silicon germanium applications. For example, a halide precursor can be used to create a doped layer in an n-type dopant application.

The present invention relates to the use of a composition for selectively etching a silicon layer in the presence of a layer comprising a silicon germanium alloy, the composition comprising: (a) 0.1% to 5% by weight of a pyridine having the formula (E1) wherein RE1 is a substituent selected from the group consisting of-(XE3) s-COORE2,-(XE3) s-OH,-(XE3) s-NH2,-(XE3) s-CONH2 and-(XE3) s-CN; m is the number of substituents RE1 and is 1 or 2; xE3 is a C1 to C4 alkanediyl group; rE2 is H or a C1 to C4 alkyl group; and s is 0 or 1; rE1 must not be in position 2 except if m is 1 and RE1 is-(XE3) s-NH2; (b) 0.1% to 10% by weight of an amine having the formula (E2) if RE1 is-(XE3) s-COOH wherein XE1, XE2 are independently selected from C2-C3 alkanediyl; yE is selected from NH2 and OH; n is 0, 1, 2 or 3; and (c) water. (E1) (E2)

The application discloses a space correlation disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment, and belongs to the technical field of electronic equipment heat dissipation, in particular to a thermoelectric refrigeration system based on space correlation disordered silicon germanium (SiGe) nanowire. The system comprises a hot end 1, a cold end 6 and a thermoelectric conversion module. The thermoelectric material layer 4 is used for responding to direct current provided by the power driving circuit 5, generating a temperature difference between two ends to enhance the refrigeration effect. The thermoelectric material layer 4 is also used for adjusting the temperature difference between two ends of the thermoelectric material layer 4 by adjusting the current value of the direct current provided by the power driving circuit 5, and then adjusting the temperature difference between the hot end 1 and the cold end 6. The space correlation disordered silicon germanium nanowire thermoelectric refrigeration system for electronic equipment is suitable for heat dissipation of electronic equipment.

Embodiments utilize a silicon germanium layer deposited to a low germanium percentage under a substrate. The substrate is used to form a field effect transistor FET structure. After formation of the FET, the silicon germanium layer is oxidized to drive germanium to a concentrated sublayer of the silicon germanium layer. The sublayer is used as a stop layer to remove the oxidized portion of the silicon germanium layer.

A semiconductor device is provided. The semiconductor device includes a substrate, a gate stack layer formed over the substrate, a silicon germanium (SiGe) channel layer formed in the substrate and covered by the gate stack layer, first and second source / drain (S / D) regions, and first and second lightly doped drain (LDD) layers. The first and second S / D regions are formed in the substrate on a first side and a second side opposite to the first side of the gate stack layer, respectively. The first LDD layer is disposed between the SiGe channel layer and the first S / D region, and the second LDD layer is disposed between the SiGe channel layer and the second S / D region. The first and second LDD layers include SiGe materials.

The application provides a back contact structure of a laminated battery, a preparation method of the back contact structure and a photovoltaic cell. The back contact structure of the laminated battery comprises a tunneling oxide layer, a silicon germanium crystallization layer, an amorphous silicon buffer layer and a polycrystalline silicon transfer layer which are sequentially stacked. The content of germanium in the silicon germanium crystallization layer increases from the tunneling oxide layer to the amorphous silicon buffer layer. The lattice constant of the silicon germanium crystallization layer changes in a gradient from the tunneling oxide layer to the amorphous silicon buffer layer. The application effectively reduces the lattice mismatch degree and improves the battery conversion efficiency by optimizing the carrier transfer and interface characteristics.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device for reducing on-resistance and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate, a drift region, a source region, a drain region and a gate structure, wherein the drift region, the source region and the drain region are formed in the semiconductor substrate. The key point is that a high carrier mobility layer is formed in the drift region, and the layer forms a part of a conductive path between the channel and the drain region. The high carrier mobility layer can be a selective epitaxial growth silicon germanium layer, and can also be a germanium-containing layer formed by ion implantation. By introducing the high mobility layer, the migration rate of carriers in the drift region is remarkably improved, the drift region resistance and the total on-resistance of the device are effectively reduced, and meanwhile, the influence on the breakdown voltage is small. According to the LDMOS device, the restrictive relation between the on-resistance and the breakdown voltage in a traditional LDMOS device is broken, low on-resistance and high breakdown voltage are achieved at the same time, and the power efficiency and the overall performance of the device are improved.

A semiconductor structure and a manufacturing method for a semiconductor structure. The semiconductor structure comprises: a substrate (10); a capacitor structure (107) located on the substrate (10), the capacitor structure (107) comprising a first electrode layer (1071), a capacitor dielectric layer (1072), and a second electrode layer (1073) which are sequentially stacked; a conductive plate (108) located on the surface of the second electrode layer (1073), the conductive plate (108) at least comprising a base layer and a first transition layer (1082) located on the surface of the base layer; and a contact member (109) inserted into the conductive plate (108), the contact member (109) being electrically connected to the second electrode layer (1073) by means of the conductive plate (108). The base layer comprises a first silicon germanium layer (1081), and the first transition layer (1082) comprises a first boron-doped polycrystalline silicon layer (1082b) and a second silicon germanium layer (1082a) arranged in a stack. The semiconductor structure has high reliability and stability.

The application relates to a high-temperature waste heat recovery system based on spatially correlated disordered silicon germanium nanowires, belonging to the technical field of thermoelectricity, and particularly relates to high-temperature waste heat recovery in industrial production processes. The system solves the problem that the existing silicon germanium nanowires still have limitations in the reduction of thermal conductivity and are difficult to meet the demand of efficient thermoelectric conversion. The system comprises a thermoelectric conversion module, a cold source area and an electric energy output module. The thermoelectric material layer is used for responding to the temperature difference between the heat source area and the cold source area, generating a thermoelectric effect to generate an electric current. The high-temperature waste heat recovery system based on spatially correlated disordered silicon germanium nanowires is suitable for high-temperature waste heat recovery in industrial production processes.

A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein each fin of the plurality of fins includes silicon germanium. A layer of silicon germanium oxide is deposited on the plurality of fins, and a first thermal annealing process is performed to convert outer regions of the plurality of fins into a plurality of silicon portions. Each silicon portion of the plurality of silicon portions is formed on a silicon germanium core portion. The method further includes forming a plurality of source / drain regions on the substrate, and depositing a layer of germanium oxide on the plurality of source / drain regions. A second thermal annealing process is performed to convert outer regions of the plurality of source / drain regions into a plurality of germanium condensed portions.

Methods for selectively etching SiGe relative to Si are provided. Some of the methods include forming a passivation layer on the surface of a Si layer to enhance SiGe etchant selectivity, and using a halogen intercompound gas that preferentially etches SiGe over Si in the presence of the passivation layer. The methods can be performed in a cyclical manner until a desired thickness of the SiGe layer is obtained.

Circuits and methods for integrated circuits particularly useful in high-quality low-noise amplifiers (LNA) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. LNA embodiments include an N-type MOSFET (NFET) or P-type MOSFET (PFET) device co-fabricated with one or more serially-coupled asymmetric PFET devices of several types. The asymmetry of the novel asymmetric PFET device provides a shorter gate length (LG) and thus a higher transconductance (gm). In addition, the inventive asymmetric PFET device has a higher hole mobility brought about by introducing strain in the conduction channel (especially at or near the source of the device) and / or by use of silicon germanium (SiGe) regions within the asymmetric PFET structure. The resulting asymmetric PFET devices have higher Vtsat and lower built-in voltage Vbi (thus higher IDS) characteristics than conventional symmetric PFET devices.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source / drain regions.

An etchant composition for etching a silicon germanium film is provided, and methods of use thereof, the etchant composition including about 3 wt % to about 90 wt % of an oxidizing agent based on a total amount of an etchant composition, about 0.01 wt % to about 5 wt % of a fluorine compound based on the total amount of the etchant composition, about 0.01 wt % to about 5 wt % of an amine compound based on the total amount of the etchant composition, about 0.01 wt % to about 1 wt % of an inhibitor based on the total amount of the etchant composition, about 1.5 wt % to about 88.5 wt % of an organic solvent based on the total amount of the etchant composition, and a residual amount of water.

The present invention provides an etching composition that suppresses the dissolution of silicon germanium and promotes the dissolution of silicon, exhibiting excellent selective dissolution of silicon to silicon germanium, as well as an etching method using this etching composition, a method for manufacturing a semiconductor device, and a method for manufacturing a gate-all-around type transistor. [Solution] An etching composition that selectively dissolves silicon in silicon germanium, comprising a quaternary ammonium salt (A) having 8 or more carbon atoms. It may further contain a chelating agent (B). An etching method for etching a structure containing silicon and silicon germanium using this etching composition.

The method of manufacturing a semiconductor device includes: forming a fin including first sacrificial layers and channel layers alternately stacked, and second and third sacrificial layers alternately stacked; a material of one of the second and third sacrificial layers including silicon or silicon germanium, and a material of the other one including silicon germanium or germanium; a difference in germanium content between the second and third sacrificial layers being less than 15%, and the second sacrificial layer being doped with an etching auxiliary agent; forming a mask straddling the fin; selectively removing the second sacrificial layers under an accelerated etching effect of the etching auxiliary agent to form a first dielectric filling region; forming first middle dielectric isolation layers in the first dielectric filling region; and removing the first sacrificial layers, the channel layers, the first middle dielectric isolation layers, and the third sacrificial layer not covered by the mask.

The invention provides a semiconductor device and a manufacturing method thereof. A substrate is provided. At least one silicon layer is formed on top of a substrate. At least one silicon germanium layer is formed on top of the at least one silicon layer. The at least one silicon germanium layer includes at least one n-type dopant. A semiconductor device having at least one silicon layer and at least one silicon germanium layer is formed.

A semiconductor device including a substrate, a first and second active pattern extending in a first horizontal direction on the substrate, the second active pattern apart from the first active pattern in the first horizontal direction, first nanosheets apart from each other in a vertical direction on the first active pattern, second nanosheets apart from each other in the vertical direction on the first and second active patterns, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the first active pattern and surrounding the first nanosheets, a source / drain region between the first and second nanosheets, an active cut penetrating the second nanosheets in the vertical direction, extending to the substrate, and separating the first and second active patterns, and a sacrificial layer between the source / drain region and the active cut, in contact with the active cut, and including silicon germanium may be provided.

Described herein is a method of using a composition for selectively etching a silicon layer in the presence of a layer including a silicon germanium alloy, the composition including: (a) 4 to 15% by weight of an amine of formula (E1), and (b) water, where XE1, XE2, and XE3 are independently selected from a chemical bond and C1-C6 alkanediyl; YE is selected from N, CRE1, and P; RE1 is selected from H and C1-C6 alkyl.

The present invention provides chemical solution which is capable of selectively removing a silicon germanium-containing material having a high germanium concentration from an object to be treated containing two kinds of silicon germanium-containing materials that have different compositions. The present invention also provides a method for treating an object to be treated and a method for manufacturing a semiconductor device using the chemical solution.　Chemical solution according to the present invention is used for an object to be treated containing two silicon-germanium-containing materials that have different germanium concentrations, and removes at least a portion of one of the silicon-germanium-containing materials that has a high germanium concentration. This chemical solution contains a fluoride ion source, an oxidizing agent, a specific unsaturated compound that has a double bond or a triple bond, and water.