35 results about "Carrier scattering" patented technology

The invention discloses a double-gate graphene transistor with aluminum oxide as gate dielectric and a manufacturing method thereof. The double-gate graphene transistor with the aluminum oxide as the gate dielectric mainly solves the problems of reduction of carrier mobility and carrier scattering in a graphene channel due to top grate dielectric of a graphene transistor in the manufacturing process in the prior art. The double-gate graphene transistor is structurally characterized in that two gate electrodes are arranged on the two sides of the graphene channel respectively to form a double-gate structure. The manufacturing method includes the first step of depositing a layer of aluminum oxide on the surface of a washed silicon carbide sample wafer and etching out a structural graph on the aluminum oxide layer, the second step of placing the etched sample wafer into a quartz tube, feeding carbon tetrachloride to react with silicon carbide to generate a carbon film, then placing the sample wafer into argon to carry out annealing to generate graphene and carrying out etching on the portions, 60-400 nanometers away from the two sides of the graphene channel, of the aluminum oxide layer to form gate grooves, and the third step of depositing metal on the sample wafer and etching the sample wafer to form a metal contact layer of the transistor. The double-gate graphene transistor manufactured through the method is capable of effectively improving the carrier mobility ratio and the modulation capacity of the gate electrodes on the channel current.

The invention discloses a germanium channel quantum well field effect transistor with a low power consumption and a high performance. The germanium channel quantum well field effect transistor comprises a semiconductor germanium substrate; the semiconductor germanium substrate is provided with a source end injection region and a drain end injection region; a two-dimensional material passivation layer, a gate insulation layer and a grid electrode are covered on a surface of the semiconductor germanium substrate in sequence; and each of the source end injection region and the drain end injection region is provided with an N+ active injection region or a P+ active injection region. When the quantum well transistor having above structure is in work, a working current larger than the traditional germanium-based metal oxide semiconductor field effect transistor can be obtained; when the number of layers of a two-dimensional material in a grid laminated layer is reduced, an energy band structure is changed, so a relative position deviation between the energy band structure corresponding to the special number of the layers and the energy band structure of germanium enables a germanium channel to form a quantum well; and therefore, the transportation space for two carriers, namely electron and hole, can be effectively limited, the influence of carrier scattering on migration rate is reduced, the working current of a device is improved, and the P type and N type transistors with the low power consumption and the high performance are realized.