35 results about "Carrier scattering" patented technology

The invention provides a FinFET structure and a manufacturing method of the FinFET structure. According to the manufacturing method of the FinFET structure, a fin-shaped channel region shaped like a triangular prism is adopted to replace a fin-shaped channel region shaped like a cuboid, two protruding faces of the FinFET structure form opposite crystal face crystal orientation structures, the scattering effect of carriers is reduced, the charge storage capacity is improved, the structure that the fin-shaped channel region is used up is formed more easily when the FinFET structure is controlled by a grid electrode, the conductive path of channels is thoroughly cut off, and therefore the driving current of an FinFET element is improved. The FinFET structure and the manufacturing method of the FinFET structure are suitable for manufacturing the FinFET element of smaller size and with higher drive current.

The invention provides a GaN-based PN diode and a preparation method thereof. The GaN-based PN diode sequentially comprises a highly-doped n+ type GaN substrate 1, a non-doped GaN layer 2, a p type AlGaN layer 3 and a p type AlGaN gradient structure 4 from bottom to top, wherein the molar content of an Al component in the p type AlGaN layer 3 is 0.2-0.4 of the sum of the Al component and a Ga component; and in the p-type AlGaN gradual change structure 4, the Al component is gradually reduced from bottom to top, and the reduction gradient is gradually increased until the top of the p-type AlGaNgradual change structure is a GaN layer. Because of the polarization effect of the gradient structure, fixed negative polarization charges are introduced to induce generation of free holes, the doping efficiency is improved, the carrier scattering probability can be reduced and the carrier mobility is improved while high hole concentration is realized at relatively low doping concentration, so that the PN diode can obtain high-quality P-type ohmic contact and higher output current more easily.

The invention discloses a double-gate graphene transistor with aluminum oxide as gate dielectric and a manufacturing method thereof. The double-gate graphene transistor with the aluminum oxide as the gate dielectric mainly solves the problems of reduction of carrier mobility and carrier scattering in a graphene channel due to top grate dielectric of a graphene transistor in the manufacturing process in the prior art. The double-gate graphene transistor is structurally characterized in that two gate electrodes are arranged on the two sides of the graphene channel respectively to form a double-gate structure. The manufacturing method includes the first step of depositing a layer of aluminum oxide on the surface of a washed silicon carbide sample wafer and etching out a structural graph on the aluminum oxide layer, the second step of placing the etched sample wafer into a quartz tube, feeding carbon tetrachloride to react with silicon carbide to generate a carbon film, then placing the sample wafer into argon to carry out annealing to generate graphene and carrying out etching on the portions, 60-400 nanometers away from the two sides of the graphene channel, of the aluminum oxide layer to form gate grooves, and the third step of depositing metal on the sample wafer and etching the sample wafer to form a metal contact layer of the transistor. The double-gate graphene transistor manufactured through the method is capable of effectively improving the carrier mobility ratio and the modulation capacity of the gate electrodes on the channel current.

The invention belongs to the field of two-dimensional material preparing, and particularly discloses a VDW dielectric material and a preparing method and application thereof. The method comprise the following steps that an inorganic molecular crystal serves as an evaporation source, a heat evaporation method is adopted, the inorganic molecular crystal is subjected to sublimation under the high vacuum, meanwhile, a perfect molecular structure of the crystal can be kept, evaporation is carried out, and a VDW film is obtained. Due to the fact that unsaturated chemical bonds do not exist in inorganic molecules, the VDW film surface has no suspension bonds, and preparing of the VDW dielectric material can be finished. The prepared VDW film can serve as a dielectric material of a two-dimensionalmaterial electronic device, the scattering source of carriers in a two-dimensional groove material can be obviously reduced, it is ensured that a two-dimensional material has the high migration rate,meanwhile, a preparing technology and a semiconductor preparing technology are compatible, and scale preparing and integrating are easy.

Flexible, conductive, graphene-polymer nanocomposites incorporating doped graphene and conductive polymer materials in a layered structure and tunable methods of fabrication are provided. The layered graphene-polymer nanocomposites exhibit resistance quenching by suppressing defect induced carrier scattering in graphene while keeping the optical transmittance greater than 90%, which is essential for many optoelectronic applications. Nanocomposites also demonstrate high mobility and carrier density compared to known TCF materials as well as very low sheet resistance with flexibility of more than ±90 degrees of bending angle. The methods employ layer-by-layer mixed chemical doping strategies that incorporate different doping species to enhance electrical and optical properties individually. The synthesis of the graphene-polymer nanocomposite may be conducted by chemical processes to provide mass production capabilities.

The invention provides a fast recovery diode (FRD) device structure and a manufacturing method thereof. An insulation layer is formed on the side wall of a trench of the FRD device structure, and the insulation layer is combined with the surface of a P-type doped region to form a combining center, so that a combining route from the P-type doped region to the insulation layer is formed, and the reverse recovery characteristic of the device is improved effectively; furthermore, due to the presence of the insulation layer on the side wall of the trench, partial combined current carriers which reach the upper surface of the P-type doped region from the P-type doped region through the combining route are shielded by the insulation layer and combined on the surface of the insulation layer, so that the emission efficiency is improved and the state voltage drop is reduced; moreover, the doping concentration at the bottom of the trench in the P-type doped region is controlled, so that the diffusion length of the current carriers is prevented from being dramatically reduced, the scattering of the current carriers and an auger combining effect are avoided, the emission efficiency of the bottom region of the trench in the P-type doped region is improved, the rising of the state voltage drop of the trench caused by doping reduction is compensated, and the forward voltage drop is improved.

The invention discloses a germanium channel quantum well field effect transistor with a low power consumption and a high performance. The germanium channel quantum well field effect transistor comprises a semiconductor germanium substrate; the semiconductor germanium substrate is provided with a source end injection region and a drain end injection region; a two-dimensional material passivation layer, a gate insulation layer and a grid electrode are covered on a surface of the semiconductor germanium substrate in sequence; and each of the source end injection region and the drain end injection region is provided with an N+ active injection region or a P+ active injection region. When the quantum well transistor having above structure is in work, a working current larger than the traditional germanium-based metal oxide semiconductor field effect transistor can be obtained; when the number of layers of a two-dimensional material in a grid laminated layer is reduced, an energy band structure is changed, so a relative position deviation between the energy band structure corresponding to the special number of the layers and the energy band structure of germanium enables a germanium channel to form a quantum well; and therefore, the transportation space for two carriers, namely electron and hole, can be effectively limited, the influence of carrier scattering on migration rate is reduced, the working current of a device is improved, and the P type and N type transistors with the low power consumption and the high performance are realized.

The invention discloses a preparation method based on Ni membrane annealing for a SiC substrate side grid graphene transistor and mainly solves the problems of low graphene channel carrier mobility and carrier scattering caused by top grid dielectric of a graphene transistor prepared by the prior technology. The preparation method is implemented by the following steps that a SiC sample substrate is cleaned; a SiO2 layer is deposited on the surface of the SiC sample substrate, and a side grid pattern is formed on the SiO2 layer in a photo-etching manner; the photo-etched sample substrate is placed in a quartz tube, and a carbon membrane is generated through the reaction of gaseous CCl4 and SiC; then the sample substrate with the carbon membrane is placed in a buffer hydrofluoric acid solution to remove the SiO2; a Ni membrane is deposited on the carbon membrane of the sample substrate, and the sample substrate is placed in Ar gas for annealing, so graphene of a side grid is generated; and finally, a metal Pd/Au layer is deposited on the graphene sample substrate and is etched to form metal contacts of a side grid transistor. The side grid graphene transistor prepared by the preparation method has high carrier mobility and can effectively restrain the scattering effect, so that the modulation effect of the grid of the graphene transistor on the channel carrier concentration is improved.

The invention discloses a preparation method of amorphous transparent conductive oxide thin film. The preparation method comprises the step of carrying out magnetron sputtering under the room temperature, and further comprises the steps of setting the target power density according to the preset power in the preparation process, and keeping the target power density unchanged; adjusting the magnetic field intensity and the target voltage to obtain the high-energy plasma particles with the energy higher than or equal to 100 eV; making the high-energy plasma particles bombard the surface of a target material to obtain sputtering atoms; making the sputtering atoms deposit on a base to obtain amorphous transparent conductive oxide thin film according to the preset deposition speed; and carryingout low-temperature annealing treatment on the amorphous transparent conductive oxide thin film. According to the preparation method of amorphous transparent conductive oxide thin film, grain boundary scattering, ionized impurity scattering and carrier scattering are greatly reduced, the influence caused by grain boundary scattering, ionized impurity scattering and carrier scattering to carrier mobility in amorphous transparent conductive oxide thin film obtained in the prior art is eliminated, and then, the purpose that the carrier mobility of TCO thin film is effectively improved on the premise that energy consumption is low is achieved.

The invention discloses lead-free perovskite Cs2AgBiBr6, a preparation method of the lead-free perovskite Cs2AgBiBr6 and a method for obtaining a diffusion coefficient of the lead-free perovskite Cs2AgBiBr6, and belongs to the field of material luminescence. And the lead-free perovskite Cs2AgBiBr6 is synthesized by adopting a crystallization method. Fluorescence imaging light spots of the lead-free perovskite Cs2AgBiBr6 are collected under low energy, the light spots at different moments are extracted, then normalization is carried out with the light spot intensity at the zero moment as the benchmark, and it can be clearly seen that the diameter of the light spots is increased, so that the light spots are more uniform. According to direct evidence, the diffusion process of the lead-free perovskite Cs2AgBiBr6 is observed. The diffusion coefficient D of the Cs2AgBiBr6 is obtained through Gaussian fitting of the fluorescence intensity, and the mobility of the Cs2AgBiBr6 is obtained through conversion. Through fitting of diffusion coefficients D at different temperatures, it is obtained that carrier scattering of the Cs2AgBiBr6 is in an optical wave scattering mode, and guiding significance is provided for research and development of lead-free perovskite.

The invention relates to a method for forming a semiconductor device, comprising the following steps: providing a semiconductor substrate; carrying out first ion doping and second ion doping to form a well region and a threshold voltage regulation region disposed in the semiconductor substrate, wherein the threshold voltage regulation region is disposed on the surface of the well region; forming a semiconductor epitaxial layer on the surface of the semiconductor substrate after the formation of the well region and the threshold voltage regulation region; and forming a transistor on the surface of the semiconductor epitaxial layer, wherein the channel region of the transistor is formed by the semiconductor epitaxial layer. According to the method for forming a semiconductor device, the semiconductor epitaxial layer, as the channel region of the transistor, avoids lattice damage caused by ion doping. Moreover, the semiconductor epitaxial layer used for forming the channel region is not doped or is lightly doped with boron. Thus, carrier scattering is reduced, the carrier migration rate of the transistor is high, and the device performance is superior.

A nickel-doped copper oxide thin film transistor and a preparation method thereof are disclosed. A precursor solution is prepared, the precursor solution is spin-coated on a heavily doped silicon wafer to form a nickel-doped copper oxide film, a metal source and a drain electrode are prepared on the nickel-doped copper oxide film by using a mask plate, and the preparation of a back gate structuretransistor, i. e., a p-type thin film transistor, is completed. The performance of the back gate structure transistor is obviously improved compared with that of the copper oxide thin film transistor.The nickel-doped copper oxide thin film prepared by the invention has the beneficial effects of high quality of the thin film, reduced carrier scattering, high hole transmission capability and low hole scattering, so that the quality of the contact interface between the thin film and the dielectric layer and the electrode is improved, and the purpose of improving the mobility of the thin film transistor is achieved.

It is an object of the present invention to provide a ferrite carrier core material and a ferrite carrier for an electrophotographic developer, which have an excellent charging property, hardly cause carrier scattering due to cracking and chipping of the core material, and have a prolonged life, and methods for manufacturing these, and an electrophotographic developer using the ferrite carrier. For this object, the ferrite carrier core material and a ferrite carrier for an electrophotographic developer, wherein (1) the ferrite composition contains 0.5 to 2.5% by weight of Sr, and the presence amount of Sr—Fe oxides satisfies a specific conditional expression, (2) the distribution in the number of the shape factor SF-2 is in a specific range, (3) the BET specific surface area is 0.15 to 0.30 m²/g, (4) the average particle diameter D₅₀ is 20 to 35 μm, and (5) the magnetization is 50 to 65 Am²/kg.