50results about How to "Improved reverse recovery characteristics" patented technology

The invention discloses a method for manufacturing a planar high-voltage ultrafast soft recovery diode. The method comprises the following steps of: oxidizing, and photoetching to form an active region and a field limiting ring; doping and pushing; manufacturing a polycrystalline silicon field plate; performing platinum diffusion; thinning; forming an N-type buffer layer; performing contact doping and annealing; and metalizing. The method can be used for manufacturing an ultrafast soft recovery diode chip which is low in cost and short in recovery time and has high-voltage resistance, low leakage current, low forward voltage drop and soft recovery characteristics.

The invention discloses a groove gate VDMOS device integrated with a Schottky diode and belongs to the technical field of semiconductor devices. According to the groove gate VDMOS device integrated with the Schottky diode, an additional structure composed of a piece of Schottky junction metal and a body electrode conductive material is additionally arranged on each of drift regions on the two sides of a groove gate structure of a conventional groove gate VDMOS device, the upper portion of each piece of Schottky junction metal is in contact with source electrode metal, the lower portion of each piece of Schottky junction metal is in contact with a corresponding body electrode conductive material, and the lower surface and the lateral sides of the each piece Schottky junction metal are in contact with a corresponding drift region to form a Schottky junction; dielectric layers are arranged between the lateral sides of each body electrode conductive material and a corresponding drift region and between the bottom surface of each body electrode conductive material and the corresponding drift region. Compared with a traditional groove gate VDMOS device with the same size, the groove gate VDMOS device integrated with the Schottky diode has the advantages that due to the fact that higher drift region dosage concentration is adopted under the condition of same puncture voltage, turn-on resistance is reduced obviously, and the reverse recovery property of the diode is improved obviously.

The invention belongs to the technical field of power semiconductor devices, and particularly relates to a reverse trench gate charge storage-type insulated gate bipolar transistor. Double split electrodes which are equal to an emitter in potential and dielectric layers between the double split electrodes and a gate electrode are introduced into the bottom part and the side surface of the gate electrode in a trench of an RC-IGBT device, so that the switching speed of the device in the IGBT working mode is improved; the carrier concentration distribution of the whole N-type drift region is improved; the switching loss of the device is reduced; the saturated current density of the device is reduced; the short-circuit safe operation area of the device is improved; the reliability is improved; a reverse free-wheeling diode has a low diode conduction voltage drop in a reverse free-wheeling diode working mode; the reverse recovery characteristics of the free-wheeling diode are improved; and meanwhile, the manufacturing method of the double split trench gate charge storage-type IGBT does not need to increase an extra processing step and is compatible with a traditional RC-IGBT manufacturing method.

The invention discloses a system for preventing reverse recovered charges in a DUT. The system is a current injection circuit connected to the two ends of the DUT in a forward bias mode. The injected current circuit comprises a pulse nS-level pulse signal generator formed by an SRD and a pulse edge acceleration circuit formed by a BG2 and a BG1, wherein the pulse edge acceleration circuit is tightly connected with the back of the pulse nS-level pulse signal generator and used for shortening the rising edge time and the falling edge time of pulses. The system has the advantages that the reverse recovered features of the DUT can be improved, the reverse recovered charges can be reduced, and the reverse recovered time can be shortened; meanwhile, switching losses and conduction losses of the DUT can be reduced, electromagnetic interference and surges can be restrained, and efficiency is improved.

The invention belongs to the technical field of a power semiconductor device, in particular relates to a reverse-conducting trench gate charge storage insulated-gate bipolar transistor (IGBT). By introducing a side-surfaces split electrode connected with an emitter into a trench on the condition of a certain device trench depth and a certain trench metal oxide semiconductor (MOS) structure density, the gate capacitance of the device is reduced, the switching speed of the device is increased, the switching loss is reduced, and the positive conduction voltage drop and the average switching loss are improved; meanwhile, the density of an MOS channel is reduced, the short-circuit safety working region of the IGBT is improved, and the performance and the reliability of the device are improved; and a reverse freewheeling diode works in multiple submodes in a working mode of the reverse freewheeling diode, the IGBG has low diode conduction voltage drop, and the reverse recovery characteristic of the freewheeling diode is improved.

The invention provides a manufacturing method of a high-voltage quick-recovery diode, and the method comprises following steps of simultaneously implementing P-type impurity doping of an anode area and a terminal field limiting ring on the front surface of an N-type monocrystalline silicon sheet which is uniformly doped through field oxidation and ion injection; adopting a diffusion method to simultaneously implement the N-type impurity doping of a silicon sheet front surface groove interception ring and a silicon-sheet back surface cathode area after the anode area and the terminal field limiting ring area are protected by an oxidation film; implementing the heat diffusion propulsion simultaneously for the P-type impurities and N-type impurities in a high-temperature diffusion furnace; and implementing the back surface metallization after completing the front surface metallization, electron radiation minority carrier lifetime control and removal of a back surface damaged layer. According to the method, the machining steps are simple, and a deep N-type doped layer on the back surface of the silicon sheet is favorable for improving the reverse recovery characteristic of the diode and improving the blocking voltage.

The invention relates to a novel method for achieving a Split Well structure in the design of an ultrahigh-density groove-type power device, and is effective in solving the problem that the Split Well structure (21) is incompatible with the ultrahigh-density design. Based on the impurity compensation theory, the method is characterized in that the high-energy N-type ion injection (18) and the quick annealing are carried out through a contact hole (22) so as to ensure that the Split Well structure (21) is formed at the bottom part in the middle of a well area (7). With the contact hole (22) over-etched below a silicon surface (23), the process ensures that the energy demand for sequential N-type ion injections is effectively reduced, thereby reducing the probability of injection damage to the well area (7) with less leakage sources that cause current to leak out from the device. Moreover, a higher integrated level can be attained with the Split Well structure 21 achieved in Z direction. The novel Split Well technology leads to a substantial improvement on the design of the device which ensures the long-standing reliability of the device as well as the workability of the on-resistance of the device, the firmness of the device and the reverse recovery characteristic of the body diode of the device.

The invention discloses a method and an apparatus for optimizing reverse recovery characteristic of a body diode. Processing is preformed for a COOLMOS device, wherein a drain region is formed at the bottom of the COOLMOS device; and the doping concentration of an n heavily doped region is higher than that of an n doped substrate region. By forming the n type heavy doping to partial regions on the back surface of the device after the device is thinned, a partial buffer layer structure can be formed, so that the reverse recovery softness of the body diode is improved and reverse voltage conversion rate (dv/dt) is lowered, thereby optimizing the reverse recovery characteristic of the body diode.

A super junction power device disclosed by the invention comprises a substrate epitaxial layer of a first doping type, body regions of a second doping type, and JFET regions. The substrate epitaxial layer is internally provided with a drain region of the first doping type and a plurality of sidewall-sloped columnar epitaxial doped regions of the second doping type. The body regions are respectively arranged on the top ends of the columnar epitaxial doped regions, and each body region is internally provided with source regions of the first doping type. Each JFET region is disposed between every two adjacent body regions. A gate oxide layer is arranged on the body regions and the JFET regions. Gates are arranged on the gate oxide layer. Compensation injection regions are arranged in the substrate epitaxial layer at the two sides of the sidewalls and at the bottom of the columnar epitaxial doped regions. The breakdown voltage is increased and the reverse recovery characteristic is improved under the condition that the on resistance of the super junction power device is basically unchanged. The manufacturing process is simple and easy to implement.

The invention provides a fast recovery diode (FRD) device structure and a manufacturing method thereof. An insulation layer is formed on the side wall of a trench of the FRD device structure, and the insulation layer is combined with the surface of a P-type doped region to form a combining center, so that a combining route from the P-type doped region to the insulation layer is formed, and the reverse recovery characteristic of the device is improved effectively; furthermore, due to the presence of the insulation layer on the side wall of the trench, partial combined current carriers which reach the upper surface of the P-type doped region from the P-type doped region through the combining route are shielded by the insulation layer and combined on the surface of the insulation layer, so that the emission efficiency is improved and the state voltage drop is reduced; moreover, the doping concentration at the bottom of the trench in the P-type doped region is controlled, so that the diffusion length of the current carriers is prevented from being dramatically reduced, the scattering of the current carriers and an auger combining effect are avoided, the emission efficiency of the bottom region of the trench in the P-type doped region is improved, the rising of the state voltage drop of the trench caused by doping reduction is compensated, and the forward voltage drop is improved.

The invention discloses a diode device and a manufacturing method thereof, and belongs to the technical field of power semiconductor devices. A cellular structure of the device comprises a metal negative electrode, an N+ substrate and an N- epitaxial layer; a trench structure is arranged on the two sides of the top layer of the epitaxial layer; the trench structure comprises a P-type semiconductorregion and a heterogeneous semiconductor from the bottom up; the top layer of the N-epitaxial layer is also provided with a P-type body region, an N+ source region and a P+ contact region; the N+ source region, the P-type body region, a part of the N- epitaxial layer and the heterogeneous semiconductor are in contact through a dielectric layer of the side wall of the trench; the surface of the device is covered with a metal positive electrode; and the heterogeneous semiconductor, the dielectric layer, the source region, the body region and the epitaxial layer form an ultra-potential barrier structure. By virtue of the diode device and the manufacturing method thereof, the problems of high forward opening voltage, poor reverse recovery capability and the like existing in the existing PIN diode device can be solved; and in addition, lower electric leakage and a larger safe working region are achieved on the premise that the withstand voltage is not affected, and the reliability of the device is improved.

The invention discloses a diode and a manufacturing method thereof, and belongs to the technical field of power semiconductor devices. The cellular structure of the device comprises a metal cathode, an N+ substrate, an N- epitaxial layer and a metal anode, wherein groove structures are arranged on two sides of the top layer of the N- epitaxial layer, each groove structure comprises a P+ semiconductor area and a P-type semiconductor Well area from the bottom up, each P-type semiconductor Well area contacts the metal anode thereon, dielectric layers are arranged on the upper surfaces of the partof the P-type semiconductor Well area and the part of the N- semiconductor epitaxial layer; heterogeneous semiconductors are arranged on the upper surfaces of the dielectric layers and the N-semiconductor epitaxial layer; the heterogeneous semiconductors, the dielectric layers, the P-type semiconductor Well area and the N- semiconductor epitaxial layer form a super barrier structure. According tothe diode and the manufacturing method thereof provided by the invention, the traditional PIN device forward opening voltage is significantly reduced without influencing the device performance, the reverse recovery property of the device is optimized, and the good property of compromise between the forward breakover voltage drop and turn-off losses is acquired. In addition, the device provided bythe invention also provides a plurality of working modes for selection, so as to be greatly conveniently used in actual applications.

The invention provides a superjunction device structure and a method for fabricating the same. The superjunction device structure comprises a first conductivity type of semiconductor substrate; a first conductivity type of graded epitaxial layer formed on the semiconductor substrate, composed of a solid solution having more than two components, and having a different lattice constant from the semiconductor substrate, wherein the component ratio of the solid solution varies in the thickness direction of the graded epitaxial layer; and a second conductivity type of pillar structure formed in the graded epitaxial layer and extending in the thickness direction of the epitaxial layer. The lattice defect is uniformly controllable in the thickness direction of the epitaxial layer by growing the graded epitaxial layer in which the solid solution components vary in the thickness direction and which has a different lattice constant from the semiconductor substrate. The reverse recovery characteristic of a device is optimized to realize a purpose of rapidly reducing carriers during the turn-off phase of the device. The superjunction device structure is simple in process, low in cost, and suitable for mass production.

The invention provides a superjunction device structure and a preparation method thereof. The superjunction device structure comprises a first conducting type semiconductor substrate; a first conducting type epitaxial layer arranged on the upper surface of the semiconductor substrate, wherein the epitaxial layer and the semiconductor substrate have different lattice constants; and a second conducting type column structure, which is arranged in the epitaxial layer and extends in the thickness direction of the epitaxial layer. By growing the epitaxial layer with different lattice constants fromthe semiconductor substrates, and introducing uniform controllable defects, probability of carrier recombination is increased and carrier life is reduced to optimize the reverse recovery characteristic of the superjunction power device and realize the purpose of rapid reduction of carriers at the turn-off stage of the device; and the preparation method is simple in preparation process, low in costand suitable for large-scale manufacture.

The invention discloses a super-junction MOSFET device with an improved reverse recovery characteristic, which comprises an N + substrate layer and a plurality of P columns and N columns which are alternately arranged on the N + substrate layer. A drain electrode is arranged at the bottom of the N + substrate layer; the top of the P column and the top of the N column are provided with an N epitaxial layer, the N epitaxial layer is provided with P-type body regions corresponding to the P columns in position and number, the P columns in a partial region in the super-junction MOSFET device body extend upwards to form epitaxial P columns, and the epitaxial P columns penetrate through the N epitaxial layer and are connected with the P-type body regions at the corresponding positions so as to maintain the same potential; and a dielectric layer is arranged at the tops of the P-type body regions, a source metal layer and a first metal layer which respectively correspond to the positions of the P columns and the epitaxial P columns are arranged at the top of the dielectric layer, a plurality of connecting holes are formed in the dielectric layer, and at least one diode is connected in series between the epitaxial P column and the source metal layer of the primitive cell in a forward direction or a reverse direction.