48results about How to "Inhibit on" patented technology

A current enhanced type lateral insulated gate bipolar transistor improves current density and the turn-off speed on the premise that a latching ability is maintained to be unchanged. The semiconductor is provided with buried oxide disposed on a P-type substrate and an N-drift region disposed on the buried oxide, a P-body region and an N-buffer region are disposed on the N-drift region, a P-type collecting electrode region is disposed in the N-buffer region, an anode metal is connected to the P-type collecting electrode region, a field oxide layer is disposed on the N-drift region, a P-well region is disposed in the P-body region, a P-type emitting electrode region and an emitting electrode region are disposed in the P-well region, the inner-side boundaries of the four regions, i.e., the P-body region, the P-well region, the P-type emitting electrode region and the emitting electrode region are synchronously recessed inwardly to form a square groove, the emitting electrode region surrounding the groove is successively defined as a first P-type emitting electrode region, second, third and fourth N-type emitting electrode regions and a fifth P-type emitting electrode region, the N-drift region protrudes outwardly and fills the square groove, a surface of the P-body region is provided with a gate oxide layer, a surface of the gate oxide layer is provided with a polysilicon layer, and a gate metal is connected to the polysilicon layer.

The invention relates to a super junction semiconductor device manufacturing method capable of improving the avalanche capacity. On-resistance is increased correspondingly due to transverse diffusion caused by the traditional high dosage concentration of a column P, and puncture voltage is reduced due to electric charge unbalance of the column P and a column N. According to the method, the epitaxy technology is utilized to form an N-type epitaxy layer; a P-type and N-type epitaxy layer is formed by injecting boron ions; the injection amount of the boron ions increases gradually, and the boron ions are pushed under the high temperature to form a P-type and N-type alternant epitaxy layer; a Pbody area is formed by injecting the boron ions; a polycrystalline silicon gate electrode is formed by etching polycrystalline silicon through the dry method; an N+ source area is formed by injecting arsenic ions; a layer of aluminum is deposited on the upper surface of a whole device, a source metal electrode is formed by etching the aluminum, and a drain electrode is formed on the back face through metallization. According to the super junction semiconductor device obtained through the method, the avalanche capacity of the super junction semiconductor device is improved, and at the same time, on-resistance is reduced.

The invention discloses a silicon carbide MOSFET device integrated with an SBD and a preparation method of the silicon carbide MOSFET device. The silicon carbide MOSFET device comprises a substrate, an N-epitaxial layer, a P well region, a P + region of a junction field effect region, a P + region and an N + region of a source groove region, a first ohmic contact metal layer, a first Schottky contact metal layer, a second ohmic contact metal layer and a second Schottky contact metal layer. The P + region of the junction field effect region is positioned on one side, far away from the N + region, of the P well region; the second ohmic contact metal layer covers one surface, deviating from the N-epitaxial layer, of the P + region of the junction field effect region; the first Schottky contact metal layer is located on the side, away from the P well region, of the second ohmic contact metal layer. And the second Schottky contact metal layer is arranged on one side, deviating from the P + region of the junction field effect region, of the second ohmic contact metal layer, and is parallel to the P + region of the junction field effect region. The source contact resistance can be reduced, the through-current capability of the silicon carbide device is improved, and the reliability of the silicon carbide device is improved.

The invention discloses a discrete power mos field effect transistor and a manufacturing method thereof. In the process of forming the power mos field effect transistor, a source region is firstly formed in an epitaxial layer, contact hole corrosion is carried out on the formed source region, P+ injection and original P+ region connection are carried out on a contact hole region to form a P+ region, metal deposition is carried out to form a metal layer and contact of the metal layer and N+ and P+ of the source region is finally obtained. In the technical process, the lithography process of separately forming N+ and P+ through twice lithography corrosion in the original technical process is reduced, so that one-time lithography is reduced from the manufacturing process of a power MOS, and the manufacturing process is simplified and the production cost is reduced; a contact path of the P+ and the metal layer is shortened by adopting a silicon etching technology, so that parasitic P+ resistance is reduced to inhibit starting of a parasitic NPN and improvement of the avalanche breakdown tolerance is facilitated; and the source region is firstly formed and then contact hole corrosion is carried out on the formed source region, so that the trouble that P+ injection cannot be carried out after contact hole lithography due to the fact that the concentration of the N+ is much greater than that of the P+ is avoided.

The invention discloses a cellular structure of a silicon carbide MOSFET device. The cellular structure comprises a drift region positioned on a substrate layer, a second conductive type well region and a first JFET region which are positioned in the drift region, an enhancement region positioned in the surface of the well region, a gate insulation layer located on the first conductivity type enhancement region, the well region and the first JFET region and making contact with the first conductivity type enhancement region, the well region and the first JFET region at the same time, a gate on the gate insulation layer, a source metal located on the enhancement region, Schottky metals located on the second conductivity type enhancement region and the drift region, a second JFET region located on the surface of the drift region between the Schottky metals, and a drain metal. An SBD is integrated in the silicon carbide MOSFET cellular structure, so opening of a body diode is restrained, and the reliability of the device is improved; the SBD is integrated between the second conduction type enhancement regions of the MOSFET cellular structure, so the overall power density of the chip is increased; and Schottky metal and the second JFET region are arranged at intervals, so a good compromise relationship between the on resistance and the leakage current is realized.

The invention discloses an insulated gate bipolar transistor comprising a substrate, gate structures, emitters and a collector. The gate structures, the emitters and the collector are arranged at the substrate; and the collector and the emitters are arranged at the two ends of the substrate. Each gate structure consists of a narrow part, a first widening part, and a second widening part; the narrow part is arranged between two emitters; the second widening part is arranged at one side, approaching the collector, of the gate structure; and the first widening part is connected between the narrow part and the second widening part. The first widening part is wider than the narrow part and thus areas that are connected with the emitter and are arranged in first directions of the emitters are filled, thereby suppressing starting of parasitic transistors at the edges of the emitters; and the second widening part is wider than the first widening part. Therefore, a technical problem of weak anti-latching capability of the existing PNM-IGBT device in the prior art can be solved; and thus a technical effect that the anti-latching capability is improved obviously while the parameter performance of the device is guaranteed is realized.

The invention relates to a trench gate metal oxide field effect transistor, which comprises a front metal electrode, a back metal electrode, an N-type single crystal substrate, an N-type epitaxial layer and a first P-type doping region, wherein a central part of the N-type epitaxial layer and a central part of the first P-type doping region are provided with a vertical trench, a first dielectric layer is arranged between the side wall of a grid electrode in the trench and the first P-type doping region, a second dielectric layer is arranged between the bottom of the grid electrode and the epitaxial layer, the first P-type doping region is provided with a first N-type doping region at the part close to the two sides of the trench, the first P-type doping region is further provided with a second P-type doping region at the part away from the two sides of the trench, the internal part of the epitaxial layer is further provided with a third P-type doping region and a second N-type doping region which are contacted with the lower part of the second dielectric layer, the third P-type doping region and the second N-type doping region are enabled to be mutually staggered and spaced, and a plurality of PN junction units are formed in the length direction and the thickness direction. According to the invention, parasitic capacitance between a grid electrode and a drain electrode of a low trench gate SiC MOSFET can be reduced, the electric field intensity at the bottom of the trench is reduced, and turn-on of a parasitic BJT (Bipolar Junction Transistor) is suppressed.

The invention provides a super-junction vertical double-diffusion metal oxide semiconductor tube, comprising an N-type heavily-doped silicon substrate which is used as a drain region, wherein drain electrode metal is arranged on the lower surface of the N-type heavily-doped silicon substrate; an N-type doped silicon epitaxial layer is arranged on the upper surface of the N-type heavily-doped silicon substrate; a discontinuous P-type doped columnar semiconductor region is arranged in the N-type doped silicon epitaxial layer; a first P-type doped semiconductor region is arranged on the P-type doped columnar semiconductor region; the first P-type doped semiconductor region is arranged in the N-type doped silicon epitaxial layer; and the first P-type doped semiconductor region is internally provided with a second P-type doped semiconductor contact region and an N-type doped semiconductor source region. The super-junction vertical double-diffusion metal oxide semiconductor tube is characterized in that: the N-type doped semiconductor source region is connected with active electrode metal; the second P-type doped semiconductor contact region is connected with substrate metal; polycrystalline silicon which is used as an resistor is arranged below the active electrode metal and the substrate metal; and the polycrystalline silicon is respectively connected with the active electrode metal and the substrate metal, and top layer metal is connected with the substrate metal.

The invention discloses a lock and a key used by matching with the same. The lock comprises a lock shell, a lock cylinder, a moving post and a braking post, wherein a lock shell braking post hole is arranged in the lock shell; and a lock shell moving post hole is arranged in the side wall of the lock shell. The lock cylinder is sleeved in the lock shell, and is provided with a lock cylinder braking post hole corresponding to the lock shell braking post hole. A lock cylinder moving post hole is arranged in the lock cylinder and is a through hole for the lock cylinder to pass through; and the both ends of the lock cylinder moving post hole respectively correspond to the lock shell moving post hole which is arranged in the side wall of the lock shell. The lock cylinder braking post hole and the lock cylinder moving post hole are communicated with each other. The lock cylinder is axially provided with a key hole. The key hole is communicated with the lock cylinder moving post hole. The moving post is arranged in the lock cylinder moving post hole. The moving post is provided with a clamping groove and a protruding part extending into the key hole. The braking post is arranged in the lock cylinder braking post hole; and one end of the braking post is provided with an arc-shaped face, and the other end of the braking post is provided with a bump fit with the clamping groove in shape. The moving post and the braking post of the lock are in a braking type design; and the braking post is hidden in the lock cylinder and is difficult to contact from the outside and damage by an external force.

The invention relates to the field of integrated circuits and discloses a U-shaped source slot VDMOSFET device integrated with a Schottky diode, which is characterized in that the device comprises a substrate (8); a drain electrode (9) arranged below the substrate (8); N-drift region (7) arranged above the substrate (8); a source (4) arranged above the N-drift region (7); an N+ source region (5) arranged in the N-drift region on both sides of the source electrode (4); a P-type base region (6) provided in the N-drift region (7); a gate-source isolation layer (3) arranged above the N+ source region (5); a gate dielectric (2) and a gate electrode (10). The interfaces of the source (4) and the N-drift region (7) are in a Schottky contact. The device can improve the reliability of the device performance and reduce the complexity and cost of the design.