48results about How to "Inhibit on" patented technology

The invention discloses a method for preparing FinFET on a germanium and III-V semiconductor material substrate, and the method mainly comprises following steps of forming a source drain and a slender graphic structure which is connected to the source drain; forming an oxidization isolation layer; forming a grid structure and a source drain structure; and forming metal contact and metal interconnection. Due to the adoption of the method, the FinFET is easily formed on the germanium and III-V semiconductor material substrate, the entire process flow is completed on the germanium and III-V semiconductor material substrate and is completely similar to the manufacturing technology of a conventional ultra-large-sized integrated structure, and the preparation process has characteristics of simpleness, convenience and short period. In addition, the minimal width of the FinFET prepared by the method can be controlled within 20 nanometers, and a multi-grid structure can provide good grid control capacity and is very suitable for preparing ultra-short-channel devices to further reduce the size of the devices. The FinFET prepared by the method has low power consumption.

The invention provides a high-voltage device for a drive chip of a plasma flat-panel display, pertaining to the field of a semi-conductor power device. A high-voltage pLDMOS device, a high-voltage nLDMOS device and a high-voltage nLIGBT device are established on a substrate, an oxygen burying layer and an SOI layer and separated by deep-slot medium isolation areas. The oxygen burying layer and thedeep-slot medium isolation areas positioned between the substrate and the SOI layer realize the full medium isolation of the device and low-voltage logic circuits. The thickness of the SOI layer is 8micrometers and can meet the requirements of the device for high-voltage resistance. Compared with the thin SOI technology, the self-heating effect is relieved obviously and the nLIGBT device has lowconduction resistance. The group of the high-voltage device for the drive chip of the plasma flat-panel display based on the thick SOI layer fully utilizes the characteristics of the SOI technology,such as low leak, small chip occupying area, high speed, high density of integration and low power consumption, thus meeting the development requirements of the large-sized plasma flat-panel display.

The invention discloses a lock and a key used by matching with the same. The lock comprises a lock shell, a lock cylinder, a moving post and a braking post, wherein a lock shell braking post hole is arranged in the lock shell; and a lock shell moving post hole is arranged in the side wall of the lock shell. The lock cylinder is sleeved in the lock shell, and is provided with a lock cylinder braking post hole corresponding to the lock shell braking post hole. A lock cylinder moving post hole is arranged in the lock cylinder and is a through hole for the lock cylinder to pass through; and the both ends of the lock cylinder moving post hole respectively correspond to the lock shell moving post hole which is arranged in the side wall of the lock shell. The lock cylinder braking post hole and the lock cylinder moving post hole are communicated with each other. The lock cylinder is axially provided with a key hole. The key hole is communicated with the lock cylinder moving post hole. The moving post is arranged in the lock cylinder moving post hole. The moving post is provided with a clamping groove and a protruding part extending into the key hole. The braking post is arranged in the lock cylinder braking post hole; and one end of the braking post is provided with an arc-shaped face, and the other end of the braking post is provided with a bump fit with the clamping groove in shape. The moving post and the braking post of the lock are in a braking type design; and the braking post is hidden in the lock cylinder and is difficult to contact from the outside and damage by an external force.

A current enhanced type lateral insulated gate bipolar transistor improves current density and the turn-off speed on the premise that a latching ability is maintained to be unchanged. The semiconductor is provided with buried oxide disposed on a P-type substrate and an N-drift region disposed on the buried oxide, a P-body region and an N-buffer region are disposed on the N-drift region, a P-type collecting electrode region is disposed in the N-buffer region, an anode metal is connected to the P-type collecting electrode region, a field oxide layer is disposed on the N-drift region, a P-well region is disposed in the P-body region, a P-type emitting electrode region and an emitting electrode region are disposed in the P-well region, the inner-side boundaries of the four regions, i.e., the P-body region, the P-well region, the P-type emitting electrode region and the emitting electrode region are synchronously recessed inwardly to form a square groove, the emitting electrode region surrounding the groove is successively defined as a first P-type emitting electrode region, second, third and fourth N-type emitting electrode regions and a fifth P-type emitting electrode region, the N-drift region protrudes outwardly and fills the square groove, a surface of the P-body region is provided with a gate oxide layer, a surface of the gate oxide layer is provided with a polysilicon layer, and a gate metal is connected to the polysilicon layer.

The invention relates to a super junction semiconductor device manufacturing method capable of improving the avalanche capacity. On-resistance is increased correspondingly due to transverse diffusion caused by the traditional high dosage concentration of a column P, and puncture voltage is reduced due to electric charge unbalance of the column P and a column N. According to the method, the epitaxy technology is utilized to form an N-type epitaxy layer; a P-type and N-type epitaxy layer is formed by injecting boron ions; the injection amount of the boron ions increases gradually, and the boron ions are pushed under the high temperature to form a P-type and N-type alternant epitaxy layer; a Pbody area is formed by injecting the boron ions; a polycrystalline silicon gate electrode is formed by etching polycrystalline silicon through the dry method; an N+ source area is formed by injecting arsenic ions; a layer of aluminum is deposited on the upper surface of a whole device, a source metal electrode is formed by etching the aluminum, and a drain electrode is formed on the back face through metallization. According to the super junction semiconductor device obtained through the method, the avalanche capacity of the super junction semiconductor device is improved, and at the same time, on-resistance is reduced.

The invention relates to the field of power semiconductors, and provides a slot-gate IGBT device with a carrier storage layer (CSL), which is used to solve the problem of high saturation voltage and short-circuit safe working area of ​​the existing slot-gate IGBT with a carrier storage layer (CSL). In view of the problems of small size and limited concentration of CSL, a new trench-gate IGBT device with carrier storage layer is proposed. The IGBT of the present invention directly integrates a plurality of series diodes on the surface of the silicon chip in the trench gate IGBT process to clamp the potential of the electric field shielding layer in the P region, thereby breaking through the concentration limit of CSL on the basis of the existing trench gate IGBT process, and extremely The injection efficiency of the emitter of the IGBT is greatly improved, thereby greatly improving the trade-off relationship between the turn-on voltage drop and the turn-off loss of the IGBT; at the same time, due to the clamping effect of the diode, the drain near the nMOS channel of the IGBT is in the Under high voltage and high current, it is clamped at a lower voltage, so that the saturation current of the new IGBT is greatly reduced, thereby improving the short-circuit safe working area of ​​the IGBT.