102results about How to "Improve integration density" patented technology

The invention discloses an external bias pixel structure of a light receiving stage circuit in a dynamic vision sensor pixel. The external bias pixel structure comprises a photodiode, a logarithmic tube, an amplifier tube, a switch tube and a bias tube, the bias tube, the switch tube and the amplifier tube are sequentially connected in series, a source electrode of the bias tube is connected with a power supply, a drain electrode of the bias tube is connected with a drain electrode of the switch tube, a source electrode of the switch tube is connected with a drain electrode of the amplifier tube, and a source electrode of the amplifier tube is grounded; the grid electrode of the bias tube is in signal connection with Vbias, the grid electrode of the switch tube is in signal connection with Vcpr, the source electrode of the switch tube and the drain electrode of the amplifier tube are connected with the grid electrode of the logarithmic tube, the drain electrode of the logarithmic tube is connected with a power supply, the source electrode of the logarithmic tube is connected with the negative electrode of the photodiode, and the positive electrode of the photodiode is grounded. And a grid electrode of the amplifier tube is also connected between the source electrode of the logarithmic tube and the negative electrode of the photodiode.

The invention relates to a shock absorber and a shock absorption system, and belongs to the technical field of precise shock absorption. The shock absorber comprises a base, a top plate, a piston and a supporting piece, a cavity is formed in the side, facing the top plate, of the base, the piston is connected with the base in the cavity in the mode that the piston can move in the depth direction of the cavity, the piston and the cavity are sealed to form a sealed cavity, the piston is connected with the top plate through the supporting piece, and therefore the pneumatic assembly with the vertical vibration reduction function is integrated in the vibration damper. The air cavity and the piston of the pneumatic assembly are both arranged at the bottom of the shock absorber, so that the air cavity and the piston are prevented from occupying the space between the base and the top plate in the shock absorber, and due to the fact that the area of the area, where the air cavity can be arranged, of the shock absorber base is larger, the shock absorber base can be more compact under the condition that the thickness of the base is not increased or slightly increased. The air cavity and the piston are arranged in the shock absorber base, so that the device integration density can be improved, the space can be compact, and miniaturization and multi-functionalization of the shock absorber are facilitated.

The invention belongs to the technical field of storage and calculation integration, and particularly discloses a three-dimensional storage and calculation integration system and an operation method thereof, and the system comprises an input module which has an input end connected to an output end of a main processor and is used for converting to-be-processed data into an analog voltage signal; the input end of the memristor array is connected to the output end of the input module, and the memristor array is used for carrying out matrix vector multiplication or matching operation on pre-stored operation data and the analog voltage signal and outputting a first operation result of the data to be processed; the input end of the sensing module is connected to the output end of the memristor array, and the sensing module is used for converting the first operation result into a corresponding digital signal based on the signal form of the first operation result; and the main processor is used for analyzing the digital signal and determining a second operation result of the data to be processed. According to the invention, the storage area and power consumption of the system can be effectively reduced, and the operation speed and efficiency of the system are improved.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps that an active structure is formed on a semiconductor substrate, the active structure comprises a first part and a second part, and the second part is close to the semiconductor substrate relative to the first part; based on the first part, forming a front vertical stacked transistor, the front vertical stacked transistor comprising: a first transistor and a second transistor, the first transistor and the second transistor having different polarities, the first transistor and the second transistor being self-aligned in a first direction, the first direction being a direction perpendicular to the semiconductor substrate; reversing and removing the semiconductor substrate; on the basis of the second part, a reverse side vertical stacking transistor is formed, the reverse side vertical stacking transistor comprises a third transistor and a fourth transistor, the polarities of the third transistor and the fourth transistor are different, and the third transistor and the fourth transistor are self-aligned in the first direction.

The present disclosure relates to a memory device and a manufacturing method thereof, and an electronic device, the memory device comprising: memory cells arranged on a substrate, the memory cells being arranged at intervals in a direction perpendicular to the substrate, the memory cells comprising gate transistors and resistive devices; the gating transistor comprises a horizontal semiconductor layer extending along a first direction parallel to the substrate, and the resistive device comprises a horizontal semiconductor layer, and a resistive layer and an electrode layer which are sequentially arranged far away from the horizontal semiconductor layer along the first direction; the source lines extend along a second direction parallel to the substrate, are arranged at intervals along a third direction perpendicular to the substrate, and are arranged on one side, far away from the resistive layer, of the horizontal semiconductor layer along the first direction; word lines disposed in the third direction to intersect the horizontal semiconductor layers of the gate transistors arranged in the third direction; and the bit line is arranged along the third direction and is connected with the electrode layers of the resistive devices arranged along the third direction. The storage units are integrated in the third direction perpendicular to the substrate, and the integration density of the storage device is improved.

The invention belongs to the related technical field of transistors, and discloses a heterojunction type multi-valued logic transistor and a preparation method and application thereof.The transistor comprises a substrate, an insulating layer, a source electrode, a drain electrode, an N-type channel layer and a P-type channel layer, and the insulating layer is arranged on the substrate; the source electrode, the drain electrode, the N-type channel layer and the P-type channel layer are respectively arranged on the surface, far away from the substrate, of the insulating layer; the source electrode and the drain electrode are electrically connected with the N-type channel layer and the P-type channel layer respectively, the N-type channel layer and the P-type channel layer share the same grid electrode, and the N-type channel layer and the P-type channel layer are partially overlapped. Different grid voltages are applied to the substrate through the grid, resistance state regulation and control can be carried out on a conducting channel, the mixed transconductance effect is achieved, and then a logic circuit with a three-valued logic function is constructed.

The invention provides a magnetic memory cell and array, and relates to the technical field of semiconductors, the magnetic memory cell at least comprises a spin orbit moment layer and a magnetic tunnel junction arranged above the spin orbit moment layer; a first write-in voltage is applied to a write-in path between the top end of a magnetic tunnel junction and at least one end of a spin-orbit moment layer, and meanwhile, the magnetic tunnel junction is short-circuited and the corresponding end of the spin-orbit moment layer is open-circuited, so that the resistance state of the magnetic storage unit is in an open-circuit state; and comparing the simultaneously read detection signal of the magnetic storage unit with a reference signal arranged outside the magnetic storage unit to obtain the data state stored by the magnetic storage unit. According to the SOT-MRAM-based magnetic storage unit, OTP or FTP data reading and writing are realized, and meanwhile, the size of an OTP unit or an FTP unit is reduced.

The embodiment of the invention provides a storage unit, a memory, a manufacturing method of the memory and electronic equipment. The memory cell comprises a read transistor and a write transistor, the read transistor is a double-gate transistor, and the read transistor comprises a first gate, a second gate, a first source / drain and a second source / drain; the first grid electrode is used for being electrically connected with a reading word line; the first source / drain electrode is used for being electrically connected with a reference voltage end; the write transistor comprises a third source / drain electrode and a fourth source / drain electrode; the third source / drain electrode is electrically connected with the second grid electrode; the fourth source / drain electrode and the second source / drain electrode are used for being electrically connected with a bit line. The read transistor is a planar transistor, the write transistor is a vertical transistor, and the read transistor and the write transistor are stacked in the direction vertical to the substrate, so that the integration density of the memory cell can be improved.

The invention relates to a preparation method of a packaging structure and the packaging structure, and the preparation method of the packaging structure comprises the steps: providing a first carrier plate; an interposer structure, an interposer substrate, a wiring layer and a conductive through hole structure are formed on the first carrier plate, the wiring layer is located on the side, away from the first carrier plate, of the interposer substrate, and the conductive through hole structure penetrates through the interposer substrate and is connected with the wiring layer; forming a chip on one side, far away from the interposer substrate, of the wiring layer; forming a plastic package layer covering the chip and the interposer structure; removing the first carrier plate; and forming an external circuit module on one side of the interposer structure far away from the chip, wherein the external circuit module is connected with the chip through the interposer structure. The performance of the packaging structure can be effectively improved.

The invention provides a wafer-level packaging structure of a heterogeneous chip and a preparation method of the wafer-level packaging structure. According to the preparation method, the first chip is inversely stacked on the second chip, and the electrodes of the first chip and the second chip are led out through the metal interconnection layer. The occupation rate of the area of the mainboard is reduced, the integration density is improved, a glass carrier plate does not need to be prepared, the preparation cost is reduced, the process efficiency is improved, and the process effects of 2.5 D packaging and 3D packaging are achieved on the basis of 2D packaging. Besides, under the condition that the first chip is inverted, an opening of the cavity in the first chip is covered by the bonding area in the metal interconnection layer, and sealing is achieved through the plastic packaging adhesive layer. Therefore, an expensive dry film does not need to be used for covering the opening of the cavity in the process of preparing the first chip, the preparation cost is further reduced, and the process efficiency is improved.

The present invention discloses an optimized integration method for high stress edge effect of analog BiCMOS process and a high linearity dual polycrystalline capacitor, the steps of which include: 1) depositing a polycrystalline film layer of a polycrystalline capacitor lower plate of P1 angstrom above a field oxide layer on the surface of an N-type well, and completing N-type photolithography implantation doping; 2) depositing a first dielectric layer of a dual polycrystalline capacitor of d1 angstrom, and completing the production of a protective film layer at the edge of the lower electrode of the dual polycrystalline capacitor by an exposure and etching process; 3) depositing a polycrystalline capacitor dielectric composite film layer of d2 angstroms, and completing the production of a capacitor dielectric layer structure by an exposure and etching process; the high linearity dual polycrystalline capacitor includes a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a self-aligned P-type well, etc. The present invention significantly improves the edge effect of the dual polycrystalline capacitor by integrating a high stress edge effect optimization technical solution of a high linearity dual polycrystalline capacitor in an analog integrated circuit.

The utility model provides an embedded circuit board, which comprises a circuit board and a chip with double-sided pins, the circuit board comprises a first surface and a second surface deviating from the first surface, the first surface of the circuit board is provided with a first circuit layer, the second surface of the circuit board is provided with a second circuit layer, and the outer surface of the chip is provided with an anti-oxidation layer. The chip is embedded in an insulating layer of the circuit board, a connecting layer is formed on the anti-oxidation layer at the position of a chip pin through sintering, a metalized blind hole is formed in the position, corresponding to the chip pin, of the circuit board, the blind hole is fixed with the chip pin through the connecting layer, and the first circuit layer and the second circuit layer are electrically connected with the chip pin through the blind hole respectively.

The embodiment of the present application relates to the field of energy storage technology, and provides an energy storage boost converter box, including: a box body, the box body includes a control area and a converter area, an isolation plate is arranged between the control area and the converter area, the control area is used to set a control circuit, and the converter area is used to set a first converter and a second converter; the control circuit includes: a first circuit breaker, a second circuit breaker, a first fuse, a second fuse, a first relay, a second relay, a third relay and a fourth relay; the first circuit breaker is arranged above the second circuit breaker through a first bracket; the first fuse and the second fuse are arranged above the first relay, the second relay, the third relay and the fourth relay through a second bracket. The energy storage boost converter box provided by the embodiment of the present application is at least conducive to realizing a high degree of integration of the energy storage system.

The utility model relates to an off-grid inverter, which belongs to the technical field of inversion devices and comprises a casing and a main board arranged on the bottom wall of the casing, the main board is sequentially provided with a PV module, an inversion module, a DC-DC module and a battery module along the transverse direction, the front side of the PV module is provided with an AC module, the main board is provided with a copper bar jumper wire and a copper sheet, and the DC-DC module is connected with the battery module. The mainboard is connected with the PV module and the AC module through copper bar jumper wires, and the mainboard is connected with the battery module through a copper sheet. Wherein the PV module is a photovoltaic input module, the DC-DC module is a DC transformation module, and the AC module is an AC output module. According to the utility model, the PV module, the inversion module, the DC-DC module and the battery module are sequentially arranged along the transverse direction of the mainboard, the mainboard is connected with the PV module and the AC module through the copper bar jumper wire and is connected with the battery module through the copper sheet, and the inverter adopts a wireless design, has the advantages of compact structure, simplicity, order and convenience in wiring, and can improve the production efficiency.

The invention discloses an OFPGA chip packaging structure, which comprises an OFPGA silicon chip main body and a glass substrate, TGV through holes, fine pitch waveguides and coupling gratings are arranged on the glass substrate, and the OFPGA silicon chip main body and the glass substrate are bonded through micro salient points and covalent bonds to realize mechanical fixation and signal interconnection; the glass substrate realizes vertical electrical interconnection through high-density TGV through holes, optical signal transmission is realized through fine-pitch waveguides and coupling gratings, and the micro convex points are metal convex structures formed on the glass substrate. The space utilization rate is greatly increased; ultra-short-distance electric signal transmission in the vertical direction is achieved through the high-density TGV through holes, and signal delay is greatly reduced; the thermal stress after bonding is effectively reduced by means of the similar thermal expansion coefficient characteristic of the glass substrate and the silicon chip, and the stability of photoelectric signal separation transmission is ensured by combining high-precision matching interconnection of the TGV through holes and the micro convex points.

The invention relates to the technical field of semiconductor device preparation, and discloses a silicon-based heterogeneous device monolithic integration method and a silicon-based heterogeneous device monolithic, and the method comprises the steps: depositing a dielectric material on the surface of a silicon substrate, forming an isolation groove above an N well and a P well, and forming an epitaxial lamination in the groove; depositing a hard mask layer and carrying out graphical process treatment, forming a reserved mask layer above the epitaxial lamination layer, and then preparing two different types of vertical devices in the isolation groove; depositing a dielectric material in the isolation groove, and exposing the surface of the vertical device in an external environment by adopting a sinking process; hKMG deposition and graphical process processing are carried out on the surface of the vertical device to form a high-K metal gate, then interlayer dielectric deposition is carried out to form an interlayer dielectric layer, through hole etching is carried out on the interlayer dielectric layer, and conductive metal is filled to form a silicon-based heterogeneous device single chip. According to the method, high-density integration of different types of vertical devices is realized, and the performance, the reliability and the integration degree of the device are remarkably improved.

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array comprising a plurality of first semiconductor columns; forming first word lines, each first semiconductor column being connected with a corresponding first word line and a first bit line; forming a second transistor array on the first transistor array, the second transistor array comprising a plurality of second semiconductor columns, the first semiconductor columns and the second semiconductor columns corresponding to each other; and forming second word lines and second bit lines, each second semiconductor column being connected with a corresponding second word line and a second bit line, so as to form a 2T0C semiconductor structure, and the capacitor process in the manufacturing process of the semiconductor structure can be simplified.

The invention provides a preparation method of a transistor, the transistor and a semiconductor device. The preparation method comprises the following steps: forming a stack structure on a semiconductor substrate; the stacking structure is etched to form a plurality of fin-shaped structures, the fin-shaped structures are sequentially arranged in the first direction, and a first groove is formed between any two adjacent fin-shaped structures in the fin-shaped structures; forming a first side wall covering the side walls of the plurality of fin-shaped structures in the first groove; etching the semiconductor substrate below the first groove to obtain a second groove; depositing a dielectric material in the first trench and the second trench to form an isolation structure; removing the first side wall to separate the isolation structure and the plurality of fin-shaped structures to obtain a first semiconductor structure; a plurality of first transistors are formed based on the plurality of fin-shaped structures in the first semiconductor structure, the isolation structure is used for electrically isolating any two adjacent first transistors in the plurality of first transistors, and the polarities of any two adjacent first transistors are the same or different.

The utility model provides a kind of multi-channel high integration low-cost tile type transmitting assembly, including tile type shell, input interface, microstrip line located in tile type shell interior and input interface are sequentially connected, microwave composite multilayer board, two branch networks are connected on microwave composite multilayer board and with microstrip line output end connection, first drive power amplifier, second drive power amplifier are respectively connected with the two output ends of two branch networks, first eight branch networks are connected with the output end of first drive power amplifier, second eight branch networks are connected with the output end of second drive power amplifier, 16-way transmitting channel and radio frequency output port connected with transmitting channel output end are respectively connected with the output end of first eight branch networks, second eight branch networks, the number of radio frequency output port is 16.The utility model is X frequency band 16 channel tile type high integration, high reliability, high consistency and with power amplification, numerical control phase shift and output detection etc. The utility model discloses a kind of multi-channel high integration low-cost tile type transmitting assembly, including tile type shell, output interface, microstrip line located in tile type shell interior and output interface are sequentially connected, microwave composite multilayer board, two branch networks are connected on microwave composition multilayer board and with microstrip line output end connection, first drive power amplifier, second power amplifier are respectively connected with the two output ends of two branch networks, first eight branch networks is connected with the output end of first drive power amplifier, second eight branch networks is connected with the output end of second drive power amplifier, 16-way transmitting channel and radio frequency input port connected with transmitting channel output end are respectively connected with the output end of first eight branch networks and second eight branch networks, the number of radio frequency input port is 16.

The invention provides an energy storage container staggered battery rack structure capable of meeting high integration density. The energy storage container staggered battery rack structure comprises a plurality of stand column sets arranged in an arrayed mode, a plurality of parallel battery rack guide rails fixedly arranged on the stand column sets at equal intervals and upper and lower limiting pieces arranged behind battery packs. The battery rack guide rail comprises an L-shaped guide rail, a baffle arranged on the L-shaped guide rail and fixing pieces arranged at the two ends of the L-shaped guide rail. The L-shaped guide rail is used for placing the battery pack, the baffle prevents the battery pack from deviating during installation, and the fixing piece prevents the battery pack from falling off in the transportation process; the up-and-down limiting pieces are used for up-and-down limiting of the battery pack, so that the battery pack is prevented from violently jumping in the transportation process; the battery rack guide rails on the adjacent upright post groups are staggered up and down; and the battery packs on the adjacent upright post groups are arranged back to back. By utilizing the depth difference between the battery module box body and the bottom plate, the battery rack guide rails are arranged up and down in a staggered manner, so that the integration density of the energy storage container in height and width is improved.

The invention discloses a gate circuit device structure and process of a CFET, and relates to the technical field of semiconductors, the gate circuit device structure comprises a substrate, the top of the substrate is wrapped by an N channel field effect transistor # imgabs0 # and a P channel field effect transistor # imgabs1 # which are connected in parallel through an insulating layer; the N channel field effect transistor # imgabs2 # and the P channel field effect transistor # imgabs3 # share the same source electrode S, and the N channel field effect transistor # imgabs4 # and the P channel field effect transistor # imgabs5 # share the same drain electrode D; a grid electrode # imgabs7 # of the N-channel field effect transistor # imgabs6 # and a grid electrode # imgabs9 # of the P-channel field effect transistor # imgabs8 # are separated from each other, and the grid electrode # imgabs10 # and the grid electrode # imgabs11 # which are separated from each other form a separation grid structure. According to the invention, the original planar CMOS unit is folded in half to form a three-dimensional device which is vertically stacked upwards, and the grid electrodes of the dielectric isolation P-type and N-type field effect transistor devices are adopted to form a separation grid structure, so that the planar area of CFET integration can be saved, the integration density can be improved, the channel process can be shortened, and the chip precision can be improved; and the circuit performance and the circuit design flexibility can be maintained.

The invention relates to the technical field of semiconductors, in particular to a packaging structure and a forming method thereof, and the packaging structure comprises an interconnection device which is a thinned bridge chip and is provided with a first surface and a second surface which are opposite to each other; the first chip is positioned on one side of the first surface of the interconnection device, and the projection surface of the first chip is partially overlapped with the first surface of the interconnection device; the second chip is located on one side of the first face of the interconnection device, the projection face of the second chip is partially overlapped with the first face of the interconnection device, and the first chip and the second chip are electrically connected through the interconnection device. Based on the above technical scheme, the structure packaging density and the chip interconnection density are significantly improved, the signal transmission distance is reduced, and the electrical performance is improved.

The embodiment of the present disclosure relates to the field of semiconductor, and provides a magnetic memory structure and a memory, which comprises: a plurality of stacked magnetic storage units, and the magnetic storage unit at least comprises: a first transistor, the first transistor comprises a gate, the gate is used for connecting a control line, and one terminal of a source or a drain of the first transistor is used for connecting a first signal line; a magnetic tunnel junction, a bottom of the magnetic tunnel junction is used for connecting the other terminal of the source or the drain in the first transistor, and a top of the magnetic tunnel junction is used for connecting a second signal line, wherein the magnetic tunnel junction extends along the stacking direction of the magnetic storage unit; and the magnetic tunnel junctions in the plurality of stacked magnetic storage units are connected to the same second signal line, so that the integration density of the magnetic memory structure is improved.

The invention provides a method for forming a dynamic memory, which comprises the following steps of: etching a first substrate according to a first photoetching pattern to form a silicon column structure separated by a first groove; and forming a storage capacitor by taking the silicon column structure as a capacitor plate, and forming a vertical transfer gate structure above the silicon column structure. The method is simple in process step, can form a high-density trench capacitor as a storage capacitor, is high in integration density, can be compatible with a forming process of an image sensor, and is wide in applicability. Meanwhile, according to the scheme, the polycrystalline silicon grid electrode and the active region can be used as the connection of the word line and the bit line, and the traditional capacitance density limit is broken through.

This invention discloses a memory device and its fabrication method, belonging to the field of semiconductor manufacturing technology. By employing a composite functional layer containing group III nitrides and co-doped metals, and directly depositing the film at room temperature using magnetron sputtering, suitable microstructures and defect distributions can be formed within the functional layer during growth. This allows the device to achieve stable resistive state transitions without additional electroforming processing, effectively reducing the device's operating voltage and significantly improving its reliability and state consistency under small-size conditions. The room-temperature magnetron sputtering fabrication method eliminates the need for high-temperature deposition or high-temperature annealing, allowing for strict control of the process temperature to meet the thermal budget requirements of CMOS back-end processes. This enables three-dimensional monolithic integration with logic circuits, simplifying the fabrication process, reducing process complexity, effectively lowering manufacturing costs, and increasing integration density.

An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device in embodiments of this application includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.

The invention relates to a micro-nano protection array device and a preparation method thereof, and belongs to the field of electromagnetic field protection. The electromagnetic interference protection device solves at least one problem that an existing electromagnetic interference protection device is difficult to meet the protection requirement of a high-density integrated and / or miniaturized electronic system for strong electromagnetic interference and is difficult to meet the protection requirement for narrow-band high-frequency electromagnetic interference. The invention discloses a preparation method of a micro-nano protection array device, the micro-nano protection array device comprises a graphical array structure formed by metal grids, and the preparation method comprises the following steps: S1, providing a sapphire substrate; s2, drawing a layout, and manufacturing a mask plate; s3, coating photoresist, forming a photoresist pattern through photoetching and developing, and depositing a metal strip line on the sapphire substrate; and S4, removing the photoresist to form the metal grid. According to the invention, high-density miniaturization and large-area integration of the electromagnetic protection device are realized, the electromagnetic interference protection capability of a unit area is improved, and the working frequency upper limit of electromagnetic interference protection is improved.

The invention discloses a multi-layer gate analog CMOS process edge stress optimization integration method and a low voltage coefficient polycrystalline capacitor. The method steps include: 1) forming an N-type well in a low voltage coefficient integrated dual polycrystalline capacitor area, and forming a self-aligned P-type well in an area outside the N-type well; 2) depositing a polycrystalline film layer of a lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor; 3) depositing a first layer of dielectric of the dual polycrystalline capacitor, and realizing the production of an edge protection layer of the lower electrode of the dual polycrystalline capacitor; 4) depositing a capacitor dielectric layer, and completing the production of a capacitor dielectric layer structure; the low voltage coefficient polycrystalline capacitor includes a P-type substrate, a P-type epitaxial layer, an N-type well, a self-aligned P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline film layer, a silicon dioxide dielectric layer, a capacitor dielectric layer, a low dielectric coefficient filling film layer, a metal interconnect film layer, and a protective dielectric passivation layer outside a top metal bonding area; the patent improves the edge effect of the dual polycrystalline capacitor and reduces the mechanical stress of the integrated dual polycrystalline capacitor.

The invention discloses a phase change storage material and device based on two-dimensional elementary bismuthene. The chemical component of the phase change storage material is bismuth elementary substance, and the melting point is lt; 300 DEG C; an amorphous phase of the material is of a long-range disordered atom arrangement structure, a local structure is mainly a defective octahedron and has a four-membered ring and five-membered ring structure, the coordination number of most atoms is 3, and an energy band structure has no band gap; a crystal phase of the two-dimensional bismuthene material has a buckling hexagonal honeycomb layered structure, adjacent layers are connected with each other through Van der Waals force, and an energy band structure has a band gap. According to the invention, the two-dimensional elemental bismuthene is used as a phase change functional layer material, so that the component segregation phenomenon in the use process of the device can be physically and essentially eliminated, and meanwhile, the ultrathin size and the low melting point characteristic of the material have the advantages in the aspects of high-density integration and low-power-consumption operation of the phase change memory device.

The application provides a two-dimensional semiconductor stacked device structure and a preparation method thereof, and realizes three-dimensional vertical stacking of a two-dimensional semiconductor device through a first interlayer dielectric layer and a second interlayer dielectric layer bonding process, effectively solves the problems of organic residue introduction, material folding and fracture and other problems commonly seen in the traditional two-dimensional semiconductor film transfer process, thereby significantly enhancing the integrity and long-term working stability of the stacked structure. At the same time, a high-efficiency interlayer isolation barrier is constructed by using the dielectric layer of the bonding interface, high-efficiency electrical isolation between the two two-dimensional semiconductor layers is realized, the threshold voltage crosstalk problem in the existing stacked structure is solved, independent and accurate adjustment of the threshold voltage of the upper and lower layer transistors is realized, and greater flexibility is provided for device performance optimization.