36results about How to "Improve integration density" patented technology

The utility model relates to an off-grid inverter, which belongs to the technical field of inversion devices and comprises a casing and a main board arranged on the bottom wall of the casing, the main board is sequentially provided with a PV module, an inversion module, a DC-DC module and a battery module along the transverse direction, the front side of the PV module is provided with an AC module, the main board is provided with a copper bar jumper wire and a copper sheet, and the DC-DC module is connected with the battery module. The mainboard is connected with the PV module and the AC module through copper bar jumper wires, and the mainboard is connected with the battery module through a copper sheet. Wherein the PV module is a photovoltaic input module, the DC-DC module is a DC transformation module, and the AC module is an AC output module. According to the utility model, the PV module, the inversion module, the DC-DC module and the battery module are sequentially arranged along the transverse direction of the mainboard, the mainboard is connected with the PV module and the AC module through the copper bar jumper wire and is connected with the battery module through the copper sheet, and the inverter adopts a wireless design, has the advantages of compact structure, simplicity, order and convenience in wiring, and can improve the production efficiency.

The invention discloses an OFPGA chip packaging structure, which comprises an OFPGA silicon chip main body and a glass substrate, TGV through holes, fine pitch waveguides and coupling gratings are arranged on the glass substrate, and the OFPGA silicon chip main body and the glass substrate are bonded through micro salient points and covalent bonds to realize mechanical fixation and signal interconnection; the glass substrate realizes vertical electrical interconnection through high-density TGV through holes, optical signal transmission is realized through fine-pitch waveguides and coupling gratings, and the micro convex points are metal convex structures formed on the glass substrate. The space utilization rate is greatly increased; ultra-short-distance electric signal transmission in the vertical direction is achieved through the high-density TGV through holes, and signal delay is greatly reduced; the thermal stress after bonding is effectively reduced by means of the similar thermal expansion coefficient characteristic of the glass substrate and the silicon chip, and the stability of photoelectric signal separation transmission is ensured by combining high-precision matching interconnection of the TGV through holes and the micro convex points.

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array comprising a plurality of first semiconductor columns; forming first word lines, each first semiconductor column being connected with a corresponding first word line and a first bit line; forming a second transistor array on the first transistor array, the second transistor array comprising a plurality of second semiconductor columns, the first semiconductor columns and the second semiconductor columns corresponding to each other; and forming second word lines and second bit lines, each second semiconductor column being connected with a corresponding second word line and a second bit line, so as to form a 2T0C semiconductor structure, and the capacitor process in the manufacturing process of the semiconductor structure can be simplified.

The embodiment of the present disclosure relates to the field of semiconductor, and provides a magnetic memory structure and a memory, which comprises: a plurality of stacked magnetic storage units, and the magnetic storage unit at least comprises: a first transistor, the first transistor comprises a gate, the gate is used for connecting a control line, and one terminal of a source or a drain of the first transistor is used for connecting a first signal line; a magnetic tunnel junction, a bottom of the magnetic tunnel junction is used for connecting the other terminal of the source or the drain in the first transistor, and a top of the magnetic tunnel junction is used for connecting a second signal line, wherein the magnetic tunnel junction extends along the stacking direction of the magnetic storage unit; and the magnetic tunnel junctions in the plurality of stacked magnetic storage units are connected to the same second signal line, so that the integration density of the magnetic memory structure is improved.

This invention discloses a memory device and its fabrication method, belonging to the field of semiconductor manufacturing technology. By employing a composite functional layer containing group III nitrides and co-doped metals, and directly depositing the film at room temperature using magnetron sputtering, suitable microstructures and defect distributions can be formed within the functional layer during growth. This allows the device to achieve stable resistive state transitions without additional electroforming processing, effectively reducing the device's operating voltage and significantly improving its reliability and state consistency under small-size conditions. The room-temperature magnetron sputtering fabrication method eliminates the need for high-temperature deposition or high-temperature annealing, allowing for strict control of the process temperature to meet the thermal budget requirements of CMOS back-end processes. This enables three-dimensional monolithic integration with logic circuits, simplifying the fabrication process, reducing process complexity, effectively lowering manufacturing costs, and increasing integration density.

An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device in embodiments of this application includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.

The invention relates to a micro-nano protection array device and a preparation method thereof, and belongs to the field of electromagnetic field protection. The electromagnetic interference protection device solves at least one problem that an existing electromagnetic interference protection device is difficult to meet the protection requirement of a high-density integrated and / or miniaturized electronic system for strong electromagnetic interference and is difficult to meet the protection requirement for narrow-band high-frequency electromagnetic interference. The invention discloses a preparation method of a micro-nano protection array device, the micro-nano protection array device comprises a graphical array structure formed by metal grids, and the preparation method comprises the following steps: S1, providing a sapphire substrate; s2, drawing a layout, and manufacturing a mask plate; s3, coating photoresist, forming a photoresist pattern through photoetching and developing, and depositing a metal strip line on the sapphire substrate; and S4, removing the photoresist to form the metal grid. According to the invention, high-density miniaturization and large-area integration of the electromagnetic protection device are realized, the electromagnetic interference protection capability of a unit area is improved, and the working frequency upper limit of electromagnetic interference protection is improved.

The invention discloses a phase change storage material and device based on two-dimensional elementary bismuthene. The chemical component of the phase change storage material is bismuth elementary substance, and the melting point is lt; 300 DEG C; an amorphous phase of the material is of a long-range disordered atom arrangement structure, a local structure is mainly a defective octahedron and has a four-membered ring and five-membered ring structure, the coordination number of most atoms is 3, and an energy band structure has no band gap; a crystal phase of the two-dimensional bismuthene material has a buckling hexagonal honeycomb layered structure, adjacent layers are connected with each other through Van der Waals force, and an energy band structure has a band gap. According to the invention, the two-dimensional elemental bismuthene is used as a phase change functional layer material, so that the component segregation phenomenon in the use process of the device can be physically and essentially eliminated, and meanwhile, the ultrathin size and the low melting point characteristic of the material have the advantages in the aspects of high-density integration and low-power-consumption operation of the phase change memory device.

The application provides a two-dimensional semiconductor stacked device structure and a preparation method thereof, and realizes three-dimensional vertical stacking of a two-dimensional semiconductor device through a first interlayer dielectric layer and a second interlayer dielectric layer bonding process, effectively solves the problems of organic residue introduction, material folding and fracture and other problems commonly seen in the traditional two-dimensional semiconductor film transfer process, thereby significantly enhancing the integrity and long-term working stability of the stacked structure. At the same time, a high-efficiency interlayer isolation barrier is constructed by using the dielectric layer of the bonding interface, high-efficiency electrical isolation between the two two-dimensional semiconductor layers is realized, the threshold voltage crosstalk problem in the existing stacked structure is solved, independent and accurate adjustment of the threshold voltage of the upper and lower layer transistors is realized, and greater flexibility is provided for device performance optimization.

The application discloses a waveguide bending structure based on a subwavelength Micallan lens and belongs to the technical field of integrated optics, which comprises an input port, an output port, a subwavelength Micallan lens, a first subwavelength taper coupler, a second subwavelength taper coupler, an insulator cladding, an insulating layer and a substrate layer; the input port and the output port are symmetric about the center of the subwavelength Micallan lens; the first subwavelength taper coupler, the subwavelength Micallan lens and the second subwavelength taper coupler are all composed of a periodic subwavelength grating structure; the subwavelength Micallan lens is composed of basic lens units arranged periodically with a large duty cycle on both sides and a small duty cycle in the middle, and the effective refractive index distribution thereof satisfies the reciprocal function of the hyperbolic cosine; the structure can realize low-loss and high-isolation optical path bending in a short propagation distance, break through the physical restriction between the bending radius and the bending loss, and is suitable for photonic integrated circuits and optical information processing chips.

This invention relates to the field of passive radio frequency microwave devices, specifically to a filter-type Wilkinson chip power divider and its fabrication method. The divider includes an aluminum nitride substrate, an adhesion layer, a metal ground plane, a buried dielectric layer, three-dimensional interdigitated tantalum nitride resistors, a filter power divider metal structure, and a passivation layer. The adhesion layer is disposed on the surface of the aluminum nitride substrate, the metal ground plane is disposed on the surface of the metal adhesion layer, the buried dielectric layer covers the surface of the metal ground plane, and the buried dielectric layer has resistor trenches and interconnecting vias etched inside. The three-dimensional interdigitated tantalum nitride resistors are disposed within the resistor trenches and electrically connected to the metal ground plane through the interconnecting vias. The filter power divider metal structure is disposed on the surface of the buried dielectric layer, and the passivation layer is deposited on the surface of the filter power divider metal structure. This invention achieves integrated power distribution, passband filtering, port isolation, and harmonic suppression functions through a single-chip structure. Compared to traditional modular solutions, it significantly reduces the device size and can meet the miniaturization and high integration requirements of radio frequency front-ends.

A semiconductor device is provided, the semiconductor device comprising: a lower insulating layer; a lower channel pattern on the lower insulating layer; an upper channel pattern; a lower gate structure surrounding the lower channel pattern; an upper gate structure surrounding the upper channel pattern; a first lower source / drain pattern on the lower gate structure; a first upper source / drain pattern on the upper gate structure; a first spacer on the first upper source / drain pattern; a first source / drain contact extending through the first spacer and the first upper source / drain pattern and connected to the first upper source / drain pattern and the first lower source / drain pattern; a second lower source / drain pattern on the lower gate structure; a second upper source / drain pattern on the upper gate structure; a first interlayer dielectric on the second upper source / drain pattern; and a second source / drain contact extending through the first interlayer dielectric and connected to the second upper source / drain pattern.

The present application relates to a silicon-based detector, which designs and processes the p+ injection area of the device without changing the thickness of the substrate, and performs carbon injection, increases the area of generating electron-hole pairs and avalanche effect, thereby increasing the breakdown voltage of the device and improving the anti-radiation performance of the device. In addition, the present application introduces a deep trench ring isolation structure. Compared with the traditional silicon-based detector, the protection ring does not need to be obtained by ion implantation, the influence of the edge electric field on the performance of the device is reduced, and the dead area can be smaller when the array is formed, the integration density is improved, and the detection efficiency is improved. The present application also relates to a preparation method of the silicon-based detector.

The application discloses a terahertz neural synapse memorization device and a preparation method thereof. The terahertz neural synapse memorization device comprises a substrate, an active region formed on the substrate, two electrodes in the form of interdigital electrodes, the two electrodes comprising test parts and finger parts, the test parts of the two electrodes being respectively formed on two sides of the active region, the finger parts being arranged on the active region in a staggered manner at a certain interval, and the interval between adjacent finger parts being controlled at a nanometer level; the two electrodes are respectively used as a presynaptic end and a postsynaptic end of a neural synapse, a high-frequency voltage signal is applied to the presynaptic end as an excitation source of the neural synapse, and a current signal response of the postsynaptic end is collected, so that a terahertz neural morphological calculation function is realized.

The embodiment of the invention provides a semiconductor device and a preparation method thereof, a memory unit, a read-write method and a memory. The semiconductor device comprises a substrate and a laminated structure arranged on the substrate, wherein the laminated structure comprises first semiconductor layers and insulating layers which are alternately arranged; the first hole structures and the second hole structures penetrate through the laminated structure and are arranged in the first direction, and the first direction is parallel to the substrate; a memory cell including a first sub-structure disposed in the first pore structure and a second sub-structure disposed in the second pore structure; the first substructure comprises a first gate structure of the read transistor and a capacitor, and the first substructure is located in the first semiconductor layer; the second substructure comprises a first transistor and a second transistor, and the second substructure is located in the first semiconductor layer.

An electronic assembly and a whole-cabinet server are provided. The electronic assembly includes a pair of processing elements, a chip cooling element, and a power supply cooling element. The pair of processing elements are disposed in a stacked manner in a thickness direction. Each processing element includes a carrier board, a chip, and a power supply unit. The carrier board has a first side and a second side opposite to each other in the thickness direction. The chip is disposed on the first side of the carrier board. The power supply unit is electrically connected with the carrier board. The chip cooling element is in contact with the chip. The power supply cooling element is in contact with the power supply unit, wherein the chip cooling element or the power supply cooling element is disposed between the pair of processing elements.

A semiconductor memory device includes a bit line (BL) extending in a first direction (Dl), a channel pattern (CP) on the bit line, the channel pattern including first and second vertical portions (VP1, VP2) facing each other and a horizontal portion (HP) connecting the first and second vertical portions, first and second word lines (WL1, WL2) provided on the horizontal portion and between the first and second vertical portions and extended in a second direction (D2) crossing the bit line, and a gate insulating pattern (Gox) provided between the first word line and the channel pattern and between the second word line and the channel pattern.

The application discloses a vertical power supply and distribution frame of a cluster chip system, belongs to the technical field of microelectronic packaging, and solves the layout problem that the power supply and distribution module of the cluster chip system is difficult to be placed in close proximity or the problem that the cluster chip system cannot realize short-distance power supply and distribution. In the frame, the load chip and the power supply and distribution module are stacked in the direction perpendicular to the circuit board; the power supply and distribution module comprises an external input layer, a conversion layer and a vertical interface layer which are stacked and connected from bottom to top; the number of the power supply and distribution module and the load chip is multiple, the number of the circuit board is one, the circuit board is used as the bearing and interconnection substrate of the multiple load chips, the internal metal layer of the circuit board is used for realizing the signal interconnection between the multiple load chips; and the power supply port of the load chip is interconnected with the vertical interface layer of the power supply and distribution module through the vertical power distribution hole in the circuit board. The application can be used for the vertical power supply and distribution of the cluster chip system.

This invention provides a bottom-lead non-hermetic SiP module, comprising: a package base including pins and a base plate, with one end of the pins fixed to the upper surface of the base plate and the other end extending from the lower surface of the base plate; an adapter board including a wiring layer, a substrate layer, and a first electrical interconnect structure, the substrate layer being bonded to the surface of the package base, the wiring layer being fabricated on the upper surface of the substrate layer, and the wiring layer and pins being interconnected through the first electrical interconnect structure; a chip stack including bare chips, an adhesive layer, and a second interconnect structure, the bottom bare chip being formed on the upper surface of the adapter board through the adhesive layer, the second layer of bare chips and higher layers of bare chips being formed on the upper surface of the next layer of bare chips through the adhesive layer, and the bare chips being interconnected with each other and with the wiring layer through the second electrical interconnect structure; and a molding compound encapsulating the upper half of the pins, the adapter board, and the chip stack, and forming an integral part with the base plate. This invention can improve the reliability between the SiP module and the circuit board.

The utility model provides a kind of hollow large current inductance and PCB circuit board, this hollow large current inductance includes base, magnetic core and coil, the magnetic core includes shell and magnetic column, the coil is wound the magnetic column and the shell surrounds the coil, the base includes installation platform and support column, the installation platform is used to install the shell, the support column is used to support the installation platform to make the installation platform overhang.This PCB circuit board includes PCB board and hollow large current inductance.Because shell is installed on installation platform, support column supports installation platform again, magnetic core and coil are all overhung, increase a heat dissipation surface.Finally realize the purpose of improving large current inductance heat dissipation efficiency.Embodiment of the utility model in PCB circuit board can realize a kind of PCB circuit board that can consider heat dissipation and improve electronic component integrated density.

The invention discloses a manufacturing method for embedding a ceramic substrate into a copper-based printed circuit board. The manufacturing method comprises the following steps: manufacturing a ceramic substrate; manufacturing a copper substrate; mounting a ceramic substrate; and laminating and manufacturing the copper-based PCB. According to the invention, a plurality of ceramic substrates made of materials such as aluminum nitride or silicon nitride are embedded into the copper substrate, so that the ceramic substrates are used as efficient heat dissipation media of the chip and are directly thermally connected with the copper substrate. In addition, the prepreg and the copper foil are overlaid on the surface of the copper substrate, the surface of the copper substrate is flush with the ceramic substrate through a lamination process, and then high-density circuit wiring is formed through graphical processing. Compared with the prior art, excellent thermal management performance and high-density interconnection capability are considered, and the heat dissipation efficiency and integration density of the device are remarkably improved.

The application provides a ceramic substrate structure and an integrated packaging structure thereof, and belongs to the technical field of packaging. The ceramic substrate structure comprises a substrate plate body, a large chip and a small chip. The upper surface of the substrate plate body is provided with a first groove and a plurality of pads, and the lower surface is provided with a second groove. The first groove is communicated with the groove bottom surface of the second groove. A plurality of metal wires are arranged in the second groove. The metal wires are electrically connected with the pads through a via technology. The large chip is fixedly connected to the top surface of the substrate plate body, and the small chip is fixedly connected in the second groove. The large chip, the small chip and the metal wires are electrically connected through wire bonding. Through the double-sided groove structure and the multi-level electrical connection scheme, the double-sided packaging of the chip is realized, the signal transmission path is effectively shortened, the packaging size is reduced, the heat dissipation efficiency and the electrical performance are significantly improved, and the application is particularly suitable for high-performance chip packaging applications such as back incidence detectors and other double-sided electrical connection applications.

The utility model relates to a rotary type clamp automatic switching device which comprises a rotary type storage location formed by a plurality of storage locations in a rotary type end-to-end communication mode. The working storage location is communicated with one of the rotary storage locations; the concentric-square-shaped traction mechanism is used for bearing and driving the clamp to move on each storage location of the rotary storage location; the transfer traction mechanism is used for transferring the clamp to the working storage location; the plurality of limiting guide devices are respectively arranged between every two adjacent storage positions of the rotary storage positions and between the transfer traction mechanism and the rotary storage positions; a clamp identification sensor and a control system. The welding fixture switching device overcomes the defect that the storage positions of the existing welding fixture switching device are linearly arranged and need to occupy more installation sites. According to the utility model, the problem that too many mounting sites are occupied is solved by adopting a rotary parking space arrangement mode, the space utilization rate is higher, and the integration density in the space is higher.

This application relates to a semiconductor structure and its fabrication method, and pertains to the field of integrated circuit technology. The first device in the semiconductor structure includes a vertical gate and a horizontal gate. On one hand, by controlling the vertical channel with the vertical gate and the horizontal channel with the horizontal gate, the on-resistance of the first device can be reduced. On the other hand, the vertically positioned vertical gate eliminates the need for horizontal voltage reduction using a drift region, which helps reduce the lateral area of ​​the first device, allowing it to be made smaller and improving the integration density of the semiconductor structure. Simultaneously, the electrodes of the first device are all located on the front side of the substrate and led out from the front, making it compatible with CMOS processes and allowing for co-integration with CMOS devices.

The invention discloses a grounding stacking integrated radio frequency front-end chip stacking structure and a preparation method thereof, and belongs to the technical field of radio frequency microsystems. Based on silicon-based packaging, radio frequency front-end chips including a power divider, a low-noise amplifier and a multifunctional chip are subjected to function division, and four-channel radio frequency chips are respectively subjected to silicon-based embedded packaging and are led out through silicon through holes (TSV). An upper layer chip packaging module and a lower layer chip packaging module which are used for packaging two channel radio frequency chips respectively are bonded and integrated in a back-to-back mode, and the radio frequency chips which are packaged differently on the upper layer and the lower layer are connected through TSV via holes. Fanout lead-out is carried out in a bottom layer radio frequency chip, so that high-density integrated stacking is realized. By the adoption of the integrated stacking structure, the packaging size can be greatly reduced, and compared with a traditional silicon-based embedded fan-out structure, the size can be further reduced, and the packaging weight is reduced.

The invention discloses a transistor, a semiconductor device, a manufacturing method of the semiconductor device and electronic equipment. The transistor comprises a first electrode, a second electrode, a semiconductor layer, a gate insulating layer and a gate electrode, wherein the semiconductor layer, the gate insulating layer and the gate electrode are located between the first electrode and the second electrode and are sequentially arranged; the first electrode and the second electrode are distributed on two sides of the semiconductor layer along a first direction, and the gate electrode is distributed on one side of the semiconductor layer along a second direction; the first direction is crossed with the second direction; the gate electrode extends along the first direction; the orthographic projection of the gate electrode on the plane perpendicular to the first direction is not overlapped with the orthographic projection of the first electrode on the plane perpendicular to the first direction. The orthographic projection of the gate electrode on the plane perpendicular to the first direction is not overlapped with the orthographic projection of the second electrode on the plane perpendicular to the first direction. The leakage current of the transistor provided by the embodiment of the invention is small.

The embodiment of the present disclosure relates to a semiconductor structure and a preparation method thereof, the semiconductor structure comprising: a substrate, a first doped region and a second doped region in the substrate, a first selection transistor and a second selection transistor, a conductive layer between the first doped region and the second doped region, a resistive switching dielectric layer, the conductive layer, the first doped region and the resistive switching dielectric layer opposite to the first doped region form a first variable resistor, the conductive layer, the second doped region and the resistive switching dielectric layer opposite to the second doped region form a second variable resistor, and an isolation dielectric layer between the conductive layer and the substrate. The embodiment of the present disclosure is beneficial to improve the storage density of RRAM memory.

This application provides a semiconductor structure and its fabrication method, a memory, and an electronic device. The method includes: forming a stacked first active structure and a second active structure on a substrate; forming a transistor based on the first active structure; the transistor includes a source / drain structure, a first interlayer dielectric layer, a gate, and a first back-end interconnect layer; washing and thinning the substrate; depositing a dielectric material to form a second interlayer dielectric layer; performing photolithography on the second interlayer dielectric layer and the first interlayer dielectric layer to form a first groove and a first via; the first groove is located inside the second interlayer dielectric layer; the first via is located inside the first interlayer dielectric layer and exposes at least a portion of the surface of the source / drain structure; the first via communicates with the bottom of the first groove; filling the first via with metal to form a conductive via; forming a memory element in the first groove; the memory element is electrically connected to the transistor through the conductive via; and forming a second back-end interconnect layer on the memory element.

The invention discloses a manufacturing method of a three-dimensional system chip based on metal bump interconnection, and the method comprises the steps: a female core structure, the surface of which is provided with a first original welding pad array; the at least one sub-core particle is stacked on the mother core structure in an inverted buckling manner, and the surface of the sub-core particle is provided with a second original welding pad array; the re-wiring metal column structure is arranged on the surface of the mother core structure and / or the sub core particles, and the re-wiring metal column structure comprises a re-wiring layer electrically connected with the first original welding pad array and / or the second original welding pad array; the dielectric layer is formed on the rewiring layer; the metal column penetrates through the dielectric layer and is electrically connected with the rewiring layer below the dielectric layer; wherein a metal column or a first original welding pad array is arranged on the surface of the female core structure. By introducing an innovative structure combining the prefabricated metal columns and post-growth interconnection, the wiring flexibility, reliability and integration density of three-dimensional interconnection are remarkably improved, and the method is particularly suitable for a multi-core-particle heterogeneous integrated system.