52results about How to "Improve integration density" patented technology

The invention discloses an external bias pixel structure of a light receiving stage circuit in a dynamic vision sensor pixel. The external bias pixel structure comprises a photodiode, a logarithmic tube, an amplifier tube, a switch tube and a bias tube, the bias tube, the switch tube and the amplifier tube are sequentially connected in series, a source electrode of the bias tube is connected with a power supply, a drain electrode of the bias tube is connected with a drain electrode of the switch tube, a source electrode of the switch tube is connected with a drain electrode of the amplifier tube, and a source electrode of the amplifier tube is grounded; the grid electrode of the bias tube is in signal connection with Vbias, the grid electrode of the switch tube is in signal connection with Vcpr, the source electrode of the switch tube and the drain electrode of the amplifier tube are connected with the grid electrode of the logarithmic tube, the drain electrode of the logarithmic tube is connected with a power supply, the source electrode of the logarithmic tube is connected with the negative electrode of the photodiode, and the positive electrode of the photodiode is grounded. And a grid electrode of the amplifier tube is also connected between the source electrode of the logarithmic tube and the negative electrode of the photodiode.

The invention relates to a shock absorber and a shock absorption system, and belongs to the technical field of precise shock absorption. The shock absorber comprises a base, a top plate, a piston and a supporting piece, a cavity is formed in the side, facing the top plate, of the base, the piston is connected with the base in the cavity in the mode that the piston can move in the depth direction of the cavity, the piston and the cavity are sealed to form a sealed cavity, the piston is connected with the top plate through the supporting piece, and therefore the pneumatic assembly with the vertical vibration reduction function is integrated in the vibration damper. The air cavity and the piston of the pneumatic assembly are both arranged at the bottom of the shock absorber, so that the air cavity and the piston are prevented from occupying the space between the base and the top plate in the shock absorber, and due to the fact that the area of the area, where the air cavity can be arranged, of the shock absorber base is larger, the shock absorber base can be more compact under the condition that the thickness of the base is not increased or slightly increased. The air cavity and the piston are arranged in the shock absorber base, so that the device integration density can be improved, the space can be compact, and miniaturization and multi-functionalization of the shock absorber are facilitated.

The present disclosure relates to a memory device and a manufacturing method thereof, and an electronic device, the memory device comprising: memory cells arranged on a substrate, the memory cells being arranged at intervals in a direction perpendicular to the substrate, the memory cells comprising gate transistors and resistive devices; the gating transistor comprises a horizontal semiconductor layer extending along a first direction parallel to the substrate, and the resistive device comprises a horizontal semiconductor layer, and a resistive layer and an electrode layer which are sequentially arranged far away from the horizontal semiconductor layer along the first direction; the source lines extend along a second direction parallel to the substrate, are arranged at intervals along a third direction perpendicular to the substrate, and are arranged on one side, far away from the resistive layer, of the horizontal semiconductor layer along the first direction; word lines disposed in the third direction to intersect the horizontal semiconductor layers of the gate transistors arranged in the third direction; and the bit line is arranged along the third direction and is connected with the electrode layers of the resistive devices arranged along the third direction. The storage units are integrated in the third direction perpendicular to the substrate, and the integration density of the storage device is improved.

The embodiment of the present application relates to the field of energy storage technology, and provides an energy storage boost converter box, including: a box body, the box body includes a control area and a converter area, an isolation plate is arranged between the control area and the converter area, the control area is used to set a control circuit, and the converter area is used to set a first converter and a second converter; the control circuit includes: a first circuit breaker, a second circuit breaker, a first fuse, a second fuse, a first relay, a second relay, a third relay and a fourth relay; the first circuit breaker is arranged above the second circuit breaker through a first bracket; the first fuse and the second fuse are arranged above the first relay, the second relay, the third relay and the fourth relay through a second bracket. The energy storage boost converter box provided by the embodiment of the present application is at least conducive to realizing a high degree of integration of the energy storage system.

The utility model relates to an off-grid inverter, which belongs to the technical field of inversion devices and comprises a casing and a main board arranged on the bottom wall of the casing, the main board is sequentially provided with a PV module, an inversion module, a DC-DC module and a battery module along the transverse direction, the front side of the PV module is provided with an AC module, the main board is provided with a copper bar jumper wire and a copper sheet, and the DC-DC module is connected with the battery module. The mainboard is connected with the PV module and the AC module through copper bar jumper wires, and the mainboard is connected with the battery module through a copper sheet. Wherein the PV module is a photovoltaic input module, the DC-DC module is a DC transformation module, and the AC module is an AC output module. According to the utility model, the PV module, the inversion module, the DC-DC module and the battery module are sequentially arranged along the transverse direction of the mainboard, the mainboard is connected with the PV module and the AC module through the copper bar jumper wire and is connected with the battery module through the copper sheet, and the inverter adopts a wireless design, has the advantages of compact structure, simplicity, order and convenience in wiring, and can improve the production efficiency.

The invention discloses an OFPGA chip packaging structure, which comprises an OFPGA silicon chip main body and a glass substrate, TGV through holes, fine pitch waveguides and coupling gratings are arranged on the glass substrate, and the OFPGA silicon chip main body and the glass substrate are bonded through micro salient points and covalent bonds to realize mechanical fixation and signal interconnection; the glass substrate realizes vertical electrical interconnection through high-density TGV through holes, optical signal transmission is realized through fine-pitch waveguides and coupling gratings, and the micro convex points are metal convex structures formed on the glass substrate. The space utilization rate is greatly increased; ultra-short-distance electric signal transmission in the vertical direction is achieved through the high-density TGV through holes, and signal delay is greatly reduced; the thermal stress after bonding is effectively reduced by means of the similar thermal expansion coefficient characteristic of the glass substrate and the silicon chip, and the stability of photoelectric signal separation transmission is ensured by combining high-precision matching interconnection of the TGV through holes and the micro convex points.

The invention relates to the technical field of semiconductor device preparation, and discloses a silicon-based heterogeneous device monolithic integration method and a silicon-based heterogeneous device monolithic, and the method comprises the steps: depositing a dielectric material on the surface of a silicon substrate, forming an isolation groove above an N well and a P well, and forming an epitaxial lamination in the groove; depositing a hard mask layer and carrying out graphical process treatment, forming a reserved mask layer above the epitaxial lamination layer, and then preparing two different types of vertical devices in the isolation groove; depositing a dielectric material in the isolation groove, and exposing the surface of the vertical device in an external environment by adopting a sinking process; hKMG deposition and graphical process processing are carried out on the surface of the vertical device to form a high-K metal gate, then interlayer dielectric deposition is carried out to form an interlayer dielectric layer, through hole etching is carried out on the interlayer dielectric layer, and conductive metal is filled to form a silicon-based heterogeneous device single chip. According to the method, high-density integration of different types of vertical devices is realized, and the performance, the reliability and the integration degree of the device are remarkably improved.

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array comprising a plurality of first semiconductor columns; forming first word lines, each first semiconductor column being connected with a corresponding first word line and a first bit line; forming a second transistor array on the first transistor array, the second transistor array comprising a plurality of second semiconductor columns, the first semiconductor columns and the second semiconductor columns corresponding to each other; and forming second word lines and second bit lines, each second semiconductor column being connected with a corresponding second word line and a second bit line, so as to form a 2T0C semiconductor structure, and the capacitor process in the manufacturing process of the semiconductor structure can be simplified.

The invention provides a preparation method of a transistor, the transistor and a semiconductor device. The preparation method comprises the following steps: forming a stack structure on a semiconductor substrate; the stacking structure is etched to form a plurality of fin-shaped structures, the fin-shaped structures are sequentially arranged in the first direction, and a first groove is formed between any two adjacent fin-shaped structures in the fin-shaped structures; forming a first side wall covering the side walls of the plurality of fin-shaped structures in the first groove; etching the semiconductor substrate below the first groove to obtain a second groove; depositing a dielectric material in the first trench and the second trench to form an isolation structure; removing the first side wall to separate the isolation structure and the plurality of fin-shaped structures to obtain a first semiconductor structure; a plurality of first transistors are formed based on the plurality of fin-shaped structures in the first semiconductor structure, the isolation structure is used for electrically isolating any two adjacent first transistors in the plurality of first transistors, and the polarities of any two adjacent first transistors are the same or different.

The utility model provides a kind of multi-channel high integration low-cost tile type transmitting assembly, including tile type shell, input interface, microstrip line located in tile type shell interior and input interface are sequentially connected, microwave composite multilayer board, two branch networks are connected on microwave composite multilayer board and with microstrip line output end connection, first drive power amplifier, second drive power amplifier are respectively connected with the two output ends of two branch networks, first eight branch networks are connected with the output end of first drive power amplifier, second eight branch networks are connected with the output end of second drive power amplifier, 16-way transmitting channel and radio frequency output port connected with transmitting channel output end are respectively connected with the output end of first eight branch networks, second eight branch networks, the number of radio frequency output port is 16.The utility model is X frequency band 16 channel tile type high integration, high reliability, high consistency and with power amplification, numerical control phase shift and output detection etc. The utility model discloses a kind of multi-channel high integration low-cost tile type transmitting assembly, including tile type shell, output interface, microstrip line located in tile type shell interior and output interface are sequentially connected, microwave composite multilayer board, two branch networks are connected on microwave composition multilayer board and with microstrip line output end connection, first drive power amplifier, second power amplifier are respectively connected with the two output ends of two branch networks, first eight branch networks is connected with the output end of first drive power amplifier, second eight branch networks is connected with the output end of second drive power amplifier, 16-way transmitting channel and radio frequency input port connected with transmitting channel output end are respectively connected with the output end of first eight branch networks and second eight branch networks, the number of radio frequency input port is 16.

The invention provides an energy storage container staggered battery rack structure capable of meeting high integration density. The energy storage container staggered battery rack structure comprises a plurality of stand column sets arranged in an arrayed mode, a plurality of parallel battery rack guide rails fixedly arranged on the stand column sets at equal intervals and upper and lower limiting pieces arranged behind battery packs. The battery rack guide rail comprises an L-shaped guide rail, a baffle arranged on the L-shaped guide rail and fixing pieces arranged at the two ends of the L-shaped guide rail. The L-shaped guide rail is used for placing the battery pack, the baffle prevents the battery pack from deviating during installation, and the fixing piece prevents the battery pack from falling off in the transportation process; the up-and-down limiting pieces are used for up-and-down limiting of the battery pack, so that the battery pack is prevented from violently jumping in the transportation process; the battery rack guide rails on the adjacent upright post groups are staggered up and down; and the battery packs on the adjacent upright post groups are arranged back to back. By utilizing the depth difference between the battery module box body and the bottom plate, the battery rack guide rails are arranged up and down in a staggered manner, so that the integration density of the energy storage container in height and width is improved.

The embodiment of the present disclosure relates to the field of semiconductor, and provides a magnetic memory structure and a memory, which comprises: a plurality of stacked magnetic storage units, and the magnetic storage unit at least comprises: a first transistor, the first transistor comprises a gate, the gate is used for connecting a control line, and one terminal of a source or a drain of the first transistor is used for connecting a first signal line; a magnetic tunnel junction, a bottom of the magnetic tunnel junction is used for connecting the other terminal of the source or the drain in the first transistor, and a top of the magnetic tunnel junction is used for connecting a second signal line, wherein the magnetic tunnel junction extends along the stacking direction of the magnetic storage unit; and the magnetic tunnel junctions in the plurality of stacked magnetic storage units are connected to the same second signal line, so that the integration density of the magnetic memory structure is improved.

This invention discloses a memory device and its fabrication method, belonging to the field of semiconductor manufacturing technology. By employing a composite functional layer containing group III nitrides and co-doped metals, and directly depositing the film at room temperature using magnetron sputtering, suitable microstructures and defect distributions can be formed within the functional layer during growth. This allows the device to achieve stable resistive state transitions without additional electroforming processing, effectively reducing the device's operating voltage and significantly improving its reliability and state consistency under small-size conditions. The room-temperature magnetron sputtering fabrication method eliminates the need for high-temperature deposition or high-temperature annealing, allowing for strict control of the process temperature to meet the thermal budget requirements of CMOS back-end processes. This enables three-dimensional monolithic integration with logic circuits, simplifying the fabrication process, reducing process complexity, effectively lowering manufacturing costs, and increasing integration density.

An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device in embodiments of this application includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.

The invention relates to a micro-nano protection array device and a preparation method thereof, and belongs to the field of electromagnetic field protection. The electromagnetic interference protection device solves at least one problem that an existing electromagnetic interference protection device is difficult to meet the protection requirement of a high-density integrated and / or miniaturized electronic system for strong electromagnetic interference and is difficult to meet the protection requirement for narrow-band high-frequency electromagnetic interference. The invention discloses a preparation method of a micro-nano protection array device, the micro-nano protection array device comprises a graphical array structure formed by metal grids, and the preparation method comprises the following steps: S1, providing a sapphire substrate; s2, drawing a layout, and manufacturing a mask plate; s3, coating photoresist, forming a photoresist pattern through photoetching and developing, and depositing a metal strip line on the sapphire substrate; and S4, removing the photoresist to form the metal grid. According to the invention, high-density miniaturization and large-area integration of the electromagnetic protection device are realized, the electromagnetic interference protection capability of a unit area is improved, and the working frequency upper limit of electromagnetic interference protection is improved.

The invention discloses a multi-layer gate analog CMOS process edge stress optimization integration method and a low voltage coefficient polycrystalline capacitor. The method steps include: 1) forming an N-type well in a low voltage coefficient integrated dual polycrystalline capacitor area, and forming a self-aligned P-type well in an area outside the N-type well; 2) depositing a polycrystalline film layer of a lower electrode of the low voltage coefficient integrated dual polycrystalline capacitor; 3) depositing a first layer of dielectric of the dual polycrystalline capacitor, and realizing the production of an edge protection layer of the lower electrode of the dual polycrystalline capacitor; 4) depositing a capacitor dielectric layer, and completing the production of a capacitor dielectric layer structure; the low voltage coefficient polycrystalline capacitor includes a P-type substrate, a P-type epitaxial layer, an N-type well, a self-aligned P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline film layer, a silicon dioxide dielectric layer, a capacitor dielectric layer, a low dielectric coefficient filling film layer, a metal interconnect film layer, and a protective dielectric passivation layer outside a top metal bonding area; the patent improves the edge effect of the dual polycrystalline capacitor and reduces the mechanical stress of the integrated dual polycrystalline capacitor.

The invention discloses a phase change storage material and device based on two-dimensional elementary bismuthene. The chemical component of the phase change storage material is bismuth elementary substance, and the melting point is lt; 300 DEG C; an amorphous phase of the material is of a long-range disordered atom arrangement structure, a local structure is mainly a defective octahedron and has a four-membered ring and five-membered ring structure, the coordination number of most atoms is 3, and an energy band structure has no band gap; a crystal phase of the two-dimensional bismuthene material has a buckling hexagonal honeycomb layered structure, adjacent layers are connected with each other through Van der Waals force, and an energy band structure has a band gap. According to the invention, the two-dimensional elemental bismuthene is used as a phase change functional layer material, so that the component segregation phenomenon in the use process of the device can be physically and essentially eliminated, and meanwhile, the ultrathin size and the low melting point characteristic of the material have the advantages in the aspects of high-density integration and low-power-consumption operation of the phase change memory device.

The application provides a two-dimensional semiconductor stacked device structure and a preparation method thereof, and realizes three-dimensional vertical stacking of a two-dimensional semiconductor device through a first interlayer dielectric layer and a second interlayer dielectric layer bonding process, effectively solves the problems of organic residue introduction, material folding and fracture and other problems commonly seen in the traditional two-dimensional semiconductor film transfer process, thereby significantly enhancing the integrity and long-term working stability of the stacked structure. At the same time, a high-efficiency interlayer isolation barrier is constructed by using the dielectric layer of the bonding interface, high-efficiency electrical isolation between the two two-dimensional semiconductor layers is realized, the threshold voltage crosstalk problem in the existing stacked structure is solved, independent and accurate adjustment of the threshold voltage of the upper and lower layer transistors is realized, and greater flexibility is provided for device performance optimization.

The application relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, a first transistor comprising a first channel in the substrate and a first end on the surface of the substrate, the first end being used for connecting with a first type of storage unit, and a second transistor comprising a second channel in the substrate and a second end on the surface of the substrate, the second end being used for connecting with a second type of storage unit, and the width of the second channel is greater than that of the first channel. The application can make the manufacturing process of the first transistor compatible with that of the second transistor, and simplify the manufacturing method of the semiconductor structure. Furthermore, the application is helpful to improve the integration density of the storage unit with the first transistor and / or the second transistor in the memory, and reduce the size of the storage unit, and lays a foundation for expanding the application field of the memory.

The application discloses a waveguide bending structure based on a subwavelength Micallan lens and belongs to the technical field of integrated optics, which comprises an input port, an output port, a subwavelength Micallan lens, a first subwavelength taper coupler, a second subwavelength taper coupler, an insulator cladding, an insulating layer and a substrate layer; the input port and the output port are symmetric about the center of the subwavelength Micallan lens; the first subwavelength taper coupler, the subwavelength Micallan lens and the second subwavelength taper coupler are all composed of a periodic subwavelength grating structure; the subwavelength Micallan lens is composed of basic lens units arranged periodically with a large duty cycle on both sides and a small duty cycle in the middle, and the effective refractive index distribution thereof satisfies the reciprocal function of the hyperbolic cosine; the structure can realize low-loss and high-isolation optical path bending in a short propagation distance, break through the physical restriction between the bending radius and the bending loss, and is suitable for photonic integrated circuits and optical information processing chips.

This invention relates to the field of passive radio frequency microwave devices, specifically to a filter-type Wilkinson chip power divider and its fabrication method. The divider includes an aluminum nitride substrate, an adhesion layer, a metal ground plane, a buried dielectric layer, three-dimensional interdigitated tantalum nitride resistors, a filter power divider metal structure, and a passivation layer. The adhesion layer is disposed on the surface of the aluminum nitride substrate, the metal ground plane is disposed on the surface of the metal adhesion layer, the buried dielectric layer covers the surface of the metal ground plane, and the buried dielectric layer has resistor trenches and interconnecting vias etched inside. The three-dimensional interdigitated tantalum nitride resistors are disposed within the resistor trenches and electrically connected to the metal ground plane through the interconnecting vias. The filter power divider metal structure is disposed on the surface of the buried dielectric layer, and the passivation layer is deposited on the surface of the filter power divider metal structure. This invention achieves integrated power distribution, passband filtering, port isolation, and harmonic suppression functions through a single-chip structure. Compared to traditional modular solutions, it significantly reduces the device size and can meet the miniaturization and high integration requirements of radio frequency front-ends.

This disclosure relates to an interfacing board and its grounding structure, packaging module, and electronic device. The grounding structure includes a plurality of first metal lines extending along a first direction and spaced apart in a second direction, and a plurality of second metal lines extending along the second direction and spaced apart in the first direction; the plurality of first metal lines intersect with the plurality of second metal lines. This grounding structure achieves higher integration density, improved shielding effect, and reduced crosstalk by arranging the plurality of first and second metal lines in the first and second directions.

A semiconductor device is provided, the semiconductor device comprising: a lower insulating layer; a lower channel pattern on the lower insulating layer; an upper channel pattern; a lower gate structure surrounding the lower channel pattern; an upper gate structure surrounding the upper channel pattern; a first lower source / drain pattern on the lower gate structure; a first upper source / drain pattern on the upper gate structure; a first spacer on the first upper source / drain pattern; a first source / drain contact extending through the first spacer and the first upper source / drain pattern and connected to the first upper source / drain pattern and the first lower source / drain pattern; a second lower source / drain pattern on the lower gate structure; a second upper source / drain pattern on the upper gate structure; a first interlayer dielectric on the second upper source / drain pattern; and a second source / drain contact extending through the first interlayer dielectric and connected to the second upper source / drain pattern.

The present application relates to a silicon-based detector, which designs and processes the p+ injection area of the device without changing the thickness of the substrate, and performs carbon injection, increases the area of generating electron-hole pairs and avalanche effect, thereby increasing the breakdown voltage of the device and improving the anti-radiation performance of the device. In addition, the present application introduces a deep trench ring isolation structure. Compared with the traditional silicon-based detector, the protection ring does not need to be obtained by ion implantation, the influence of the edge electric field on the performance of the device is reduced, and the dead area can be smaller when the array is formed, the integration density is improved, and the detection efficiency is improved. The present application also relates to a preparation method of the silicon-based detector.

The application discloses a terahertz neural synapse memorization device and a preparation method thereof. The terahertz neural synapse memorization device comprises a substrate, an active region formed on the substrate, two electrodes in the form of interdigital electrodes, the two electrodes comprising test parts and finger parts, the test parts of the two electrodes being respectively formed on two sides of the active region, the finger parts being arranged on the active region in a staggered manner at a certain interval, and the interval between adjacent finger parts being controlled at a nanometer level; the two electrodes are respectively used as a presynaptic end and a postsynaptic end of a neural synapse, a high-frequency voltage signal is applied to the presynaptic end as an excitation source of the neural synapse, and a current signal response of the postsynaptic end is collected, so that a terahertz neural morphological calculation function is realized.

The present invention relates to a positive electrode active material and a lithium secondary battery containing the same, and more specifically, to a positive electrode active material, a positive electrode containing the above-mentioned positive electrode active material, and a lithium secondary battery using the above-mentioned positive electrode, wherein the above-mentioned positive electrode active material is a bimodal positive electrode active material comprising a first lithium composite oxide as small particles and a second lithium composite oxide as large particles, wherein the slope of the concentration gradient of cobalt in the above-mentioned small particles and the above-mentioned large particles decreasing from the surface portion to the center portion is controlled, thereby uniformly improving the particle stability of the above-mentioned small particles and the above-mentioned large particles.

The embodiment of the invention provides a semiconductor device and a preparation method thereof, a memory unit, a read-write method and a memory. The semiconductor device comprises a substrate and a laminated structure arranged on the substrate, wherein the laminated structure comprises first semiconductor layers and insulating layers which are alternately arranged; the first hole structures and the second hole structures penetrate through the laminated structure and are arranged in the first direction, and the first direction is parallel to the substrate; a memory cell including a first sub-structure disposed in the first pore structure and a second sub-structure disposed in the second pore structure; the first substructure comprises a first gate structure of the read transistor and a capacitor, and the first substructure is located in the first semiconductor layer; the second substructure comprises a first transistor and a second transistor, and the second substructure is located in the first semiconductor layer.

The invention relates to a production process of a capacitor chip, which comprises the following steps of: etching a silicon substrate to form a bottle-shaped groove structure, and forming an upper electrode and a lower electrode with convex shapes in a groove through the steps of depositing silicon crystal grains, implanting ions, forming an intermediate dielectric layer, etching the intermediate dielectric layer and depositing a conductive layer; and hole etching is carried out on gaps among the three adjacent trench capacitors, and a heat dissipation insulating material is deposited to form a heat dissipation isolation structure. According to the invention, the bottle-shaped groove is formed through two etching processes, and the capacitance value of the chip is further improved in combination with the convex structure of the electrode; in addition, by forming a heat dissipation isolation structure, the chip integration density is improved, the heat dissipation performance of the capacitor chip is improved, and meanwhile the electrical insulation performance between capacitors is further improved.

An electronic assembly and a whole-cabinet server are provided. The electronic assembly includes a pair of processing elements, a chip cooling element, and a power supply cooling element. The pair of processing elements are disposed in a stacked manner in a thickness direction. Each processing element includes a carrier board, a chip, and a power supply unit. The carrier board has a first side and a second side opposite to each other in the thickness direction. The chip is disposed on the first side of the carrier board. The power supply unit is electrically connected with the carrier board. The chip cooling element is in contact with the chip. The power supply cooling element is in contact with the power supply unit, wherein the chip cooling element or the power supply cooling element is disposed between the pair of processing elements.