194results about How to "Performance of was minimized" patented technology

A finger-mapped gesture system is a user interface method and apparatus for rapid data input on a touch-sensitive surface. The user gestures by holding the hand stationary relative to the surface and moving the fingers primarily by extension and flexion on the surface. Each finger gestures on a gesturing area instead of selecting among keys. Individual gestures are constructed from finger actions that each independently parameterize the gesture. In combination, the particular fingers gesturing and the parameters that the fingers gesture indicate the input that the user intends. On devices that do not directly identify fingers, fingers are identified via a finger map that, after calibration to a person's hand, associates each finger with a gesturing area. Gestures are otherwise independent of where they are performed, freeing users from having to look at their fingers to target visual elements. The system is optimized for rapid character data entry.

Generalized learning rules may be implemented. A framework may be used to enable adaptive signal processing system to flexibly combine different learning rules (supervised, unsupervised, reinforcement learning) with different methods (online or batch learning). The generalized learning framework may employ non-associative transform of time-averaged performance function as the learning measure, thereby enabling modular architecture where learning tasks are separated from control tasks, so that changes in one of the modules do not necessitate changes within the other. The use of non-associative transformations, when employed in conjunction with gradient optimization methods, does not bias the performance function gradient, on a long-term averaging scale and may advantageously enable stochastic drift thereby facilitating exploration leading to faster convergence of learning process. When applied to spiking learning networks, transforming the performance function using a constant term, may lead to non-associative increase of synaptic connection efficacy thereby providing additional exploration mechanisms.

Light efficient packaging configurations for LED lamps using high refractive index encapsulants. The packaging configurations including dome (bullet) shaped LED's, SMD (surface mount device) LED's and a hybrid LED type, including a dome mounted within a SMD package. In another embodiment used with SMD LED devices a relatively small semi-hemispherical “blob” of HRI encapsulant surrounds the LED chip with the remainder of the SMD cavity filled with conventional encapsulant. The packaging configurations increase the LED's light emission efficiency at a reasonable cost and in a commercially viable manner, by maximizing the light efficiency while minimizing the amount of high refractive index encapsulant used.

A network function virtualization device includes at least one network function virtual machine; and a network function flow switch configured to receive flows and to switch the flows to the at least one network function virtual machine, and a network functions virtualization method for applying the virtualized network function to the flows.

In a method for selecting a transmission target terminal in a zero-forcing beamforming algorithm, information about a channel capacity of each terminal is received from all K terminals. A terminal with a largest channel capacity is selected as an initial transmission target terminal. A determination is made as to whether the number of currently selected terminals, i, is equal to the predefined number N. If the number of currently selected terminals, i, is different from the predefined number N, information about channel capacities of remaining terminals except previously selected transmission target terminals is received until i is equal to N and a terminal with a largest channel capacity is selected as a transmission target terminal.

A data retention system has master-slave latches for holding data in an active mode; a data retention latch for preserving data read from the master latch in a sleep mode, which is connected to the master latch in parallel with the slave latch; a first multiplexer for receiving data externally provided and feedback data from the data retention latch, and selectively outputting either the data externally provided or the feedback data to the master latch in response to a first control signal; and a second multiplexer for transferring output data of the master latch to the slave latch and the data retention latch in response to a second control signal, wherein power for the data retention latch remains turned on in the sleep mode, while power for the data retention system except for the data retention latch is turned off. The data retention latch may include gate transistors controlled by the second control signal and a data holding unit having transistors for holding data transferred through the gate transistors, wherein the gate transistors and the transistors in the data holding unit have a high-threshold voltage.

To provide a storage system capable of minimizing a performance deterioration, saving power consumption, and realizing a high reliability. A storage system according to the present invention includes a computer, a storage apparatus 1 connected with the computer, and a storage management apparatus connected to the storage apparatus, the storage apparatus including a hard disk unit to control a data write operation and a data read operation between the computer and the hard disk unit, and control on/off states of power supply of the hard disk unit on a group basis, and the system management apparatus collecting running information about the computer and computer execution job information for each computer, and determining an on/off time of the power supply of the hard disk unit on the group basis to record the collected information and the on/off time of the power supply on the group basis.

A method and system for arbitrating among memory access commands from clients seeking access to a DRAM or other memory, and an arbiter for use in implementing such method or system. When arbitrating among competing commands that include at least one command of the same read/write type as the current command, the arbiter selects a command of the same read/write type as the current command. In a wait mode, when arbitrating among a set of the commands that includes no command of the same read/write type as the current command, the arbiter prevents each command in the set from reaching the memory. Preferably, after operating in the wait mode for a limited time, the arbiter enters another arbitration mode in which it can select a command of the opposite read/write type as the current command. Preferably, the arbiter is implemented to be operable in any of multiple operating modes. For example, it can have separately programmable wait times for “read to write” and “write to read” situations. Preferably, the arbiter monitors for occurrence of potential page fault conditions.

A system and method for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

A method for puncturing a Low Density Parity Check (LDPC). The method includes a) setting a codeword length and the total number of bit nodes to be punctured; b) selecting a check node (or check nodes) with highest priority excluding check nodes completely checked in a current round; c) selecting a bit node (or bit nodes) with a highest priority excluding bit nodes completely checked among bit nodes connected to the selected check node (or check nodes); d) determining whether the selected bit node is a bit node to be punctured, that is, it is not systematic, not set by a puncturing prohibition flag; e) puncturing an associated bit node if the selected bit node is the bit node to be punctured, setting unpunctured bit nodes connected to the selected check node by a puncturing prohibition flag, decreasing the number of remained bit nodes to be punctured by 1 and increasing the number of connected punctured node of associated check node by 1; f) determining whether the number of remaining bits to be punctured is greater than 0; and g) returning to step b) if the number of remaining bits to be punctured is greater than 0, and ending a puncturing process if the number of remaining bits to be punctured is not greater than 0.

Systems and methods are provided for implementing a persistent battery system shutdown condition when a battery pack voltage level drops below a predetermined minimum acceptable operating voltage threshold that is above a pre-determined permanent failure operating voltage threshold at which the battery pack is permanently disabled. The disclosed systems and methods may be implemented such that shutdown portion of the power-consuming components of the information handling system are not allowed to be restarted until external power has been first provided and applied to at least partially recharge the battery cells of the battery pack to a battery voltage level that is above the minimum acceptable operating voltage threshold and/or when sufficient external power is applied to power the information handling system and at the same time charge the battery cells of the battery pack.

An architecture is described for performing memory management in a virtualization environment. Multiple levels of caches are provided to perform address translations, where at least one of the caches contains a mapping between a guest virtual address and a host physical address. This type of caching implementation serves to minimize the need to perform costly multi-stage translations in a virtualization environment.

The present invention describes an efficient and fast framework for implementing table-valued functions (TVF's) in a relational database server. The framework provides desirable extensibility properties and has the ability to minimize performance degradations by integrating tightly with the optimization infrastructure in a query processor. The present invention also enables a managed execution environment (MEE) such as the Common-Language-Runtime (CLR), to efficiently and dynamically extend the logic of the database engine with user-supplied code.

In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

Provided are a method and an attestation system for preventing an attestation replay attack. The method for preventing an attestation replay attack in an attestation system including an attestation target system and an attestation request system, the method including: measuring associated components when an event that affects the integrity of the attestation target system occurs; perceiving own identity information and verifying the perceived identity information; extending the measured component and the identity information into a register and logging the measured component and the identity information; generating an attestation response message including values of the log and the register when an attestation request message is received from the attestation request system; and transmitting the generated attestation response message to the attestation request system. Therefore, the method and an attestation system may be useful to provide an additional simple mathematical operation in verifying an attestation message by preventing an attestation replay attack, and thus to minimize performance degradation in the attestation system, compared to the conventional attestation processing mechanisms.

A system, apparatus, and method are provided which allows for reducing power consumption in dynamic voltage and frequency scaled processors while maintaining performance within specified limits. The method includes determining the off-chip stall cycle in a processor for a specified interval in order to characterize a frequency independent application workload in the processor. This current application workload is then used to predict the application workload in the next interval which is in turn used, in conjunction with a specified performance bound, to compute and schedule a desired frequency and voltage to minimize energy consumption within the performance bound. The apparatus combines the aforementioned method within a larger-scale context that reduces the energy consumption of any given computing system that exports a dynamic voltage and frequency scaling interface. The combination of the apparatus and method form the overall system.

Workload type to be managed by a database management system (DBMS) is a key consideration in tuning the DBMS. Allocations for resources, such as main memory, can be very different depending on whether the workload type is Online Transaction Processing (OLTP) or Decision Support System (DSS). The DBMS also experiences changes in workload type during the normal processing cycle of the DBMS. It would be preferable for the database administrators to recognize the significant shifts of workload type that demand reconfiguring the DBMS to maintain acceptable levels of performance. Disclosed is a workload type classifier module, used by a DBMS, for recognizing workload types so that the DBMS may then manage or adjust its performance and reconfigure its resources accordingly. The classifier may be constructed based on the most significant workload characteristics that differentiate OLTP from DSS. The classifier is then used for identifying changes in workload types contained in a workload.

A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

By releasing a part of execution environment that contains a leaked resource, a failure is avoided while the remaining part of execution environment in a memory and the like prevents performance degradation that results from a cold cache. This invention provides a highly available application operation method for replacing a first application (App1) which receives a processing request with a second application (App2). The method includes the steps of: invoking the first application (App1) and forwarding the processing request to the first application (App1); when a given condition is met, invoking the second application (App2) and forwarding a new processing request to the second application (App2); and, when the first application (App1) completes the processing request after the second application (App2) is invoked, stopping the first application (App1).

A system for providing hosts with a capability to determine which threshold rule of a plurality of threshold rules to use based upon threshold consensus. For example, the system would address a configuration case of several hosts sharing an output port of a fabric via zoning and that port being connected to a single port of a storage controller. If one host is executing lower priority jobs and its threshold is much higher than another host with higher priority jobs and a lower threshold, and the storage controller recognizes that several hosts are sharing the same storage controller port, the consensus will be to ignore the threshold of the first host and to use the threshold of the second host to prevent performance degradation in the system.

An efficient bit interleaving scheme for a multi-band OFDM ultra-wideband (UWB) system. The encoded bits of the multi-band OFDM system are interleaved within each OFDM symbol and across OFDM symbols. The bit interleaving scheme minimizes performance degradation due to groups of contiguous OFDM tones experiencing a poor SNR caused by the frequency selective channel, exploits the frequency diversity across sub-bands, randomizes the effect of co-channel interference from simultaneously operating un-coordinated piconets, and randomizes the impact of generic narrow-band interferers present within the UWB spectrum.