149 results about "Memory management unit" patented technology

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention provides an accelerator and a request processing method, which can be applied to the technical field of computers. The accelerator comprises: a computing unit configured to send an access request to a target virtual address to a memory management unit; the memory management unit comprises an address translation buffer module, and the memory management unit is configured to respond to the received access request and search a corresponding physical page number in the address translation buffer module according to the target virtual address so as to determine a physical address; wherein the address translation buffer module comprises a plurality of buffer units, and the address translation buffer module is configured to determine a target buffer unit from the plurality of buffer units according to a virtual base address in a target virtual address; and based on address identification information in the target virtual address, searching a physical page number corresponding to the target virtual address from physical page numbers corresponding to the at least two different virtual base addresses stored in the target buffer unit to determine a physical address.

The invention relates to the field of memory management, and provides a memory allocation method and device for a mobile terminal system. The method comprises the following steps: dividing a DDR (Double Data Rate) memory in the mobile terminal into a plurality of physical blocks through a memory management unit; uniquely numbering the plurality of physical blocks, and establishing a mapping relationship between the virtual address used by the mobile terminal system and the physical numbers corresponding to the plurality of physical blocks through the memory management unit; after receiving a memory allocation request, judging whether a target physical block indicated in the memory allocation request belongs to a single channel of the 16-bit memory; and if the target physical block does not belong to the single channel of the 16-bit memory, remapping a physical number in the memory allocation request into an equivalent physical number in a single channel range, and importing the to-be-allocated data into a corresponding 16-bit memory space through a memory management unit based on the mapping relationship and a virtual address corresponding to the equivalent physical number. The memory allocation efficiency is improved by realizing optimal allocation of the 16-bit memory.

Provided is an accelerator for accelerating batch large language model (LLM) inference via key-value cache compression. An accelerator, according to one embodiment, may comprise a plurality of compute cores. Here, each of the plurality of compute cores may comprise a plurality of processing units for processing an LLM inference operation on a per-token basis, and a direct memory access unit for managing operations of reading weights from a memory and writing key-value activation data back to the memory. In addition, the direct memory access unit may comprise a compression engine for managing online compression of the key-value activation data when the key-value activation data is written to the memory, a decompression engine for decompressing the compressed key-value activation data retrieved from the memory, and a memory management unit for managing reading and writing of the compressed key-value activation data in the memory.

A system controls access to a physical address (PA) space. The system includes multiple system resources addressable within the PA space, and multiple processing circuits executing multiple virtual machines (VMs). A given region of the PA space is dedicated to addressing the VMs. The system also includes multiple memory management units (MMUs) coupled to corresponding processing circuits. A given MMU is operative to translate a virtual address indicated in an access request from a processing circuit into a requested PA that is accessible by the processing circuit according to a configurable setting of the given MMU. The system further includes multiple memory protection units (MPUs). A given MPU, which is coupled to a target system resource allocated with the requested PA, is operative to grant or deny the request based on information indicating whether the requested PA is accessible to a requesting VM executed on the processing circuit.

A neural processing device and a method for using shared page table thereof are provided. The neural processing device including at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to exchange data between the at least one neural processor and the shared memory, comprises at least one processing unit each of which included in each of the at least one neural processor and configured to provide logical addresses, a memory management unit configured to receive and translate the logical addresses into physical addresses, and a physical memory accessible by the physical addresses, wherein the memory management unit comprises a shared page table that has translation information between the logical addresses and the physical addresses and is shared by at least one process with each other.

The invention provides a memory management method, a memory management unit, a chip and electronic equipment. The memory management method comprises the following steps: receiving a command from main equipment; matching the command with a tag array to obtain a matching result; if matching succeeds, corresponding read address information is generated according to the hit tag, a first memory is accessed according to the read address information to obtain corresponding cache line page table information, and the virtual address information is converted into physical address information according to the cache line page table information; and if the matching fails, initiating a page table reading command for accessing the second memory to obtain corresponding page table information according to the command, obtaining replacement cache line information corresponding to the page table information in the first memory, writing the page table information into the first memory according to the replacement cache line information, and updating the tag array. According to the method, the cache line replacement strategy is preset, so that the hit rate of the page table is increased, and the power consumption and the area of the IOMMU are effectively reduced while the high-performance application requirement is met.

A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.

An apparatus to facilitate processing in a multi-tile device is disclosed. The apparatus comprises a plurality of processing tiles, each including a memory device and a plurality of processing resources, coupled to the device memory, and a memory management unit to manage the memory devices in each of the plurality of tiles to perform allocation of memory resources among the memory devices for execution by the plurality of processing resources.

A security module of a processor manages the lifecycle of a device interface of an input / output (I / O) device in a virtualized environment in a secure and trusted manner. For example, the security module is configured to bind a device interface of the I / O device interface to a virtual machine (VM). In response to binding the device interface, the security module is configured to certify at least one of the device interface and the I / O device. In response to certifying at least one of the device interface and the I / O device, the security module is configured to configure an input / output memory management unit (IOMMU) and memory resources associated with the VM.

The embodiment of the invention provides a memory access method and system of a virtual machine and direct connection equipment, the memory access method of the virtual machine is applied to the direct connection equipment of the virtual machine, an equipment memory management unit is configured on the direct connection equipment, and a system memory management unit is configured on a host machine of the virtual machine; the method comprises the steps that a memory access command is received, and the memory access command carries a virtual address of a virtual machine to be accessed; driving an equipment memory management unit to access a system memory management unit so as to perform address conversion on the virtual address of the to-be-accessed virtual machine, and determining a to-be-accessed host physical address; and the direct connection equipment accesses the memory of the virtual machine according to the to-be-accessed host physical address. Through the dual-memory management unit, the conversion from the virtual address of the virtual machine to the physical address of the host is realized, and the complexity of address conversion is reduced.

A system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture, wherein the system comprises: a plurality of processor cores arranged within a processor structure and configured to perform computational tasks in parallel; a linking network that operationally connects the plurality of processor cores for data communication; a context capture unit connected to each of the plurality of processing cores and configured to monitor execution parameters such as instruction throughput, cache access behavior, memory latency, and data exchange characteristics between the cores, wherein the context capture unit generates context descriptors that are representative of the runtime execution conditions;a scheduling processor operationally connected to the context capture unit and configured to distribute computational tasks across the multitude of processor cores based on the generated context descriptors; and a memory management unit operationally connected to a hierarchical memory arrangement comprising multiple cache levels and main memory, the memory management unit being configured to dynamically allocate and migrate data segments across the hierarchical memory arrangement according to the context descriptors, thus achieving alignment between task execution and data locality.

The present application relates to devices and components, including apparatus, systems, and methods for scheduling delivery and execution of page fault or permission fault exceptions. A memory management unit may receive a virtual address associated with an execution mode and initiate a virtual-to-physical translation operation. The MMU may detect a first condition associated with a search of the virtual address in a translation lookaside buffer (TLB). In response to the detection of the first condition, MMU may start a timer. MMU may detect a fault exception associated with the translation operation of the virtual address and determine that a second condition is satisfied. In response to detecting the second condition, the MMU or the reorder buffer exception monitor may deliver the fault exception based on the timer.

The embodiment of the invention provides an accelerator, an input and output memory management unit and a related device and method, and the accelerator comprises the steps that a receiving unit sequentially receives a first translation request and a second translation request, and virtual page numbers corresponding to the first translation request and the second translation request are recorded in the same first page table item; the query unit queries whether a first page table item exists in a first translation backup buffer area of the first-level cache or not, if not, the first page table item is obtained from the outside of the first translation backup buffer area, and the first translation request is sent to the prefetching unit; and the duplicate removal unit associates the second translation request with the first translation request, and obtains a translation result from the first page table item after the query unit obtains the first page table item. And the prefetching unit initiates a prefetching operation after the prefetching training is completed, obtains a second page table item of the predicted translation request, and stores the second page table item into a second translation backup buffer area of the second-level cache. According to the scheme, the efficiency of virtual address translation can be improved.

The invention discloses a permission adjustment method, device and equipment and a computer readable storage medium, and is applied to the technical field of computing, and the method comprises the steps: obtaining the access frequency of a heap area in a virtual address, the number of errors of physical address permission detection, and the code exception jump condition; determining a corresponding control signal according to the access frequency, the error number and the code exception jump condition; the control signal comprises an authority change signal and a process freezing signal; dynamically adjusting the physical memory authority of the memory management unit according to the control signal; the dynamic adjustment includes adjusting read or write or execution permissions of the physical page, and disrupting an access sequence of the translation lookaside buffer cache. According to the method, the limitation that traditional static permission configuration cannot adapt to the dynamic running state of the process is solved; and the MMU cannot detect and block hostile attacks in real time, so that the safety and the flexibility of MMU authority management are improved.

The present application relates to an artificial intelligence chip, a method for virtual address conversion, a computing device, a computer readable storage medium and a computer program product. The artificial intelligence chip comprises: an address cache bank arranged before a memory management unit and comprising a plurality of address caches, the address cache bank being configured to perform hit and miss detection on virtual addresses associated with read / write requests from a plurality of computing units to obtain corresponding physical addresses; the memory management unit being configured to query virtual addresses missed by the address cache bank and provide the queried corresponding physical addresses to the address cache bank; and the plurality of computing units being configured to perform calculations and provide read / write requests to the address cache bank. The present application can significantly reduce arbitration conflicts between multiple requests and improve the conversion efficiency of virtual addresses to physical addresses and the performance of the chip.

The application relates to the field of memory management, and provides a memory allocation method and device of a mobile terminal system. The method comprises the following steps: dividing a DDR memory in the mobile terminal into a plurality of physical blocks through a memory management unit; numbering the plurality of physical blocks uniquely, and establishing a mapping relationship between a virtual address used by the mobile terminal system and a physical number corresponding to each of the plurality of physical blocks through the memory management unit; after receiving a memory allocation request, judging whether a target physical block indicated in the memory allocation request belongs to a single channel of 16-bit memory; if the target physical block does not belong to the single channel of 16-bit memory, remapping the physical number in the memory allocation request into an equivalent physical number within the single channel range, and guiding to-be-allocated data into corresponding 16-bit memory space based on the mapping relationship and a virtual address corresponding to the equivalent physical number through the memory management unit. The optimized allocation of 16-bit memory is realized, and the memory allocation efficiency is improved.

The invention relates to the technical field of power distribution Internet of Things, in particular to a power distribution Internet of Things area intelligent fusion terminal system which comprises a single physical processor, a first virtual machine, a second virtual machine, a virtual machine monitor and a single physical processor supporting hardware virtualization extension and an input and output memory management unit. The first virtual machine is specially used for power distribution monitoring services, running a real-time operating system, and processing fault recording and remote control tripping tasks; the second virtual machine is specially used for power utilization acquisition business, runs a non-real-time operating system and processes data reading and edge computing tasks; the virtual machine monitor runs on a single physical processor, and the virtual machine monitor realizes isolation of memory and equipment hardware between the first virtual machine and the second virtual machine through the input and output memory management unit. Redundancy of a control core is achieved so as to solve the problems of system reliability, control strategy and safety of an existing fusion terminal.

Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a TLB, comprising multiple TLB entries each comprising a tag and a plurality of data portions, and further comprises a memory management unit (MMU). The MMU is configured to receive a memory access request comprising a VA, and determine that a TLB access to the TLB for a page VA of the VA results in a miss. In response, the MMU generates a TLB entry, wherein the tag of the TLB entry comprises the page VA, the plurality of data portions comprises a corresponding plurality of page PAs, a first data portion thereof comprising a page PA corresponding to the page VA, and one or more second data portions thereof comprising corresponding PAs of next sequential page VAs following the page VA.

The invention provides a method and system for verifying a memory management unit and electronic equipment. The method comprises the following steps: receiving a command, wherein the command comprises virtual address information; dividing the memory according to a preset memory division strategy and the virtual address information to obtain a page table area and a data area; converting the virtual address information into corresponding physical address information through a reference model according to the page table area and the data area to obtain a first conversion result; converting the virtual address information into corresponding physical address information through the to-be-tested design according to the page table area and the data area so as to obtain a second conversion result; checking each signal in a conversion process of converting the virtual address information into the corresponding physical address information by the design to be tested to obtain a checking result; and judging according to the check result and a comparison result between the first conversion result and the second conversion result to obtain a verification result for the to-be-tested design. The verification method and device are high in universality and expansibility, and full, effective and efficient verification can be achieved.

Numerical control device capable of providing an interface that performs safe task control for adding an original function, wherein the numerical control device comprises: - a memory management unit that is set up to develop or initialize a program executed by a task in memory, analyze the program, and gather information about the program, - an execution time calculation unit that is set up to calculate an execution time of the task, - an execution condition setting unit configured to set an execution condition of the task based on the execution results of the memory management unit and the execution time calculation unit, - a task monitoring unit that is configured to monitor the state of a computing unit and to determine the computing unit to which the task is assigned, and - a task control unit that is configured to register and start the task in the assigned computing unit based on the execution condition.

This invention provides a method and computing system capable of enhancing memory protection related to the operating system kernel, thereby ensuring system security. The computing system provided by this invention may include: a processor configured to execute a guest virtual machine (VM), wherein an operating system (OS) runs on the guest VM, and an application (APP) runs on the OS. The kernel of the OS includes: a protection service module configured to receive at least one virtual address and first size information sent by a client of the APP; and a memory management unit (MMU) manager. The computing system further includes a virtual machine manager configured to receive the at least one virtual address and the first size information sent by the protection service module. The computing system also includes a host VM, which includes: a protection manager configured to receive and obtain a physical address array and second size information based on the at least one virtual address and the first size information to protect memory allocated by the kernel of the OS.

The embodiment of the invention provides an equipment fault processing method, a host, a computer program product and a storage medium. The operating system of the target host can run an error report driving program after receiving an interrupt signal sent by any root interface and used for triggering an error report mechanism; based on an error report driving program, obtaining an address translation exception record from an event queue maintained by a memory management unit; if the address translation exception record points to any virtual device connected to the root interface, calling a kernel mode drive program corresponding to the virtual device through an error report drive program; and controlling the target virtual machine served by the virtual equipment to be paused based on the kernel mode driving program. Therefore, when a single virtual device has a fault, the fault domain can be accurately controlled on the virtual machine served by the faulted virtual device, so that only the virtual machine served by the faulted virtual device is suspended, and the influence on other virtual machines running on the target host can be effectively avoided.

Provided in the embodiments of the present disclosure are a memory access method and system for a virtual machine, and a pass-through device. The memory access method for a virtual machine is applied to a pass-through device for the virtual machine, wherein a device memory management unit is configured on the pass-through device, and a system memory management unit is configured on a host of the virtual machine. The method comprises: receiving a memory access command, which carries a guest virtual address to be accessed; driving a device memory management unit to access a system memory management unit, so as to perform address translation on said guest virtual address to determine a host physical address to be accessed; and a pass-through device accessing a memory of a virtual machine on the basis of said host physical address. By means of dual memory management units, the translation from a guest virtual address to a host physical address is realized, thereby reducing the complexity of address translation.

This application discloses a method and apparatus for writing buffer data in a memory management unit, relating to the field of chip verification technology, and is invented to shorten verification time and improve verification efficiency. The method includes: traversing a page table to obtain the mapping relationship between virtual addresses and physical addresses recorded in the page table; filtering the mapping relationship according to a predetermined strategy to obtain a target mapping relationship; converting the target mapping relationship into a predetermined format to obtain a target mapping relationship; and writing the predetermined format target mapping relationship into a substitution bypass buffer in the memory management unit through a backdoor access function. This application is applicable to verification related to substitution bypass buffers.

The invention discloses a big language model security test data processing method and system, and relates to the technical field of memory management, the method comprises the following steps: obtaining test data in a big language model security test platform, the test data comprising multi-modal data, structured attack load data, long-term session state data and short-term temporary data; according to the test data, performing region division on a main memory space to obtain a plurality of initial functional regions; constructing a corresponding regional memory management unit in each initial functional region, the regional memory management unit being used for performing memory allocation according to a memory allocation strategy; and after memory allocation, allocating the test data to the corresponding initial function region, and processing the test data. According to the method, the memory can be allocated in combination with the functional region and the memory allocation strategy, so that the test data has enough memory space, the test data processing is realized, and the memory management reliability and the data processing efficiency are improved.

A memory processing system includes a processor, a main memory, and a MMU coupled to the processor and the main memory. The processor is used to generate a plurality of virtual addresses. The main memory includes a plurality of data corresponding to physical addresses in a main page table. The main page table is used to map the plurality of virtual addresses to the plurality of physical addresses. The memory management unit includes a TLB coupled to the processor and the main memory, a table walk unit coupled to the TLB and the main memory, and a merger coupled to the TLB and the processor. The TLB performs address translation by retrieving a physical address according to a virtual address from a first page table in the TLB or a second page table in the table walk unit or the main page table in the main memory.

The application relates to the field of data processing, and provides a multi-process DMA access method and device based on device end context recognition and a chip. The method comprises the following steps: when initiating a DMA operation, a target VF generates a DMA request containing a local virtual address of the target VF; a VFID corresponding to the target VF is extracted from the DMA request, a virtual function address conversion table in a terminal device is inquired according to the VFID, and an address mapping table is acquired; the local virtual address of the target VF is converted into a corresponding DVA through the address mapping table; a standard PCIe TLP is generated based on the converted DVA; and the TLP is sent to a host, so that an input / output memory management unit or an address conversion service on the host side converts the DVA into a host physical address HPA, and the DMA operation is completed. Through the front movement of the multi-process address conversion from the host side to the terminal device side, a more efficient DMA access path is realized without relying on a PASID.

A method includes executing, by a processor core, a first task; scheduling, by a scheduler, a second task to be executed by the processor core upon completion of executing the first task; responsive to scheduling the second task, providing, by the scheduler, a prewarming message to a memory management unit (MMU) coupled to the processor core; and responsive to receiving the prewarming message, fetching, by the MMU, a page table specified by a page table base of the prewarming message.

A method of preloading address translation information directly into cache memory of an IOMMU includes storing the address translation information in a register set of memory management input / output registers of an input-output memory management unit and loading the address translation information into cache memory of the input-output memory management unit. The address translation information includes a virtual address and a corresponding physical address of system memory of a computing system. The address translation information is sent by software being executed by a processor of the computing system. The address translation information is received directly from the processor.