319 results about "Memory management unit" patented technology

A memory management method and apparatus, and a computing device. The method is executed by a GMEM system. When receiving a physical memory range, a memory management unit operation function, and an accelerator device address of an accelerator device, the GMEM system configures a memory management unit operation function interface for the accelerator device, and a device where the GMEM system is located is enabled to use a driver of the accelerator device to manage a memory management unit and a physical memory of the accelerator device by means of the memory management unit operation function interface for the accelerator device, so as to read and write data. In the present application, the GMEM system extends a native memory management interface of an operating system into a heterogeneous memory management interface, supporting programming based on a unified virtual address space, and memory management unit operation function interfaces are configured for different types of accelerator devices, so that the device where the GMEM system is located can support the use of different types of accelerator devices, without the need to consider the compatibility of memory interfaces of different types of accelerator devices.

The invention discloses a memory management method and device and computing equipment. The method is executed by a GMEM system, after the GMEM system receives a physical memory range, a memory management unit operation function and an accelerator device address of the accelerator device, a memory management unit operation function interface is configured for the accelerator device, and the device where the GMEM system is located is enabled to operate the function interface through the accelerator device memory management unit. And managing a memory management unit and a physical memory of the accelerator equipment by utilizing a driver of the accelerator equipment so as to read and write data. According to the GMEM system, a native memory management interface of an operating system is expanded into a heterogeneous memory management interface, programming of a unified virtual address space is supported, and memory management unit operation function interfaces are configured for various types of accelerator devices, so that the device where the GMEM system is located can support the use of the various types of accelerator devices, and the operation efficiency of the accelerator devices is improved. And the compatibility problem of memory interfaces of various types of accelerator equipment does not need to be considered.

The invention provides a memory resource access method and device, an address translation method and device, electronic equipment and a storage medium. According to the embodiment of the invention, a virtual machine management component can be used for firstly obtaining a direct memory access request of external equipment to a memory resource mounted under a virtual machine; and searching a target physical address corresponding to the target virtual address of the target memory resource from the data processing unit, so that the external equipment accesses the target memory resource by accessing the target physical address. Wherein a physical address translated by the virtual machine management component for the virtual address of the memory resource in advance is stored in the data processing unit, and the data processing unit performs data communication with the virtual machine management component through a communication drive simulated in the virtual machine management component. By adopting the scheme, the congestion of the shared memory resource (IOTLB) of the memory management unit possibly caused by excessive address query can be avoided, the consumption of the shared memory resource is reduced, and the utilization rate of the shared memory resource is improved.

The invention relates to the technical field of computers, in particular to an incentive generation method and device and a medium, and the incentive generation method comprises the following steps: distributing a first number of multiple physical addresses, and distributing a second number of multiple page table entry addresses; for each virtual address in a third number of virtual addresses needing to be generated, selecting a corresponding target physical address from the plurality of physical addresses and selecting at least one target page table entry address for the target physical address from the plurality of page table entry addresses, determining page table item data and storing the page table item data in a target page table item to generate a corresponding virtual address; and generating excitation for verifying the memory management unit. According to the excitation generation method and device disclosed by the embodiment of the invention, the medium can realize dynamic simulation of flexible allocation of the memory address, strengthen randomized verification of the address and improve the verification coverage rate of the mapping relationship between the page table entries at all levels.

Embodiments of the present application relate to the technical field of computer storage, and provide a resource allocation method and apparatus, an electronic device, and a storage medium. The method comprises: in response to a memory acquisition request sent by a target host, a memory management unit in a resource allocation system acquiring demanded memory capacity and a memory starting address carried by the memory acquisition request; on the basis of a memory allocation unit in the resource allocation system, selecting from among at least two memory modules a target memory module matching the demanded memory capacity; and on the basis of a memory address router in the memory allocation unit and the memory starting address, performing address translation on the target memory module, and allocating to the target host the target memory module having undergone address translation, thereby achieving dynamic resource allocation of the target host. In this way, the interaction between a memory management unit and a memory allocation unit ensures rapid allocation of idle memory modules in a system, thereby improving the utilization rate of memory resources, and reducing costs of usage of the memory resources.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention provides a system memory management unit configuration method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: distributing corresponding external equipment for each virtual machine according to a preset configuration file, and storing the external equipment in a preset table recording the information of the external equipment; acquiring a numerical value of a first specified data bit of a table item corresponding to the distributed external equipment, before the virtual machine is started, setting the numerical value of the first specified data bit as a preset value, and after the virtual machine is started, adjusting the numerical value of the first specified data bit as a first numerical value, the method comprises the following steps: when a virtual machine accesses a memory through an input operation of an external device, obtaining a physical address of the input operation, obtaining a target memory address matched with the physical address of the input operation from a corresponding relationship between the physical address recorded in a page table corresponding to the virtual machine to which the external device belongs and the memory address, and according to the target memory address, storing the target memory address in the external device; and the memory is accessed by the input operation, so that the probability of unsafe memory access is reduced.

Embodiments of this application disclose a memory sharing method and an apparatus. The method in embodiments of this application includes: A host side establishes a first memory page table via a shared virtual address management unit. The first memory page table includes mapping from a virtual address on the host side to a physical address on the host side. A first device side establishes a second memory page table via a shared virtual address agent unit. The second memory page table includes mapping from a virtual address on the first device side to a physical address on the first device side. An agent system memory management unit SMMU on the first device side updates the second memory page table based on the first memory page table, or the host side updates the first memory page table based on the second memory page table.

The invention relates to a safe dynamic loading method for a peripheral adaptive plug-in in an embedded low-resource environment, and belongs to the technical field of plug-in loading. The method comprises the following steps: executing digital signature identity authentication and lightweight increment integrity verification; analyzing the metadata, and distributing a physical isolation memory area by utilizing a memory management unit; initializing and analyzing the peripheral dependency list in the isolation memory, dynamically generating an encryption capability token bound with an isolation domain identifier, and embedding a monitoring hook to verify the authority of the token; performing lightweight behavior auditing during operation, triggering a response mechanism based on a result, and checking a certificate state by using a pre-downloaded certificate revocation list incremental data packet when the system is idle; verifying the new-version plug-in independently, pausing the old-version capture state snapshot, switching the peripheral control right to the new-version plug-in through the atomic operation sequence, recovering the token and safely erasing the memory. The whole mechanism ensures high-security isolation and dynamic protection. The efficient and safe loading and operation of the peripheral adaptive plug-in under the embedded low-resource environment are realized.

The invention provides an accelerator and a request processing method, which can be applied to the technical field of computers. The accelerator comprises: a computing unit configured to send an access request to a target virtual address to a memory management unit; the memory management unit comprises an address translation buffer module, and the memory management unit is configured to respond to the received access request and search a corresponding physical page number in the address translation buffer module according to the target virtual address so as to determine a physical address; wherein the address translation buffer module comprises a plurality of buffer units, and the address translation buffer module is configured to determine a target buffer unit from the plurality of buffer units according to a virtual base address in a target virtual address; and based on address identification information in the target virtual address, searching a physical page number corresponding to the target virtual address from physical page numbers corresponding to the at least two different virtual base addresses stored in the target buffer unit to determine a physical address.

The invention provides a unified memory system based on heterogeneous computing, belongs to the field of parallel computing and artificial intelligence, and realizes memory sharing by constructing a global virtual address space and eliminating explicit data transmission between a host end and an equipment end. The core module comprises: 1) a cache consistency manager, which adopts an adaptive protocol (write broadcast / write invalidation) and a cache directory table (CCDT) to ensure data consistency; 2) an MMU memory management unit which supports dynamic address translation, on-demand distribution and page migration; and 3) an intelligent data migration unit which dynamically migrates the hotspot data to a near-end memory based on the prediction model and reduces the access delay. The architecture is suitable for edge AI applications with high requirements on real-time performance and energy efficiency.

The invention discloses a PCIe ECAM address mapping optimization method and system, and belongs to the technical field of operating system optimization, and the method comprises the steps: formulating a PCIe device region division rule, and dividing a PCIe device into a high-frequency access region device and a low-frequency access region device according to the device distribution condition in a PCIe bus topology based on the rule; the page table allocation comprises static page table pre-allocation and dynamic page table allocation adjustment, based on PCIe device area division, devices in a high-frequency access area are subjected to centralized memory mapping with a large page as the granularity, and devices in a low-frequency access area are subjected to independent memory mapping with a small page as the granularity; and setting an access frequency threshold, monitoring the access frequency of the PCIe equipment configuration space when the system runs, and merging or splitting the page table through the memory management unit. The number of page table items can be remarkably reduced, the hit rate of the TLB is increased, and the overall memory access efficiency of a system is improved.

Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit (105) is coupled between an input-output memory management unit (IOMMU) (120) and an endpoint device (118). The inspection unit (105) stores a registry (330) comprising entries (332) which each correspond to a respective address, and a respective one or more resources of the endpoint device (118). A given entry (332) of the registry (330) is created based on a message from the IOM MU (120) which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device (118) performs a search, based on a DMA request, to determine if any registry (330) entry (332) indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU (120) is contingent on a result of the search.

The embodiment of the invention provides an input and output memory management unit, a memory access method and related equipment, and the input and output memory management unit comprises an input and output translation bypass buffer which comprises a cache table item used for caching a mapping relation between an equipment virtual address and a system physical address carried by a memory access request; an address space identifier of the equipment sending the memory access request is cached in a label item of the cache table item; and when a memory access request is obtained, querying a cache table item of the input / output translation bypass buffer at least based on the sent address space identifier, so as to obtain a system physical address mapped by the cached equipment virtual address in the address item corresponding to the tag item hit by the query. According to the technical scheme provided by the embodiment of the invention, on the basis of ensuring that the function of the input / output translation bypass buffer is realized, the reliability and the safety of determining the physical address of the system between devices can be improved.

The invention provides a hardware auxiliary page table management system and method, a medium, a program product and a terminal. Efficient address translation is achieved through cooperative work of a memory management unit and a memory unit. Comprising the key steps of conversion backup buffer hit detection, guest page table lookup, page traversal cache lookup and the like. After receiving the access instruction, the memory management unit executes detection through a conversion backup buffer hit detection module; and if not, a guest page table search module obtains a corresponding host physical address. And the system executes search in the page traversal cache module, accesses a second-level cache of the memory unit when necessary, and stores a search result into a cache line in a preset format. Transparent conversion of the client page table address in the cache is achieved in a hardware assisting mode, and a complete shadow page table item life cycle management scheme is provided.

An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input / output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the memory that corresponds to an identifier associated with the IO transaction, and control utilization of one or more resources of the IOMMU based on the determined resource control information. Other embodiments are disclosed and claimed.

The invention relates to the field of memory management, and provides a memory allocation method and device for a mobile terminal system. The method comprises the following steps: dividing a DDR (Double Data Rate) memory in the mobile terminal into a plurality of physical blocks through a memory management unit; uniquely numbering the plurality of physical blocks, and establishing a mapping relationship between the virtual address used by the mobile terminal system and the physical numbers corresponding to the plurality of physical blocks through the memory management unit; after receiving a memory allocation request, judging whether a target physical block indicated in the memory allocation request belongs to a single channel of the 16-bit memory; and if the target physical block does not belong to the single channel of the 16-bit memory, remapping a physical number in the memory allocation request into an equivalent physical number in a single channel range, and importing the to-be-allocated data into a corresponding 16-bit memory space through a memory management unit based on the mapping relationship and a virtual address corresponding to the equivalent physical number. The memory allocation efficiency is improved by realizing optimal allocation of the 16-bit memory.

The invention discloses a memory management unit, a processor and a page table caching method, and belongs to the technical field of computers. The memory management unit comprises a cache management module, a conversion backup buffer TLB module and a page table traversal PTW module; the TLB module is configured to cache a page table item; the PTW module is configured to query the page table according to the first virtual address under the condition that the TLB module is queried through the first virtual address and the TLB module is not hit; the cache management module is configured to merge 2n page table entries including a target page table entry to obtain a merged page table entry if the target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is smaller than or equal to a merging threshold value; and caching the merged page table entry into a TLB module. The memory management unit provided by the invention can merge the effective page table entries corresponding to the pages smaller than or equal to the merge threshold, so that the utilization rate and hit rate of the TLB module are improved.

Provided is an accelerator for accelerating batch large language model (LLM) inference via key-value cache compression. An accelerator, according to one embodiment, may comprise a plurality of compute cores. Here, each of the plurality of compute cores may comprise a plurality of processing units for processing an LLM inference operation on a per-token basis, and a direct memory access unit for managing operations of reading weights from a memory and writing key-value activation data back to the memory. In addition, the direct memory access unit may comprise a compression engine for managing online compression of the key-value activation data when the key-value activation data is written to the memory, a decompression engine for decompressing the compressed key-value activation data retrieved from the memory, and a memory management unit for managing reading and writing of the compressed key-value activation data in the memory.

A data copying method, apparatus, computer-readable storage medium, and electronic device are disclosed. The method includes: generating an address translation request via a target virtual machine, the address translation request including an intermediate physical address; converting the intermediate physical address into a physical address via a memory management unit; configuring the physical address in a direct memory access controller via the target virtual machine; and controlling a target module to copy data according to the physical address via the direct memory access controller, the target module including a memory module and / or a peripheral module. Embodiments of this disclosure can reduce chip manufacturing costs.

A memory access method and an input-output memory management unit (IOMMU) are disclosed. The method includes: receiving a memory access request sent by a PCI device, which carrying a virtual address; searching for a physical address corresponding to the virtual address in its IOTLB; in a case that no corresponding physical address is found, broadcasting an address probing message carrying the virtual address to each CPU core; searching for a physical address corresponding to the virtual address in its TLB in response to the address probing message, and sending an address response message carrying the found physical address to the IOMMU after finding the physical address corresponding to the virtual address; and receiving, by the IOMMU, the address response message sent by the CPU core, storing a mapping relationship between the physical address and the virtual address in its IOTLB, and performing memory access based on the physical address.

An address translation system, method and device including a translation extension unit associated with a client and having a client address translation cache storing a client cache of the address translations. When virtual address of a translation request from the client is the same as the virtual address of an address translation of the client cache, the translation extension unit returns the physical address that is mapped to the virtual address according to the address translation to the client without transmitting the translation request to a memory management unit that maintains a page table of all the translations and a translation lookaside buffer with a subset of the translations.

An image processing device according to an embodiment includes: an image division unit dividing input image data into first division image data and second division image data having a predetermined overlap region with the first division image data according to a size of a kernel used for image processing; a reuse data determination unit determining first reuse data reused in performing the image processing to the second division image data among the first division image data; and a memory management unit, in a memory, storing first processed data of a first division image obtained by performing the image processing to the first division image data, in a region other than a region storing the first reuse data, and allocates a region storing the second division image data so as to be adjacent to the region storing the first reuse data.

The embodiment of the invention provides a memory address mapping method, a memory management unit, electronic equipment and a storage medium. The memory address mapping method comprises the following steps: receiving a virtual address from a current process; determining an address field table and an address field attribute table according to the identification information of the current process; base address information is searched from an address field table according to a first virtual address field included in the virtual address, the base address information is used for indicating a base address of a target physical address space segment, and the target physical address space segment is a physical address space segment where a physical address mapped with the virtual address is located; searching offset information from an address field attribute table according to a second virtual address field included in the virtual address, wherein the offset information is used for indicating the offset of a physical address mapped with the virtual address in a target physical address space field; and determining a physical address mapped with the virtual address according to the base address information and the offset information. According to the scheme, the efficiency of mapping the virtual address into the physical address can be improved.

The invention discloses a data transmission method, system and device, a storage medium and a program product, and relates to the technical field of data processing. Determining a target virtual path by adopting a preset flow table rule according to the address of the first processor and the address of the second processor, sending the target data acquisition request to a memory management unit of the second processor by adopting the target virtual path, and receiving target data sent by the memory management unit of the second processor through the target virtual path, according to the method, a virtual path is defined by software, and direct mapping is carried out through a memory address, so that efficient data transmission among different servers is realized, and the data transmission cost is reduced.

A method of reducing page walk latency resulting from a translation lookaside buffer (TLB) miss comprises providing a page fetch / walk logic module disposed between a coherent fabric and a memory controller. Upon receiving a notification of a TLB miss, performing, by the page fetch / walk logic module, a page table walk of a virtual address to produce a corresponding physical address. The method may further comprise forming, by a memory management unit, a TLB request that comprises a virtual address, and a request type field. The request type field may comprise (i) an indication that a TLB miss has occurred and (ii) a specification of a number of stages required of the page table walk.

The invention discloses a firmware switching method and device, equipment and a storage medium, and relates to the technical field of computers, after an upgrading command of an operation and maintenance end is received, integrity verification is firstly carried out on target firmware, it is ensured that the target firmware to be upgraded is legal and then stored in a preset address of a memory, and then the target firmware is upgraded. After the execution of the stored to-be-processed command taken out from the command queue is finished, the firmware initial address is remapped through the memory management unit, so that the service execution of the target equipment directly jumps to the execution of the target firmware without switching to a bootstrap program, and the time for carrying out secondary firmware loading and bootstrap from a bootstrap loading program is saved.

A system controls access to a physical address (PA) space. The system includes multiple system resources addressable within the PA space, and multiple processing circuits executing multiple virtual machines (VMs). A given region of the PA space is dedicated to addressing the VMs. The system also includes multiple memory management units (MMUs) coupled to corresponding processing circuits. A given MMU is operative to translate a virtual address indicated in an access request from a processing circuit into a requested PA that is accessible by the processing circuit according to a configurable setting of the given MMU. The system further includes multiple memory protection units (MPUs). A given MPU, which is coupled to a target system resource allocated with the requested PA, is operative to grant or deny the request based on information indicating whether the requested PA is accessible to a requesting VM executed on the processing circuit.

A neural processing device and a method for using shared page table thereof are provided. The neural processing device including at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to exchange data between the at least one neural processor and the shared memory, comprises at least one processing unit each of which included in each of the at least one neural processor and configured to provide logical addresses, a memory management unit configured to receive and translate the logical addresses into physical addresses, and a physical memory accessible by the physical addresses, wherein the memory management unit comprises a shared page table that has translation information between the logical addresses and the physical addresses and is shared by at least one process with each other.

The invention discloses a memory cross-border positioning method and device and a storage medium, and the method comprises the steps: recognizing a protection memory section which may have a pollution possibility, and distributing continuous memory blocks in front of and behind the protection memory section to obtain a memory protection region, setting the attribute of the memory protection area as a system mode or a non-executable mode; then calling the memory management unit to respond to a CPU access request; and when the response of the memory management unit is abnormal, capturing and positioning a position where memory crossing occurs. By utilizing the characteristic that when a memory is set to be in a read-only mode or a non-executable mode, writing cannot be carried out, when positioning cross-border occurs, a pollution source tries to access a memory protection area, and at the moment, a read-only attribute or a non-executable attribute set in the memory protection area causes insufficient access authority, so that response abnormity occurs; the position where memory crossing occurs can be accurately judged by tracking the error position, memory crossing positioning is achieved, the efficiency of memory crossing positioning is improved, and resource consumption is reduced.