229 results about "Memory management unit" patented technology

Embodiments of the present application relate to the technical field of computer storage, and provide a resource allocation method and apparatus, an electronic device, and a storage medium. The method comprises: in response to a memory acquisition request sent by a target host, a memory management unit in a resource allocation system acquiring demanded memory capacity and a memory starting address carried by the memory acquisition request; on the basis of a memory allocation unit in the resource allocation system, selecting from among at least two memory modules a target memory module matching the demanded memory capacity; and on the basis of a memory address router in the memory allocation unit and the memory starting address, performing address translation on the target memory module, and allocating to the target host the target memory module having undergone address translation, thereby achieving dynamic resource allocation of the target host. In this way, the interaction between a memory management unit and a memory allocation unit ensures rapid allocation of idle memory modules in a system, thereby improving the utilization rate of memory resources, and reducing costs of usage of the memory resources.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention relates to a safe dynamic loading method for a peripheral adaptive plug-in in an embedded low-resource environment, and belongs to the technical field of plug-in loading. The method comprises the following steps: executing digital signature identity authentication and lightweight increment integrity verification; analyzing the metadata, and distributing a physical isolation memory area by utilizing a memory management unit; initializing and analyzing the peripheral dependency list in the isolation memory, dynamically generating an encryption capability token bound with an isolation domain identifier, and embedding a monitoring hook to verify the authority of the token; performing lightweight behavior auditing during operation, triggering a response mechanism based on a result, and checking a certificate state by using a pre-downloaded certificate revocation list incremental data packet when the system is idle; verifying the new-version plug-in independently, pausing the old-version capture state snapshot, switching the peripheral control right to the new-version plug-in through the atomic operation sequence, recovering the token and safely erasing the memory. The whole mechanism ensures high-security isolation and dynamic protection. The efficient and safe loading and operation of the peripheral adaptive plug-in under the embedded low-resource environment are realized.

The invention provides an accelerator and a request processing method, which can be applied to the technical field of computers. The accelerator comprises: a computing unit configured to send an access request to a target virtual address to a memory management unit; the memory management unit comprises an address translation buffer module, and the memory management unit is configured to respond to the received access request and search a corresponding physical page number in the address translation buffer module according to the target virtual address so as to determine a physical address; wherein the address translation buffer module comprises a plurality of buffer units, and the address translation buffer module is configured to determine a target buffer unit from the plurality of buffer units according to a virtual base address in a target virtual address; and based on address identification information in the target virtual address, searching a physical page number corresponding to the target virtual address from physical page numbers corresponding to the at least two different virtual base addresses stored in the target buffer unit to determine a physical address.

The embodiment of the invention provides an input and output memory management unit, a memory access method and related equipment, and the input and output memory management unit comprises an input and output translation bypass buffer which comprises a cache table item used for caching a mapping relation between an equipment virtual address and a system physical address carried by a memory access request; an address space identifier of the equipment sending the memory access request is cached in a label item of the cache table item; and when a memory access request is obtained, querying a cache table item of the input / output translation bypass buffer at least based on the sent address space identifier, so as to obtain a system physical address mapped by the cached equipment virtual address in the address item corresponding to the tag item hit by the query. According to the technical scheme provided by the embodiment of the invention, on the basis of ensuring that the function of the input / output translation bypass buffer is realized, the reliability and the safety of determining the physical address of the system between devices can be improved.

An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input / output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the memory that corresponds to an identifier associated with the IO transaction, and control utilization of one or more resources of the IOMMU based on the determined resource control information. Other embodiments are disclosed and claimed.

The invention relates to the field of memory management, and provides a memory allocation method and device for a mobile terminal system. The method comprises the following steps: dividing a DDR (Double Data Rate) memory in the mobile terminal into a plurality of physical blocks through a memory management unit; uniquely numbering the plurality of physical blocks, and establishing a mapping relationship between the virtual address used by the mobile terminal system and the physical numbers corresponding to the plurality of physical blocks through the memory management unit; after receiving a memory allocation request, judging whether a target physical block indicated in the memory allocation request belongs to a single channel of the 16-bit memory; and if the target physical block does not belong to the single channel of the 16-bit memory, remapping a physical number in the memory allocation request into an equivalent physical number in a single channel range, and importing the to-be-allocated data into a corresponding 16-bit memory space through a memory management unit based on the mapping relationship and a virtual address corresponding to the equivalent physical number. The memory allocation efficiency is improved by realizing optimal allocation of the 16-bit memory.

The invention discloses a memory management unit, a processor and a page table caching method, and belongs to the technical field of computers. The memory management unit comprises a cache management module, a conversion backup buffer TLB module and a page table traversal PTW module; the TLB module is configured to cache a page table item; the PTW module is configured to query the page table according to the first virtual address under the condition that the TLB module is queried through the first virtual address and the TLB module is not hit; the cache management module is configured to merge 2n page table entries including a target page table entry to obtain a merged page table entry if the target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is smaller than or equal to a merging threshold value; and caching the merged page table entry into a TLB module. The memory management unit provided by the invention can merge the effective page table entries corresponding to the pages smaller than or equal to the merge threshold, so that the utilization rate and hit rate of the TLB module are improved.

Provided is an accelerator for accelerating batch large language model (LLM) inference via key-value cache compression. An accelerator, according to one embodiment, may comprise a plurality of compute cores. Here, each of the plurality of compute cores may comprise a plurality of processing units for processing an LLM inference operation on a per-token basis, and a direct memory access unit for managing operations of reading weights from a memory and writing key-value activation data back to the memory. In addition, the direct memory access unit may comprise a compression engine for managing online compression of the key-value activation data when the key-value activation data is written to the memory, a decompression engine for decompressing the compressed key-value activation data retrieved from the memory, and a memory management unit for managing reading and writing of the compressed key-value activation data in the memory.

A data copying method, apparatus, computer-readable storage medium, and electronic device are disclosed. The method includes: generating an address translation request via a target virtual machine, the address translation request including an intermediate physical address; converting the intermediate physical address into a physical address via a memory management unit; configuring the physical address in a direct memory access controller via the target virtual machine; and controlling a target module to copy data according to the physical address via the direct memory access controller, the target module including a memory module and / or a peripheral module. Embodiments of this disclosure can reduce chip manufacturing costs.

An image processing device according to an embodiment includes: an image division unit dividing input image data into first division image data and second division image data having a predetermined overlap region with the first division image data according to a size of a kernel used for image processing; a reuse data determination unit determining first reuse data reused in performing the image processing to the second division image data among the first division image data; and a memory management unit, in a memory, storing first processed data of a first division image obtained by performing the image processing to the first division image data, in a region other than a region storing the first reuse data, and allocates a region storing the second division image data so as to be adjacent to the region storing the first reuse data.

The embodiment of the invention provides a memory address mapping method, a memory management unit, electronic equipment and a storage medium. The memory address mapping method comprises the following steps: receiving a virtual address from a current process; determining an address field table and an address field attribute table according to the identification information of the current process; base address information is searched from an address field table according to a first virtual address field included in the virtual address, the base address information is used for indicating a base address of a target physical address space segment, and the target physical address space segment is a physical address space segment where a physical address mapped with the virtual address is located; searching offset information from an address field attribute table according to a second virtual address field included in the virtual address, wherein the offset information is used for indicating the offset of a physical address mapped with the virtual address in a target physical address space field; and determining a physical address mapped with the virtual address according to the base address information and the offset information. According to the scheme, the efficiency of mapping the virtual address into the physical address can be improved.

A method of reducing page walk latency resulting from a translation lookaside buffer (TLB) miss comprises providing a page fetch / walk logic module disposed between a coherent fabric and a memory controller. Upon receiving a notification of a TLB miss, performing, by the page fetch / walk logic module, a page table walk of a virtual address to produce a corresponding physical address. The method may further comprise forming, by a memory management unit, a TLB request that comprises a virtual address, and a request type field. The request type field may comprise (i) an indication that a TLB miss has occurred and (ii) a specification of a number of stages required of the page table walk.

A system controls access to a physical address (PA) space. The system includes multiple system resources addressable within the PA space, and multiple processing circuits executing multiple virtual machines (VMs). A given region of the PA space is dedicated to addressing the VMs. The system also includes multiple memory management units (MMUs) coupled to corresponding processing circuits. A given MMU is operative to translate a virtual address indicated in an access request from a processing circuit into a requested PA that is accessible by the processing circuit according to a configurable setting of the given MMU. The system further includes multiple memory protection units (MPUs). A given MPU, which is coupled to a target system resource allocated with the requested PA, is operative to grant or deny the request based on information indicating whether the requested PA is accessible to a requesting VM executed on the processing circuit.

A neural processing device and a method for using shared page table thereof are provided. The neural processing device including at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to exchange data between the at least one neural processor and the shared memory, comprises at least one processing unit each of which included in each of the at least one neural processor and configured to provide logical addresses, a memory management unit configured to receive and translate the logical addresses into physical addresses, and a physical memory accessible by the physical addresses, wherein the memory management unit comprises a shared page table that has translation information between the logical addresses and the physical addresses and is shared by at least one process with each other.

A sparse processing unit (SPU) can utilize an onboard memory management unit (MMU), and a cluster of parallel processors to increase the efficiency of processing of sparse workloads. The MMU maps an n-dimensional sparse address space, related to the sparse input, intermediary or output sparse data, to a one-dimensional physical memory layout. The SPU can be added to a host computer system, freeing up the host from having to perform memory management functions for accelerating the processing of the sparse workloads.

The invention provides a memory management method, a memory management unit, a chip and electronic equipment. The memory management method comprises the following steps: receiving a command from main equipment; matching the command with a tag array to obtain a matching result; if matching succeeds, corresponding read address information is generated according to the hit tag, a first memory is accessed according to the read address information to obtain corresponding cache line page table information, and the virtual address information is converted into physical address information according to the cache line page table information; and if the matching fails, initiating a page table reading command for accessing the second memory to obtain corresponding page table information according to the command, obtaining replacement cache line information corresponding to the page table information in the first memory, writing the page table information into the first memory according to the replacement cache line information, and updating the tag array. According to the method, the cache line replacement strategy is preset, so that the hit rate of the page table is increased, and the power consumption and the area of the IOMMU are effectively reduced while the high-performance application requirement is met.

A system for global system memory management unit (SMMU) fault handling, the system comprising: a peripheral device having a guest virtual machine (GVM), the peripheral device configured to access a memory (DDR) through a system memory management unit (SMMU); a hosted hypervisor associated with the peripheral device, the GVM, the SMMU, and the memory (DDR), where, upon identification of a faulty memory transaction and a global SMMU fault issued, the hosted hypervisor is configured to identify that a flow identifier (SID) associated with the global SMMU fault is assigned to the GVM, and the hosted hypervisor is configured to reset only the GVM, and to identify that the flow identifier (SID) associated with the global SMMU fault is assigned to the GVM. And restarting of the complete system is avoided.

A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.

An apparatus to facilitate processing in a multi-tile device is disclosed. The apparatus comprises a plurality of processing tiles, each including a memory device and a plurality of processing resources, coupled to the device memory, and a memory management unit to manage the memory devices in each of the plurality of tiles to perform allocation of memory resources among the memory devices for execution by the plurality of processing resources.

A security module of a processor manages the lifecycle of a device interface of an input / output (I / O) device in a virtualized environment in a secure and trusted manner. For example, the security module is configured to bind a device interface of the I / O device interface to a virtual machine (VM). In response to binding the device interface, the security module is configured to certify at least one of the device interface and the I / O device. In response to certifying at least one of the device interface and the I / O device, the security module is configured to configure an input / output memory management unit (IOMMU) and memory resources associated with the VM.

Compressing a translation lookaside buffer (TLB) tag using a TLB metadata buffer in a processor-based device is disclosed herein. In some aspects, a processor-based apparatus provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer that includes a plurality of TLB metadata buffer entries that store corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request including a virtual address (VA), the MMU generates a TLB entry for the VA in the TLB and stores the active TLB metadata pointer as part of a TLB tag of the TLB entry in place of the TLB metadata of the TLB metadata buffer entry.

The embodiment of the invention provides a memory access method and system of a virtual machine and direct connection equipment, the memory access method of the virtual machine is applied to the direct connection equipment of the virtual machine, an equipment memory management unit is configured on the direct connection equipment, and a system memory management unit is configured on a host machine of the virtual machine; the method comprises the steps that a memory access command is received, and the memory access command carries a virtual address of a virtual machine to be accessed; driving an equipment memory management unit to access a system memory management unit so as to perform address conversion on the virtual address of the to-be-accessed virtual machine, and determining a to-be-accessed host physical address; and the direct connection equipment accesses the memory of the virtual machine according to the to-be-accessed host physical address. Through the dual-memory management unit, the conversion from the virtual address of the virtual machine to the physical address of the host is realized, and the complexity of address conversion is reduced.

A system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture, wherein the system comprises: a plurality of processor cores arranged within a processor structure and configured to perform computational tasks in parallel; a linking network that operationally connects the plurality of processor cores for data communication; a context capture unit connected to each of the plurality of processing cores and configured to monitor execution parameters such as instruction throughput, cache access behavior, memory latency, and data exchange characteristics between the cores, wherein the context capture unit generates context descriptors that are representative of the runtime execution conditions;a scheduling processor operationally connected to the context capture unit and configured to distribute computational tasks across the multitude of processor cores based on the generated context descriptors; and a memory management unit operationally connected to a hierarchical memory arrangement comprising multiple cache levels and main memory, the memory management unit being configured to dynamically allocate and migrate data segments across the hierarchical memory arrangement according to the context descriptors, thus achieving alignment between task execution and data locality.

The present application relates to devices and components, including apparatus, systems, and methods for scheduling delivery and execution of page fault or permission fault exceptions. A memory management unit may receive a virtual address associated with an execution mode and initiate a virtual-to-physical translation operation. The MMU may detect a first condition associated with a search of the virtual address in a translation lookaside buffer (TLB). In response to the detection of the first condition, MMU may start a timer. MMU may detect a fault exception associated with the translation operation of the virtual address and determine that a second condition is satisfied. In response to detecting the second condition, the MMU or the reorder buffer exception monitor may deliver the fault exception based on the timer.

This application discloses a data processing apparatus and a data processing method, relating to the field of data processing technology. The apparatus includes a processor, memory units, and input / output interfaces. The processor includes a kernel, a memory management unit, registers, a level 1 cache unit, and a level 2 cache unit. The apparatus further includes: a cache partitioning control module, used to determine a second target cache block in the level 1 cache unit corresponding to the secure computing program and a first target cache block in the level 2 cache unit when the general computing program and the secure computing program are executed in parallel; a memory partitioning control module, used to determine a target memory block corresponding to the secure computing program; and an input / output interface partitioning control module, used to determine a target input / output interface corresponding to the secure computing program. The registers include a first register corresponding to the general computing program and a second register corresponding to the secure computing program, enabling the kernel to run the general computing program and the secure computing program in parallel.

The embodiment of the invention provides an accelerator, an input and output memory management unit and a related device and method, and the accelerator comprises the steps that a receiving unit sequentially receives a first translation request and a second translation request, and virtual page numbers corresponding to the first translation request and the second translation request are recorded in the same first page table item; the query unit queries whether a first page table item exists in a first translation backup buffer area of the first-level cache or not, if not, the first page table item is obtained from the outside of the first translation backup buffer area, and the first translation request is sent to the prefetching unit; and the duplicate removal unit associates the second translation request with the first translation request, and obtains a translation result from the first page table item after the query unit obtains the first page table item. And the prefetching unit initiates a prefetching operation after the prefetching training is completed, obtains a second page table item of the predicted translation request, and stores the second page table item into a second translation backup buffer area of the second-level cache. According to the scheme, the efficiency of virtual address translation can be improved.

The invention discloses a permission adjustment method, device and equipment and a computer readable storage medium, and is applied to the technical field of computing, and the method comprises the steps: obtaining the access frequency of a heap area in a virtual address, the number of errors of physical address permission detection, and the code exception jump condition; determining a corresponding control signal according to the access frequency, the error number and the code exception jump condition; the control signal comprises an authority change signal and a process freezing signal; dynamically adjusting the physical memory authority of the memory management unit according to the control signal; the dynamic adjustment includes adjusting read or write or execution permissions of the physical page, and disrupting an access sequence of the translation lookaside buffer cache. According to the method, the limitation that traditional static permission configuration cannot adapt to the dynamic running state of the process is solved; and the MMU cannot detect and block hostile attacks in real time, so that the safety and the flexibility of MMU authority management are improved.

The present application relates to an artificial intelligence chip, a method for virtual address conversion, a computing device, a computer readable storage medium and a computer program product. The artificial intelligence chip comprises: an address cache bank arranged before a memory management unit and comprising a plurality of address caches, the address cache bank being configured to perform hit and miss detection on virtual addresses associated with read / write requests from a plurality of computing units to obtain corresponding physical addresses; the memory management unit being configured to query virtual addresses missed by the address cache bank and provide the queried corresponding physical addresses to the address cache bank; and the plurality of computing units being configured to perform calculations and provide read / write requests to the address cache bank. The present application can significantly reduce arbitration conflicts between multiple requests and improve the conversion efficiency of virtual addresses to physical addresses and the performance of the chip.

The application relates to the field of memory management, and provides a memory allocation method and device of a mobile terminal system. The method comprises the following steps: dividing a DDR memory in the mobile terminal into a plurality of physical blocks through a memory management unit; numbering the plurality of physical blocks uniquely, and establishing a mapping relationship between a virtual address used by the mobile terminal system and a physical number corresponding to each of the plurality of physical blocks through the memory management unit; after receiving a memory allocation request, judging whether a target physical block indicated in the memory allocation request belongs to a single channel of 16-bit memory; if the target physical block does not belong to the single channel of 16-bit memory, remapping the physical number in the memory allocation request into an equivalent physical number within the single channel range, and guiding to-be-allocated data into corresponding 16-bit memory space based on the mapping relationship and a virtual address corresponding to the equivalent physical number through the memory management unit. The optimized allocation of 16-bit memory is realized, and the memory allocation efficiency is improved.